DE3587682D1 - Verfahren zur Hemmung von Ausdiffusion von Dotierstoffen. - Google Patents

Verfahren zur Hemmung von Ausdiffusion von Dotierstoffen.

Info

Publication number
DE3587682D1
DE3587682D1 DE85400680T DE3587682T DE3587682D1 DE 3587682 D1 DE3587682 D1 DE 3587682D1 DE 85400680 T DE85400680 T DE 85400680T DE 3587682 T DE3587682 T DE 3587682T DE 3587682 D1 DE3587682 D1 DE 3587682D1
Authority
DE
Germany
Prior art keywords
outdiffusion
dopants
inhibiting
inhibiting outdiffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE85400680T
Other languages
English (en)
Other versions
DE3587682T2 (de
Inventor
Michael E Thomas
Madhukar B Vora
Ashok K Kapoor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corp filed Critical Fairchild Semiconductor Corp
Application granted granted Critical
Publication of DE3587682D1 publication Critical patent/DE3587682D1/de
Publication of DE3587682T2 publication Critical patent/DE3587682T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/034Diffusion of boron or silicon
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/909Controlled atmosphere

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE3587682T 1984-04-13 1985-04-05 Verfahren zur Hemmung von Ausdiffusion von Dotierstoffen. Expired - Lifetime DE3587682T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/600,163 US4640004A (en) 1984-04-13 1984-04-13 Method and structure for inhibiting dopant out-diffusion

Publications (2)

Publication Number Publication Date
DE3587682D1 true DE3587682D1 (de) 1994-01-27
DE3587682T2 DE3587682T2 (de) 1994-06-23

Family

ID=24402552

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3587682T Expired - Lifetime DE3587682T2 (de) 1984-04-13 1985-04-05 Verfahren zur Hemmung von Ausdiffusion von Dotierstoffen.

Country Status (5)

Country Link
US (1) US4640004A (de)
EP (2) EP0159935B1 (de)
JP (1) JPH065667B2 (de)
CA (1) CA1219687A (de)
DE (1) DE3587682T2 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2555364B1 (fr) * 1983-11-18 1990-02-02 Hitachi Ltd Procede de fabrication de connexions d'un dispositif a circuits integres a semi-conducteurs comportant en particulier un mitset
EP0214690B1 (de) * 1985-09-06 1992-03-25 Philips Electronics Uk Limited Herstellungsverfahren einer Halbleitervorrichtung
JPH0783034B2 (ja) * 1986-03-29 1995-09-06 株式会社東芝 半導体装置
US4727045A (en) * 1986-07-30 1988-02-23 Advanced Micro Devices, Inc. Plugged poly silicon resistor load for static random access memory cells
JPH0677158B2 (ja) * 1986-09-03 1994-09-28 株式会社日立製作所 電子写真感光体
JPS6373660A (ja) * 1986-09-17 1988-04-04 Fujitsu Ltd 半導体装置
US4884123A (en) * 1987-02-19 1989-11-28 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
CA1306072C (en) * 1987-03-30 1992-08-04 John E. Cronin Refractory metal - titanium nitride conductive structures and processes for forming the same
JP2624736B2 (ja) * 1988-01-14 1997-06-25 株式会社東芝 半導体装置の製造方法
US4962414A (en) * 1988-02-11 1990-10-09 Sgs-Thomson Microelectronics, Inc. Method for forming a contact VIA
US4998157A (en) * 1988-08-06 1991-03-05 Seiko Epson Corporation Ohmic contact to silicon substrate
US4897287A (en) * 1988-10-06 1990-01-30 The Boc Group, Inc. Metallization process for an integrated circuit
JPH02141569A (ja) * 1988-11-24 1990-05-30 Hitachi Ltd 超伝導材料
US5221853A (en) * 1989-01-06 1993-06-22 International Business Machines Corporation MOSFET with a refractory metal film, a silicide film and a nitride film formed on and in contact with a source, drain and gate region
US5202287A (en) * 1989-01-06 1993-04-13 International Business Machines Corporation Method for a two step selective deposition of refractory metals utilizing SiH4 reduction and H2 reduction
US5084417A (en) * 1989-01-06 1992-01-28 International Business Machines Corporation Method for selective deposition of refractory metals on silicon substrates and device formed thereby
US5075761A (en) * 1989-05-31 1991-12-24 Sgs-Thomson Microelectronics, Inc. Local interconnect for integrated circuits
US5164333A (en) * 1990-06-19 1992-11-17 Siemens Aktiengesellschaft Method for manufacturing a multi-layer gate electrode for a mos transistor
US5034348A (en) * 1990-08-16 1991-07-23 International Business Machines Corp. Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit
EP0517368B1 (de) * 1991-05-03 1998-09-16 STMicroelectronics, Inc. Lokalverbindungen für integrierte Schaltungen
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5858868A (en) * 1992-05-08 1999-01-12 Yamaha Corporation Method of manufacturing a laminated wiring structure preventing impurity diffusion therein from N+ and P+ regions in CMOS device with ohmic contact
US5369304A (en) * 1992-08-14 1994-11-29 Motorola, Inc. Conductive diffusion barrier of titanium nitride in ohmic contact with a plurality of doped layers therefor
US5364803A (en) * 1993-06-24 1994-11-15 United Microelectronics Corporation Method of preventing fluorine-induced gate oxide degradation in WSix polycide structure
US5356837A (en) * 1993-10-29 1994-10-18 International Business Machines Corporation Method of making epitaxial cobalt silicide using a thin metal underlayer
DE4337355C2 (de) * 1993-11-02 1997-08-21 Siemens Ag Verfahren zur Herstellung eines Kontaktlochs zu einem dotierten Bereich
US5403778A (en) * 1994-01-06 1995-04-04 Texas Instruments Incorporated Limited metal reaction for contact cleaning and improved metal-to-metal antifuse contact cleaning method
US5652183A (en) * 1994-01-18 1997-07-29 Matsushita Electric Industrial Co., Ltd. Method for fabricating semiconductor device containing excessive silicon in metal silicide film
JP3045946B2 (ja) * 1994-05-09 2000-05-29 インターナショナル・ビジネス・マシーンズ・コーポレイション 半導体デバイスの製造方法
US5504041A (en) * 1994-08-01 1996-04-02 Texas Instruments Incorporated Conductive exotic-nitride barrier layer for high-dielectric-constant materials
US5614437A (en) * 1995-01-26 1997-03-25 Lsi Logic Corporation Method for fabricating reliable metallization with Ta-Si-N barrier for semiconductors
JPH098297A (ja) * 1995-06-26 1997-01-10 Mitsubishi Electric Corp 半導体装置、その製造方法及び電界効果トランジスタ
EP0751566A3 (de) 1995-06-30 1997-02-26 Ibm Metalldünnschichtbarriere für elektrische Verbindungen
JPH0974195A (ja) * 1995-07-06 1997-03-18 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
US5916634A (en) * 1996-10-01 1999-06-29 Sandia Corporation Chemical vapor deposition of W-Si-N and W-B-N
TW400579B (en) * 1997-03-24 2000-08-01 United Microelectronics Corp Method for manufacturing semiconductor device with titanium nitride
US8957511B2 (en) 2005-08-22 2015-02-17 Madhukar B. Vora Apparatus and methods for high-density chip connectivity
US7745301B2 (en) 2005-08-22 2010-06-29 Terapede, Llc Methods and apparatus for high-density chip connectivity
KR100650858B1 (ko) * 2005-12-23 2006-11-28 주식회사 하이닉스반도체 플래쉬 메모리 소자의 제조 방법
CN106158654B (zh) * 2015-04-20 2019-04-26 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法

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Publication number Priority date Publication date Assignee Title
US3614547A (en) * 1970-03-16 1971-10-19 Gen Electric Tungsten barrier electrical connection
US3879746A (en) * 1972-05-30 1975-04-22 Bell Telephone Labor Inc Gate metallization structure
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
US4228212A (en) * 1979-06-11 1980-10-14 General Electric Company Composite conductive structures in integrated circuits
JPS5680144A (en) * 1979-12-06 1981-07-01 Fujitsu Ltd Preparation of semiconductor device
US4344223A (en) * 1980-11-26 1982-08-17 Western Electric Company, Inc. Monolithic hybrid integrated circuits
EP0077813B1 (de) * 1981-05-04 1986-02-05 Motorola, Inc. Mehrschichtenmetallisierung mit niedrigem spezifischen widerstand für halbleiteranordnungen und herstellungsverfahren
JPS57207377A (en) * 1981-06-15 1982-12-20 Nec Corp Manufacture of semiconductor device
JPS5877257A (ja) * 1981-11-04 1983-05-10 Hitachi Ltd 超高信頼性電極

Also Published As

Publication number Publication date
CA1219687A (en) 1987-03-24
EP0159935A2 (de) 1985-10-30
JPH065667B2 (ja) 1994-01-19
EP0568108A1 (de) 1993-11-03
US4640004A (en) 1987-02-03
JPS616822A (ja) 1986-01-13
EP0159935B1 (de) 1993-12-15
DE3587682T2 (de) 1994-06-23
EP0159935A3 (en) 1989-07-19

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