DE2806518A1 - ARRANGEMENT FOR CONNECTING AND PACKING AT LEAST ONE SEMICONDUCTOR BODY - Google Patents

ARRANGEMENT FOR CONNECTING AND PACKING AT LEAST ONE SEMICONDUCTOR BODY

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Publication number
DE2806518A1
DE2806518A1 DE19782806518 DE2806518A DE2806518A1 DE 2806518 A1 DE2806518 A1 DE 2806518A1 DE 19782806518 DE19782806518 DE 19782806518 DE 2806518 A DE2806518 A DE 2806518A DE 2806518 A1 DE2806518 A1 DE 2806518A1
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DE
Germany
Prior art keywords
arrangement according
conductor tracks
substrate
semiconductor body
metal part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19782806518
Other languages
German (de)
Inventor
Anton Dipl Phys Kaiser
Helmut Dipl Ing Keller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Priority to DE19782806518 priority Critical patent/DE2806518A1/en
Priority to GB7904609A priority patent/GB2014786B/en
Publication of DE2806518A1 publication Critical patent/DE2806518A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01076—Osmium [Os]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Multi-Conductor Connections (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

A 4 4 £, A 4 £ 4,

26Q651826Q6518

Stand der TechnikState of the art

Die Erfindung geht aus von einer Anordnung zum Anschluß und Verpacken mindestens eines Halbleiterkörpers nach der Gattung des Hauptanspruchs. Derartige Anordnungen sind aus der DE-OS 22 14 163 und aus der DE-OS 22 26 395 bekannt. Bei diesen Anordnungen ist der Halbleiterkörper entweder auf das nichtleitende Substrat oder auf eine der auf dieses Substrat aufgebrachten Leiterbahnen aufgebracht. In beiden Fällen ergeben sich häufig Schwierigkeiten bei der Ableitung der in dem Halbleiterkörper entstehenden Verlustwärme. Diese Schwierigkeiten lassen sich in dem zuletzt genannten Fall zwar teilweise dadurch beheben, daß möglichst dicke Leiterbahnen verwendet werden. Dies hat aber wiederum den Nachteil, daß die aus einer hohen Anschlußdichte des Halbleiterkörpers resultierenden feinen Anschlußfingergeometrien aus der dicken Metallkaschierung dann nicht mehr ausgeätzt werden können.The invention is based on an arrangement for connecting and packaging at least one semiconductor body of the type of the main claim. Such arrangements are known from DE-OS 22 14 163 and DE-OS 22 26 395. at In these arrangements, the semiconductor body is either on the non-conductive substrate or on one of the on this Substrate applied conductor tracks applied. In both In cases, difficulties often arise in the dissipation of the heat loss occurring in the semiconductor body. These Difficulties in the last-mentioned case can be partially remedied by making conductor tracks that are as thick as possible be used. However, this in turn has the disadvantage that the result of a high connection density of the semiconductor body The resulting fine connecting finger geometries from the thick metal lamination can then no longer be etched out.

Vorteile der ErfindungAdvantages of the invention

Die erfindungsgemäße Anordnung mit den kennzeichnenden Merkmalen des Hauptanspruchs hat demgegenüber den Vorteil, daß eine gute Wärmeabfuhr gewährleistet wird. Außerdem sind die Herstellungs- und Investitionskosten gering. Durch die Form der Anordnung sind günstige Anwendungs- und Weiterverarbeitungsmöglichkeiten gegeben.The arrangement according to the invention with the characterizing features The main claim has the advantage that good heat dissipation is guaranteed. Also are the manufacturing and investment costs are low. Due to the shape of the arrangement, there are favorable application and further processing options given.

Zeichnungdrawing

Ausführungsbeispxele der Erfindung sind in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert. Fig. 1, 3, 5 zeigen die Aufsicht der Beispiele, Fig. 2, 4, 6 deren Schnitt nach der Linie A-B der Fig. 1, 3, 5·Exemplary embodiments of the invention are shown in the drawing and in more detail in the description below explained. 1, 3, 5 show the top view of the examples, FIGS. 2, 4, 6 their section along the line A-B of FIGS. 1, 3, 5.

- 3 _ 9Q8835/002g- 3 _ 9Q8835 / 002g

, 28Q6516, 28Q6516

Beschreibung der ErfindungDescription of the invention

In Fig. 1 und 2 wird das Substrat 5S auf das die Leiterbahnen 6 aufgebracht sind, mit einem z.B. kreisförmigen Ausschnitt 12 versehen. Auf die Unterseite des Substrats 5 wird dann ein Metallteil H so geklebt j daß von diesem der Ausschnitt 12 überdeckt wird. Dadurch ist es möglich, den Halbleiterkörper 1 direkt auf das massive Metallteil Ί im Bereich des Ausschnittes 12 aufzubringen und damit eine sehr günstige Wärmeabfuhr zu erreichen. Die Leiterbahnen 6, die über die Verbindungsteile 3 mit den Anschlußflecken 2 des Halbleiterkörpers 1 verbunden sind, können aus einer dünnen und leicht ätzbaren Metallfolie bestehen. Hierdurch sind feine Leiterbahnenstrukturen leicht herstellbar, d.h. auf begrenztem Raum können viele einzelne Verbindungen mit dem Halbleiterkörper hergestellt werden. Das Metallteil 4 wird zur verbesserten Wärmeabfuhr vorzugsweise mi£ der öffnung 9 auf einen Kühlkörper so aufgebracht, daß sich zwischen beiden ein guter Wärmekontakt ergibt. Zum Schutz der Anordnung ist eine Abdeckung.aus Kunststoffmaterial 8 vorgesehen, welche durch die Form 7 begrenzt ist.In FIGS. 1 and 2, the substrate 5 S to which the conductor tracks 6 are applied is provided with a, for example, circular cutout 12. A metal part H is then glued to the underside of the substrate 5 in such a way that the cutout 12 is covered by it. This makes it possible to apply the semiconductor body 1 directly to the solid metal part Ί in the region of the cutout 12 and thus to achieve very favorable heat dissipation. The conductor tracks 6, which are connected to the connection pads 2 of the semiconductor body 1 via the connecting parts 3, can consist of a thin and easily etchable metal foil. As a result, fine conductor track structures can be easily produced, ie many individual connections can be made to the semiconductor body in a limited space. For improved heat dissipation, the metal part 4 is preferably applied to a heat sink with the opening 9 in such a way that there is good thermal contact between the two. To protect the arrangement, a cover made of plastic material 8, which is delimited by the mold 7, is provided.

Die vom Halbleiterkörper 1 wegführenden Leiterbahnen 6 werden zweckmäßigerweise an eine oder mehrere Seiten des Substrats 5 kammförmig herangeführt. Ist ein solcher Anschlußkamm nur an eine Seite herangeführt, so kann dieses Substrat in den Schlitz eines anderen Substrates gesteckt werden. Wenn entsprechend dem Anschlußkamm des ersten Substrates 5 an diesen Schlitz - ebenfalls Leiterbahnen herangeführt sind, so können die Leiterbahnen beider Substrate z.B. mittels bekannter Löttechniken verbunden werden. Es ist aber auch -möglich, einen solchen Anschlußkamm mit einem weiteren freitragenden und den Rand des Substrates überragenden Kamm zu verbinden und diesen in vorgesehene Bohrungen eines anderen Substrates einzuführen und mit dortigen Leiterbahnen zu verbinden. Wenn die vom Halbleiterkörper 1 wegführenden Leiterbahnen 6 an zwei oder mehrThe conductor tracks 6 leading away from the semiconductor body 1 are expediently connected to one or more sides of the Substrate 5 brought in a comb shape. Is such a connection comb only brought up to one side, this substrate can be inserted into the slot of another substrate will. If, in accordance with the connecting comb of the first substrate 5, this slot is also brought up to conductor tracks the conductor tracks of both substrates can be connected e.g. by means of known soldering techniques. But it is also possible to have such a connection comb with a further self-supporting structure and the edge of the substrate to connect superior comb and introduce this into holes provided in another substrate and with to connect conductor tracks there. If the conductor tracks 6 leading away from the semiconductor body 1 are connected to two or more

909835/0025909835/0025

Seiten des Substrates 5 geführt werden, sind solche zusätzlichen und über das Substrat 5 hinausstehenden Kämme sinnvoll verwendbar j wenn diese im Winkel von 90 nach oben oder unten gebogen sind und dadurch auch z.B. in Bohrungen anderer Substrate einsetzbar werden. In Fig. 3 und 4 ist ein den Substratrand überragender und zusätzlich auf die Leiterbahnen 6 aufgebrachter Kamm 10 aufgeführt, dessen lediglich der einfachen Aufbringung dienender Steg 10a anschließend abgetrennt wird. In der Herstellung und Verarbeitung solcher Teile ist es vorteilhaft, die Substrate, Kämme und Metallteile möglichst lange in zusammenhängender Streifenform zu halten. Durch die mit 10a, 11, 13 und 13a gekennzeichneten Stege, die bei Bedarf abgetrennt werden, können die Substrate 5 ebenso wie die zusätzlichen Kämme 10 und die Metallteile h in Streifenform verarbeitet" werden.Sides of the substrate 5 are guided, such additional combs protruding beyond the substrate 5 are useful if they are bent upwards or downwards at an angle of 90 and can therefore also be used, for example, in bores in other substrates. In FIGS. 3 and 4, a comb 10 protruding beyond the edge of the substrate and additionally applied to the conductor tracks 6 is shown, the web 10a of which is then severed, merely serving for simple application. In the manufacture and processing of such parts, it is advantageous to keep the substrates, combs and metal parts in continuous strip form for as long as possible. The substrates 5 as well as the additional combs 10 and the metal parts h can be processed in strip form by means of the webs marked 10a, 11, 13 and 13a, which are separated off if necessary.

In Fällen bei denen das Substrat 5 schlecht stanzbar oder bohrbar ist und somit ein Ausschnitt 12 nur schwer erreichbar ist, kann es zweckmäßig sein, wie in Fig. 5 gezeigt, auf diesen zu verzichten und den Halbleiterkörper direkt auf das Metallteil 4 nahe dem Rand des Substrates zu setzen. Die Leiterbahnen 6 werden dann ebenfalls kammförmig an den dem Halbleiterkörper naheliegenden Rand geführt und wie zuvor über Verbindungsteile 3 mit den Anschlußflecken 2 verbunden. Damit für die Form 7 kein zu großer Spalt beim Überragen über das Substrat entsteht, kann das Metallteil 4 entsprechend Fig. 6 geformt sein. In der Fig. 5 sind die zuvor beschriebenen Teile wie Kamm 10 Form 7, Kunststoffmasse 8 und Stege 11, 13, 13a weggelassen.In cases in which the substrate 5 is difficult to punch or drill and thus a cutout 12 can only be reached with difficulty it can be expedient, as shown in FIG. 5, to dispense with this and the semiconductor body to put directly on the metal part 4 near the edge of the substrate. The conductor tracks 6 are then also comb-shaped guided to the edge close to the semiconductor body and, as before, via connecting parts 3 with the connection pads 2 connected. So that there is no too large a gap for the mold 7 when it protrudes over the substrate, the metal part 4 can be shaped according to FIG. 6. In Fig. 5, the above-described parts are as Comb 10 shape 7, plastic compound 8 and webs 11, 13, 13a omitted.

In Fortführung dieser Anordnungen kann es auch vorteilhaft sein, das Substrat 5 mit seinen Leiterbahnen 6 durch eine sogenannte flexible Leiterplatte zu ersetzen. Dieses Verfahren ermöglicht es, den in beschriebener Weise hiermit verbundenen Halbleiterkörper direkt mittels hierzu bekann-As a continuation of these arrangements, it can also be advantageous to pass the substrate 5 with its conductor tracks 6 through to replace a so-called flexible printed circuit board. This method makes it possible to use the described method connected semiconductor body directly by means of this known

909835/0025909835/0025

— C —- C -

44 4 344 4 3

28Q651828Q6518

ter Verfahren mit anderen Schaltelementen wie Stecker und Leiterplatten einfach und schnell zu verbinden. Wird dieses Verfahren z.B. bei Fig. 1 bzw. 5 angewandt, so kann die auf einem entfernten Kühlkörper sitzende Anordnung über eine entsprechend lang ausgebildete flexible Leiterplatte direkt ohne zusätzliche Leitungen mit einem anderen z.B. auf einer herkömmlichen Leiterplatte sitzenden Schaltungsteil verbunden werden.ter process with other switching elements such as plugs and Connect circuit boards quickly and easily. If this method is used, for example, in Fig. 1 or 5, then the arrangement seated on a remote heat sink via a flexible printed circuit board of corresponding length directly without additional lines with another circuit part, e.g. sitting on a conventional printed circuit board get connected.

Selbstverständlich ist es auch möglich, mehrere Halbleiterkörper in der beschriebenen Form zu verarbeiten oder zusätzliche diskrete Bauelemente auf das Substrat aufzubringen und mit den Leiterbahnen zu verbinden, so daß hochfrequenzmäßig optimale Anordnungen erreichbar sind.Of course, it is also possible to have a plurality of semiconductor bodies to process in the form described or to apply additional discrete components to the substrate and to be connected to the conductor tracks, so that in terms of high frequency optimal arrangements are achievable.

909835/0025909835/0025

Claims (1)

28Ü651828Ü6518 R. Ά 4«8R. Ά 4 «8 12.1.1978 Bt/HmJanuary 12, 1978 Bt / Hm Robert Bosch GmbH, StuttgartRobert Bosch GmbH, Stuttgart AnsprücheExpectations 1.)Anordnung zum Anschluß und Verpacken mindestens eines Halbleiterkörpers, der an einer Oberflächenseite eine Vielzahl elektrischer Anschlußkontakte hat, mit einer entsprechenden Anzahl von auf ein nichtleitendes Substrat aufgebrachten Leiterbahnen, die mit den Anschlußkontakten •des Halbleiterkörpers elektrisch leitend verbunden sind, dadurch gekennzeichnet, daß der Halbleiterkörper (1) auf ein untergeklebtes Metallteil (4) aufgebracht ist.1.) Arrangement for connecting and packing at least one Semiconductor body which has a plurality of electrical connection contacts on one surface side, with a corresponding number of conductor tracks applied to a non-conductive substrate, which are connected to the connection contacts • the semiconductor body are electrically conductively connected, characterized in that the semiconductor body (1) on an under-glued metal part (4) is applied. 2. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß der Halbleiterkörper (1) auf ein untergeklebtes und durch einen Ausschnitt im Substrat (5) zugängliches Metallteil (4) aufgebracht ist.2. Arrangement according to claim 1, characterized in that the semiconductor body (1) on a glued underneath and through a cutout in the substrate (5) accessible metal part (4) is applied. 3. Anordnung nach Anspruch I9 dadurch gekennzeichnet, daß der Halbleiterkörper (1) auf ein das Substrat (5) überragendes Stück des untergeklebten Metallteils (4) aufgebracht ist.3. Arrangement according to claim I 9, characterized in that the semiconductor body (1) is applied to a piece of the metal part (4) which is glued underneath that protrudes beyond the substrate (5). 909835/0026909835/0026 4 4 4g - 2 - 4 4 4g - 2 - 4. Anordnung nach Anspruch 3, dadurch gekennzeichnet 3 daß durch die Formgebung des Metallteils (4) die. Montagefläche des Halbleiterkörpers (1) mindestens annähernd in einer Ebene mit der die Leiterbahnen (6) tragenden Substratfläche (5) liegt.4. Arrangement according to claim 3, characterized 3 that the shape of the metal part (4). The mounting surface of the semiconductor body (1) lies at least approximately in one plane with the substrate surface (5) carrying the conductor tracks (6). 5. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß das die Leiterbahnen (6) tragende Substrat aus keramischem Mate- " rial besteht und daß die Leiterbahnen (6) durch ein aufgebrachtes Formteil oder mittels selektiv aufgebrachter Leiterbahnen hergestellt sind.5. Arrangement according to claim 1, characterized in that the conductor tracks (6) carrying the substrate made of ceramic mate- " rial and that the conductor tracks (6) by an applied molded part or by means of selectively applied conductor tracks are made. 6. Anordnung nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, daß die an eine oder mehrere Seiten des Substrats (5) führenden Leiterbahnen (6) unmittelbar oder mittelbar zum Anschluß an andere Schaltungsteile verwendet werden.6. Arrangement according to one of claims 1 to 5, characterized in that that the conductor tracks (6) leading to one or more sides of the substrate (5) directly or indirectly to the connection can be used on other parts of the circuit. 7. Anordnung nach einem der Ansprüche 1, 2, 3, 4, 6, dadurch gekennzeichnet, daß das Substrat (5) mit seinen Leiterbahnen (6) durch eine flexible Leiterplatte dargestellt wird.7. Arrangement according to one of claims 1, 2, 3, 4, 6, characterized in that the substrate (5) with its conductor tracks (6) is represented by a flexible printed circuit board. 8. Anordnung nach einem der Ansprüche I9 2, 3» 4, 6, 7» dadurch gekennzeichnet, daß zusätzlich ein das Substrat (5) überragender Kamm (10), der mit den an die Seite geführten Leiterbahnen (6) verbunden ist, zur unmittelbaren Verbindung mit anderen Schaltungsteilen verwendet wird.8. Arrangement according to one of claims I 9 2, 3 »4, 6, 7» characterized in that in addition a substrate (5) projecting comb (10) which is connected to the conductor tracks (6) led to the side, is used for direct connection with other circuit parts. 909835/0025 - 3 -909835/0025 - 3 - 26065182606518 At.4 ί At .4 ί — "Z — - "Z - 9. Anordnung nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, daß das den Halbleiterkörper (1) tragende Metallteil (1J) mit einem zusätzlichen Kühlkörper in Verbindung gebracht ist.9. Arrangement according to one of claims 1 to 8, characterized in that the metal part ( 1 J) carrying the semiconductor body (1) is brought into connection with an additional heat sink. 10. Verfahren zur Herstellung einer Anordnung nach einem der Ansprüche. 1, 2, 3» M, 6, dadurch gekennzeichnet, daß die Leiterbahnen (6) als fertiges Formteil auf das Substrat (5) aufgeklebt werden.10. A method for producing an arrangement according to one of the claims. 1, 2, 3 »M, 6, characterized in that the Conductor tracks (6) are glued onto the substrate (5) as a finished molded part. 11. Verfahren zur Herstellung einer Anordnung nach einem der Ansprüche 1 bis 9, dadurch gekennzeichnet, daß die aufeinander gefügten Bestandteile zunächst in Streifenform verarbeitet werden, wobei die einzelnen Teile vorzugsweise durch SollbruchsteIlen verbunden werden, und daß das Auftrennen durch Brechen, Stanzen oder Sägen erfolgt.11. A method for producing an arrangement according to any one of claims 1 to 9, characterized in that the one on top of the other Joined components are first processed in strip form, the individual parts preferably by Predetermined breaking points are connected, and that the separation is done by breaking, punching or sawing. 12. Anordnung nach einem der Ansprüche 1 bis 9, gekennzeichnet durch eine den Halbleiterkörper (1) und seine Verbindungsteile (3) zu den Leiterbahnen (6) abdeckende Kunststoffmasse (8).12. Arrangement according to one of claims 1 to 9 , characterized by the semiconductor body (1) and its connecting parts (3) to the conductor tracks (6) covering plastic compound (8). 13. Anordnung nach einem der Ansprüche 1 bis 9 und 12, gekennzeichnet durch eine den Halbleiterkörper (1) und seine Verbindungsteile (3) zu den Leiterbahnen (6) abdeckende Abdeckkappe.13. Arrangement according to one of claims 1 to 9 and 12, characterized by one covering the semiconductor body (1) and its connecting parts (3) to the conductor tracks (6) Cover cap. 909835/0025909835/0025 280'SS T 8 -n- 280'SS T 8 -n- 14. Anordnung nach Anspruch 12, dadurch gekennzeichnet, daß die Kunststoffmasse (8) durch ein aufgeklebtes und eine
Schutzfunktion ausübendes Formteil (7) begrenzt ist.14. The arrangement according to claim 12, characterized in that the plastic mass (8) by a glued on and a
Protective function exercising molded part (7) is limited. 15. Verfahren zur Herstellung einer Anordnung nach Anspruch 12, dadurch gekennzeichnet, daß zur Begrenzung der Kunststoffmasse (8) ein Formteil (7) aufgebracht und nach dem Aushärten der Kunststoffmasse (8) wieder entfernt wird.15. A method for producing an arrangement according to claim 12, characterized in that to limit the plastic mass (8) a molded part (7) is applied and removed again after the plastic compound (8) has hardened. 16. Anordnung nach einem der Ansprüche 1 bis 9 und 12 bis 14, dadurch gekennzeichnet, daß zusätzlich diskrete elektrische Bauelemente auf das Substrat (5) aufgebracht sind und mit
den dortigen Leiterbahnen (6) in Verbindung stehen.16. Arrangement according to one of claims 1 to 9 and 12 to 14, characterized in that, in addition, discrete electrical components are applied to the substrate (5) and with
the conductor tracks (6) there are in connection. 909835/0025909835/0025
DE19782806518 1978-02-16 1978-02-16 ARRANGEMENT FOR CONNECTING AND PACKING AT LEAST ONE SEMICONDUCTOR BODY Withdrawn DE2806518A1 (en)

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DE19782806518 DE2806518A1 (en) 1978-02-16 1978-02-16 ARRANGEMENT FOR CONNECTING AND PACKING AT LEAST ONE SEMICONDUCTOR BODY
GB7904609A GB2014786B (en) 1978-02-16 1979-02-09 Arrangement for the connection and enclosure of at least one semiconductor member

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Application Number Priority Date Filing Date Title
DE19782806518 DE2806518A1 (en) 1978-02-16 1978-02-16 ARRANGEMENT FOR CONNECTING AND PACKING AT LEAST ONE SEMICONDUCTOR BODY

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048938A1 (en) * 1980-09-25 1982-04-07 Siemens Aktiengesellschaft Vertically pluggable "single-in-line" circuit module without case
US4689719A (en) * 1980-09-25 1987-08-25 Siemens Aktiengesellschaft Housing-free vertically insertable single-in-line circuit module
DE102006015510A1 (en) * 2006-03-31 2007-10-11 Compal Communications Inc. Illuminating assembly, has chip receiver attached to contact surface of rib type cooling unit and defining mounting recess, and light emitting chip installed in chip receiver and comprising connecting unit with two connecting contacts

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2135521A (en) * 1983-02-16 1984-08-30 Ferranti Plc Printed circuit boards

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0048938A1 (en) * 1980-09-25 1982-04-07 Siemens Aktiengesellschaft Vertically pluggable "single-in-line" circuit module without case
US4689719A (en) * 1980-09-25 1987-08-25 Siemens Aktiengesellschaft Housing-free vertically insertable single-in-line circuit module
DE102006015510A1 (en) * 2006-03-31 2007-10-11 Compal Communications Inc. Illuminating assembly, has chip receiver attached to contact surface of rib type cooling unit and defining mounting recess, and light emitting chip installed in chip receiver and comprising connecting unit with two connecting contacts

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GB2014786A (en) 1979-08-30
GB2014786B (en) 1982-05-19

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