DE19815907C1 - Field effect semiconductor element - Google Patents
Field effect semiconductor elementInfo
- Publication number
- DE19815907C1 DE19815907C1 DE1998115907 DE19815907A DE19815907C1 DE 19815907 C1 DE19815907 C1 DE 19815907C1 DE 1998115907 DE1998115907 DE 1998115907 DE 19815907 A DE19815907 A DE 19815907A DE 19815907 C1 DE19815907 C1 DE 19815907C1
- Authority
- DE
- Germany
- Prior art keywords
- type
- field effect
- controllable
- region
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 230000005669 field effect Effects 0.000 title claims description 26
- 239000002800 charge carrier Substances 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000004020 conductor Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 230000001427 coherent effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009415 formwork Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
Description
Die vorliegende Erfindung betrifft ein durch Feldeffekt steu erbares Halbleiterbauelement mit einer Drainzone vom ersten Leitungstyp, wenigstens einer gegenüber der Drainzone iso lierten Gateelektrode und wenigstens einer in der Drainzone vorgesehenen Zone vom zweiten Leitungstyp, innerhalb der eine Sourcezone vom ersten Leitungstyp eingebracht ist, wobei in der Drainzone ein dotierter Bereich vom ersten Leitungstyp vorgesehen ist, in dem eine Vielzahl dotierter Bereiche vom zweiten Leitungstyp vorhanden ist.The present invention relates to a steu by field effect erable semiconductor device with a drain zone from the first Conduction type, at least one iso opposite the drain zone gated gate electrode and at least one in the drain zone intended zone of the second conduction type, within the one Source zone of the first conductivity type is introduced, wherein in the drain zone is a doped region of the first conductivity type is provided in which a plurality of doped areas from second line type is available.
Ein derartiges, durch Feldeffekt steuerbares Halbleiterbau element, bei dem in dem dotierten Bereich die Gesamtmenge der Dotierungen vom zweiten Leitungstyp in etwa der Gesamtmenge der Dotierungen vom ersten Leitungstyp entspricht, ist aus DE 196 04 044 A1 bekannt.Such a semiconductor construction controllable by field effect element in which the total amount of Doping of the second conductivity type in approximately the total amount which corresponds to doping of the first conductivity type is from DE 196 04 044 A1 known.
Außerdem ist aus DE 196 04 043 ein durch Feldeffekt steuerba res Halbleiterbauelement mit einer Drainzone vom ersten Lei tungstyp, mit wenigstens einer aus polykristallinem Silizium bestehenden Gateelektrode, die gegenüber der Drainelektrode isoliert ist, und mit wenigstens einem in der Drainzone ein gebrachten Soucebereich vom zweiten Leitungstyp bekannt. Bei diesem Halbleiterbauelement sind in die Drainzone Bereiche vom jeweils ersten und zweiten Leitungstyp eingebracht, wobei die Dotierungskonzentration von eingebrachten n-leitenden Be reichen in etwa der Dotierungskonzentration von eingebrachten p-leitenden Bereichen entspricht.In addition, DE 196 04 043 is controllable by a field effect res semiconductor device with a drain zone from the first lei type, with at least one made of polycrystalline silicon existing gate electrode, which is opposite the drain electrode is isolated, and with at least one in the drain zone brought souce area of the second conduction type known. At areas of this semiconductor device are in the drain zone introduced from the first and second conduction type, respectively the doping concentration of introduced n-type Be range roughly the doping concentration of introduced p-conductive areas.
Die so aufgebauten, bekannten Halbleiterbauelemente weisen den Vorteil auf, daß beispielsweise durch einfaches Einbrin gen einer im Vergleich zu einer Epitaxieschicht höher dotier ten n-leitenden Zone, in welcher eine Vielzahl von p-leiten den Bereichen verteilt ist, zum einen durch die n-leitende Zone eine gute Leitfähigkeit gewährleistet wird und sich zum anderen bei Erhöhung der Drainspannung die derart gebildeten p-leitenden Bereiche und die n-leitende Zone sich gegenseitig von Ladungsträgern aus räumen und so als eine niedrig dotierte Zone wirken, wodurch eine hohe Sperrspannung gesichert bleibt.The known semiconductor components constructed in this way have the advantage that, for example, by simple insertion a higher doping compared to an epitaxial layer th n-type zone in which a multiplicity of p-lines the areas is distributed, on the one hand by the n-type Zone good conductivity is guaranteed and to others when the drain voltage is increased p-type regions and the n-type zone mutually clear from charge carriers and so as a low doped Zone act, which ensures a high reverse voltage remains.
Dieses gegenseitige Ausräumen der Ladungen um die p-leitenden Bereiche herum "erwürgt" aber den Strompfad zwischen Source und Drain. Die ausgeräumte Zone rund um die p-leitenden Be reiche bleibt auch dann erhalten, wenn die Drainspannung nach einer Erhöhung wieder reduziert wird (z. B. beim Einschalten). Um die Leitfähigkeit der n-leitenden Zone wiederherzustellen, sollten die auf Sperrspannung liegenden floatenden, p-leiten den Bereiche entladen werden.This mutual clearing of the charges around the p-type Areas around "strangle" the current path between source and drain. The cleared zone around the p-type Be rich remains even if the drain voltage after an increase is reduced again (e.g. when switching on). To restore the conductivity of the n-type zone, should the floating, p-conductors lying on reverse voltage unloaded from the areas.
Es ist Aufgabe der vorliegenden Erfindung, ein durch Feldef fekt steuerbares Halbleiterbauelement zu schaffen, das als gut leitender Schalter für hohe Spannungen eingesetzt werden kann.It is an object of the present invention, a Feldef to create perfectly controllable semiconductor device that as well conductive switch for high voltages can.
Diese Aufgabe wird bei einem durch Feldeffekt steuerbaren Halbleiterbauelement der eingangs genannten Art erfindungsge mäß dadurch gelöst, daß in dem in der Drainzone vorgesehenen dotierten Bereich die Gesamtmenge der Dotierungen vom zweiten Leitungstyp höher ist als die Gesamtmenge der Dotierungen vom ersten Leitungstyp. Dadurch wird erreicht, daß im eingeschal teten Zustand des Halbleiterbauelements beispielsweise aus der Rückseite oder aus einer anderen Injektorzone soviele Lö cher injiziert werden, wie etwa für die Entladung der p-lei tenden Bereiche nötig sind, wobei keine übermäßige Speicher ladung verursacht wird. This task is controlled by a field effect Semiconductor component of the type mentioned in the invention moderately solved in that in the drain zone provided doped area the total amount of doping from the second Conductivity type is higher than the total amount of doping from first line type. This ensures that in the formwork teten condition of the semiconductor device, for example as much solder on the back or from another injector zone be injected, such as for the discharge of the p-lei areas are needed, with no excessive memory charge is caused.
Diese Löcherinjektion wird in vorteilhafter Weise dadurch er reicht, daß im Bereich des Drainanschlusses ein "schwacher Injektor" vorgesehen wird, welcher eine niedrige Überflutung bewirkt. Bei diesem schwachen Injektor kann es sich bei spielsweise um einen Schottky-Kontakt, eine Legierung oder dergleichen handeln. Ein solcher schwacher Injektor kann un terhalb des Drainkontaktes vorgesehen werden. Auch ist es möglich, beispielsweise unterhalb des Drainkontaktes eine p-leitende oder schwach injizierende Schicht in eine n⁺-lei tende Kontaktschicht einzubetten. Diese p-leitende oder schwach injizierende-Schicht kann dabei dicker oder dünner als die n⁺-leitende Kontaktschicht gestaltet werden. Ein schwacher Injektor auf der "Rückseite" mit abwechselnd kon taktierten n⁺- und p⁺-Bereichen ist beispielsweise aus IEEE Electron Device Letters, Bd. 15, No. 6, Sept. 1994, bekannt. Es gibt aber auch andere, auf der Rückseite vorgesehene schwache Injektoren (IEEE Transactions on Electron Devices, Bd. E0-31, Nr. 1, Januar 1984, Seite 35 ff.).This hole injection is thereby advantageous is sufficient that a "weaker" in the area of the drain connection Injector "is provided, which has a low flooding causes. This weak injector can for example a Schottky contact, an alloy or act like that. Such a weak injector can not be provided below the drain contact. It is too possible, for example below the drain contact p-conductive or weakly injecting layer in a n⁺-lei embedding contact layer. This p-type or weakly injecting layer can be thicker or thinner be designed as the n-type contact layer. A weak injector on the "back" with alternating con clocked n⁺ and p⁺ areas is, for example, from IEEE Electron Device Letters, Vol. 15, No. 6, Sept. 1994. But there are also others on the back weak injectors (IEEE transactions on electron devices, Vol. E0-31, No. 1, January 1984, page 35 ff.).
Es ist aber auch möglich, als Injektor eine p-leitende Schicht oder einen Schottky-Kontakt in der Nähe der Gateelek trode und der Sourcezone auf der zum Drainkontakt gegenüber liegenden Seite einer Halbleiterscheibe vorzusehen. Dabei kann der Injektor beispielsweise unterhalb einer gemeinsamen Gateelektrode von zwei Halbleiterbauelementen angeordnet wer den.But it is also possible to use a p-type injector Layer or a Schottky contact near the gateelek trode and the source zone on the opposite to the drain contact Provide lying side of a semiconductor wafer. Here can the injector, for example, below a common one Gate electrode of two semiconductor devices arranged who the.
Bei den vorstehenden Erläuterungen wurde davon ausgegangen, daß der zweite Leitungstyp der p-Leitungstyp ist. Es sind al so bei dem Halbleiterbauelement eine Vielzahl von p-leitenden Bereichen in den n-leitenden Bereich der Drainzone eingebet tet. Selbstverständlich können diese Leitungstypen auch umge kehrt werden. Da aber die Einbettung von p-leitenden Berei chen in einen n-leitenden Bereich der Drainzone besonders vorteilhaft ist, wird im folgenden von einer derartigen Ge staltung der Leitungstypen ausgegangen.In the above explanations, it was assumed that the second line type is the p-line type. There are al a large number of p-type conductors in the semiconductor component Areas embedded in the n-type area of the drain zone tet. Of course, these line types can also be reversed be returned. But since the embedding of p-type areas especially in an n-conducting area of the drain zone is advantageous in the following from such a Ge design of the line types.
Die p-leitenden Bereiche sind in bevorzugter Weise in paral lelen Schichten angeordnet und dabei zueinander ausgerichtet. Die p-leitenden Bereiche können ein zusammenhängendes Gitter bilden, was speziell für den Mittenbereich eines Halbleiter bauelementes gilt. Im Randbereich sind die p-leitenden Berei che zweckmäßigerweise voneinander unabhängig.The p-type regions are preferably parallel All layers arranged and aligned with each other. The p-type regions can be a continuous grid form what is specifically for the midrange of a semiconductor component applies. The p-type areas are in the edge area che suitably independent of each other.
Der Abstand der p-leitenden Bereiche voneinander ist in den verschiedenen Ebenen des n-leitenden Bereiches zweckmäßiger weise kleiner als die Breite der Raumladungszone zwischen dem n-leitenden Bereich und dem jeweiligen p-leitenden Bereich bei der Durchbruchsspannung zwischen den p-leitenden Berei chen und dem Umfeld des n-leitenden Bereiches wäre. Die p-leitenden Bereiche können kugelförmig, ellipsoidförmig usw. sein. Der n-leitende Bereich, der die p-leitenden Bereiche enthält, kann dabei nahezu die gesamte Drainzone ausfüllen.The distance between the p-type regions is in the different levels of the n-type area more appropriate as smaller than the width of the space charge zone between the n-type region and the respective p-type region at the breakdown voltage between the p-type regions and the environment of the n-leading area. The P-type areas can be spherical, ellipsoidal, etc. be. The n-type region, the p-type regions contains, can fill almost the entire drain zone.
Wie bereits oben erläutert wurde, kann der schwache Injektor in der Form eines Schottky-Kontaktes, einer Legierung oder einfach einer p-leitenden Zone im Bereich der Drainelektrode auf der einen Seite einer Halbleiterscheibe oder auch im Be reich der Gateelektrode bzw. Sourceelektrode auf der gegen überliegenden Seite der Halbleiterscheibe vorgesehen werden. Liegt der Injektor auf der gegenüberliegenden Seite der Halb leiterscheibe, also im Bereich der Gateelektrode bzw. der Sourceelektrode, so wird im eingeschalteten Zustand die ge samte Drainzone und damit vorzugsweise ein epitaktisch aufge brachte Schicht, mit Löchern geringfügig überflutet. Es ent steht so eine geringe Speicherladung, wobei die Leitfähigkeit hoch bleibt, da alle p-leitenden Bereiche auf 0 V entladen werden, auch wenn sie nicht direkt an die p-leitenden Source zonen angeschlossen sind. Damit kann ein Hochvolt-MOSFET mit niedrigem Einschaltwiderstand erhalten werden, der eine Spei cherladung hat, die wesentlich kleiner ist, als dies bei Bi polartransistoren mit isoliertem Gate (IGBTs) üblich ist.As already explained above, the weak injector can in the form of a Schottky contact, an alloy or simply a p-type zone in the area of the drain electrode on one side of a semiconductor wafer or in the loading range of the gate electrode or source electrode on the opposite Overlying side of the semiconductor wafer can be provided. The injector is on the opposite side of the half conductor disc, ie in the area of the gate electrode or Source electrode, the ge is in the on state entire drain zone and thus preferably an epitaxially brought layer, slightly flooded with holes. It ent so there is a low storage charge, the conductivity remains high because all p-type areas discharge to 0 V. even if they are not directly connected to the p-type source zones are connected. This allows a high-voltage MOSFET to be used low on-resistance can be obtained, the one Spei has a charge that is significantly smaller than that of Bi insulated gate polar transistors (IGBTs) is common.
Die Herstellung derartiger Halbleiterbauelemente ist sehr einfach, da die p-leitenden Bereiche nicht angeschlossen zu werden brauchen, sondern vielmehr "floaten". Diese p-leiten den Bereiche werden nicht mehr vollständig ausgeräumt, wie dies beim Stand der Technik vorgesehen ist, und sie können gitterartig miteinander verbunden werden, brauchen dies aber nicht zu sein.The manufacture of such semiconductor devices is very easy because the p-type areas are not connected too will need, but rather "float". This p-line the areas are no longer completely cleared out, like this is provided in the prior art, and they can are connected to one another like a grid, but need this not to be.
Nachfolgend wird die Erfindung anhand der Zeichnungen näher erläutert. Es zeigen:The invention will be described in more detail below with reference to the drawings explained. Show it:
Fig. 1 einen Schnitt durch einen Feldeffekttransi stor, bei dem p-leitende Bereiche in einen n-leitenden Bereich der Drainzone eingebettet sind, wobei hier die P-Dotierung insgesamt höher als die n-Dotierung ist, und wobei auf der Rückseite ein schwacher Injektor vorgese hen ist, Fig. 1 shows a section through a field effect transistor, in which the p-type regions are embedded in an n-type region of the drain zone, the P-type doping overall being higher than the n-type doping, and with a weak injector on the rear is provided,
Fig. 2 einen Schnitt durch einen Lateral-FET mit ei nem schwachen Injektor, Fig. 2 shows a section through a Lateral FET ei nem weak injector,
Fig. 3 ein zu Fig. 1 ähnliches Ausführungsbeispiel, wobei hier zusätzlich die Randstruktur ge zeigt ist, Fig. 3 is a similar to Fig. 1 embodiment, and here, in addition, the edge structure is ge shows,
Fig. 4 eine Abwandlung des Ausführungsbeispiels von Fig. 3 mit einer in eine n⁺-leitende Kontakt schicht eingebetteten p-leitenden oder schwach injizierenden Schicht, Fig. 4 shows a modification of the embodiment of Fig. 3 with a conductive n⁺-contact layer in an embedded p-type or weak injecting layer,
Fig. 5 eine Abwandlung des Ausführungsbeispiels von Fig. 4, wobei hier die p-leitende oder schwach injizierende Schicht eine von der Schichtdicke der n⁺-leitenden Schicht abwei chende Schichtdicke hat, Figure 5 is a modification of the embodiment of FIG. 4, in which case the p-type or weak injecting layer has a conductive N + layer of the thickness of the layer deviate sponding layer thickness.,
Fig. 6 einen Schnitt durch ein weiteres Ausführungs beispiel der Erfindung, bei der ein schwacher Injektor auf der Vorder- bzw. Oberseite eines FETs vorgesehen ist, und Fig. 6 shows a section through a further embodiment of the invention, in which a weak injector is provided on the front or top of an FET, and
Fig. 7 ein weiteres Ausführungsbeispiel des erfin dungsgemäßen Halbleiterbauelements mit einem auf der Oberseite angeordneten Injektor. Fig. 7 shows another embodiment of the semiconductor device according to the invention with an injector arranged on the top.
Fig. 1 zeigt einen vertikalen MOSFET. Ein n⁺-leitendes Sub strat 1 bildet einen Teil einer Drainzone und ist rückseitig mit einer üblichen Metallisierung kontaktiert, die einen Drainanschluß D bildet. Auf dem Substrat 1 ist eine n⁻-do tierte Epitaxieschicht 2 abgeschieden, die ebenfalls einen Teil der Drainzonen bildet und in der in einem Bereich 15, der n-dotiert ist, p-dotierte Bereiche 16 eingebracht sind. Die Epitaxieschicht 2 enthält noch p-dotierte Sourcebereiche 3, in die n⁺-dotierte Bereiche 4 eingebettet sind. Eine Sour cemetallisierung 5 bildet einen Kurzschluß zwischen den Be reichen 3 und 4. In der Fig. 1 sind mehrere Sourcebereiche 3, 4 dargestellt, die voneinander beabstandet sind und von denen jeweils zwei einen Zwischenbereich in Verbindung mit der Drainzone 1, 2 definieren, über den, eingebettet in ein Gate oxid 7 ein Gate 6 angeordnet ist. Das Gate 6 ist mit einem Gateanschluß G verbunden, während an der Sourcemetallisierung 5 ein Sourceanschluß S liegt. Fig. 1 shows a vertical MOSFET. A n⁺-conductive substrate 1 forms part of a drain zone and is contacted on the back with a conventional metallization, which forms a drain connection D. A n⁻-doped epitaxial layer 2 is deposited on the substrate 1 , which likewise forms part of the drain zones and in which p-doped regions 16 are introduced in a region 15 which is n-doped. The epitaxial layer 2 also contains p-doped source regions 3 , in which n⁺-doped regions 4 are embedded. A Sour cemetallisierung 5 forms a short circuit between the loading areas 3 and 4. In Fig. 1, a plurality of source areas 3 , 4 are shown, which are spaced from each other and two of which each define an intermediate area in connection with the drain zone 1 , 2 , over the, embedded in a gate oxide 7, a gate 6 is arranged. The gate 6 is connected to a gate terminal G, while a source terminal S is connected to the source metallization 5 .
Die p-dotierten Bereiche 16 können an sich statistisch ver teilt und jeweils floatend in den Bereich 15 eingebracht sein. Vorzugsweise sind aber, wie in Fig. 1 angedeutet ist, die p-leitenden Bereiche 16 in parallelen Schichten angeord net und gegebenenfalls zueinander ausgerichtet. Dabei können die p-Bereiche 16 in einer Ebene auch ein Gitter bilden, also zusammenhängend sein. Im Randbereich des Halbleiterbauele ments sind die p-Bereiche aber vorzugsweise voneinander beab standet und unabhängig.The p-doped regions 16 can be statistically divided and can be introduced into the region 15 in a floating manner. However, as is indicated in FIG. 1, the p-type regions 16 are preferably arranged in parallel layers and, if appropriate, aligned with one another. The p-regions 16 can also form a grid in one plane, that is to say they can be connected. In the edge region of the semiconductor component, however, the p-regions are preferably spaced apart and independent of one another.
Die Gestalt der p-Bereiche kann kugelförmig, ellipsoid usw. sein und beispielsweise durch Ausdiffusion aus einer implan tierten Zone auf einer jeweiligen Epitaxieschicht-Oberfläche entstehen.The shape of the p-regions can be spherical, ellipsoid, etc. be and for example by diffusion from an implan zone on a respective epitaxial layer surface arise.
Erfindungsgemäß ist bei der Erfindung ein schwacher Injektor 10 zwischen dem Substrat 1 und der Drainzone 2 vorgesehen. Dieser schwache Injektor kann beispielsweise ein Schottkykon takt aus Platin oder Gold, eine Legierung aus Al-Si oder auch eine p-leitende Schicht mit zerstörter Kristallgitterstruktur sein, die p-Ladungsträger in die Drainzone 2 injiziert. Durch die Entladung der p-leitenden Bereiche 16 auf das Potential des n-leitenden Bereiches 15 wird ein Abschneiden des Strom pfades zwischen Source und Drain durch Ausbreitung der Raum ladungszone verhindert, so daß insgesamt ein gut leitender Feldeffekttransistor für höhere Spannungen erhalten wird.According to the invention, a weak injector 10 is provided between the substrate 1 and the drain zone 2 in the invention. This weak injector can be, for example, a Schottkykon clock made of platinum or gold, an alloy made of Al-Si or a p-type layer with a destroyed crystal lattice structure, which injects p-charge carriers into the drain zone 2 . The discharge of the p-type regions 16 to the potential of the n-type region 15 prevents the current path between source and drain from being cut off by spreading the space charge zone, so that overall a highly conductive field effect transistor for higher voltages is obtained.
Fig. 2 zeigt ein weiteres Ausführungsbeispiel, welches einen lateralen MOSFET darstellt. Hier ist beispielsweise ein p-do tiertes Gebiet 19 vorgesehen, in welches eine n-dotierte Sourcezone 22 eingebracht ist, in der sich eine p-dotierte Kontaktierungszone 23 befindet, welche mit einem Sourcean schluß S verbunden ist. Des weiteren ist eine ebenfalls n-dotierte Drainzone 20 vorgesehen, mit welcher wiederum eine p-dotierte Polysilizium-Kontaktierungszone 21 verbunden ist, die zur Kontaktierung der Drainzone 20 mit einem Drainan schluß D dient. Zwischen der Sourcezone 22 und der Drainzone 20 ist isoliert über dem p-dotierten Gebiet 19 ein Gate 26 mit einem Gateanschluß G angebracht, wobei das Gate 26 durch eine Isolationsschicht 27 vom Halbleiterkörper isoliert ist. Zwischen der Sourcezone 22 und der Drainzone 20 ist ein Be reich 25 vorgesehen, der sich von der Drainzone 20 lateral in Richtung zur Sourcezone 22 erstreckt. Dieser Bereich 25 be ginnt von der Oberfläche des Halbleiterkörpers und erstreckt sich in das p-dotierte Gebiet 19. Der Bereich 25 ist n-do tiert und weist p-dotierte Bereiche 16 auf. Fig. 2 shows another embodiment, which is a lateral MOSFET. Here, for example, a p-doped region 19 is provided, into which an n-doped source zone 22 is introduced, in which there is a p-doped contacting zone 23 , which is connected to a source circuit S. Furthermore, an also n-doped drain zone 20 is provided, with which in turn a p-doped polysilicon contacting zone 21 is connected, which serves to contact the drain zone 20 with a drain D circuit D. Between the source zone 22 and the drain zone 20 , a gate 26 with a gate connection G is attached in an insulated manner above the p-doped region 19 , the gate 26 being insulated from the semiconductor body by an insulation layer 27 . Between the source zone 22 and the drain zone 20 , a loading area 25 is provided which extends laterally from the drain zone 20 in the direction of the source zone 22 . This region 25 begins from the surface of the semiconductor body and extends into the p-doped region 19. The region 25 is n-doped and has p-doped regions 16 .
Der Abstand der einzelnen p-leitenden Bereiche 16 voneinander ist vorzugsweise kleiner als die Breite der Raumladungszone beim Durchbruch zwischen den eingebrachten p-leitenden Berei chen 16 und dem n-leitenden Bereich 25. The distance of the individual p-type regions 16 from one another is preferably smaller than the width of the space charge zone at the breakthrough between the introduced p-type regions 16 and the n-type region 25.
Erfindungsgemäß ist zusätzlich unterhalb der Kontaktierungs zone 21 des Drainanschlusses D aus Metall noch ein schwacher Injektor 10 vorhanden, der p-Ladungsträger in den Bereich 25 injiziert, so daß dort im eingeschalteten Zustand die p-lei tenden Bereiche 16 entladen werden.According to the invention, a weak injector 10 is also present below the contacting zone 21 of the drain connection D made of metal, which injects p charge carriers into the region 25 , so that the p-conductive regions 16 are discharged there when the switch is on.
Bei kleiner Drainspannung ist die Leitfähigkeit des erfin dungsgemäßen Halbleiterbauelements gut, da der Bereich 15, 25 (vgl. Fig. 1 und 2) niederohmig ist. Wird die Drainspannung erhöht, werden bei moderater Spannung, beispielsweise einer Spannung kleiner als 30 V, erste von der Oberfläche der Epi taxieschicht 2 bzw. 19 gesehene Schichten der p- bzw. n-do tierten Bereiche 15, 16 bzw. 25, 16 gegenseitig ausgeräumt. Bei einer weiteren Spannungserhöhung wird die vertikale Feld stärke derart gesteigert, daß an sich der gesamte Bereich 15, 25 ausgeräumt wird, so daß hohe Spannungen blockiert werden können.If the drain voltage is low, the conductivity of the semiconductor component according to the invention is good, since the region 15 , 25 (cf. FIGS. 1 and 2) has a low resistance. If the drain voltage is increased, at a moderate voltage, for example a voltage less than 30 V, first layers of the p- and n-doped regions 15 , 16 and 25 , 16 seen from the surface of the epi taxie layer 2 and 19 are mutually cleared out. With a further increase in voltage, the vertical field strength is increased in such a way that the entire area 15 , 25 is cleared out, so that high voltages can be blocked.
Die Ausräumung der Ladungsträger startet von der Oberfläche unter dem Gate 6 bzw. 26 und gegebenenfalls den Sourcezonen 3, 4. Sie schreitet dann in den Bereich 15, 16 bzw. 25, 16 voran. Wenn die Raumladungszone die ersten p-leitenden Berei che 16 erreicht, bleiben diese Bereiche 16 auf der Spannung, die das Potential der Raumladungszone erreicht hat. Dann wird die nächste Umgebung in Richtung des Drainanschlusses D aus geräumt. Dieser Vorgang wiederholt sich von Schicht zu Schicht.The removal of the charge carriers starts from the surface under the gate 6 or 26 and possibly the source zones 3 , 4. It then proceeds into the area 15 , 16 or 25 , 16 . If the space charge region surface, the first p-type preparation reaches 16, these areas 16 remain on the voltage reaches the potential of the space charge zone. Then the next environment is cleared in the direction of the drain connection D. This process is repeated from layer to layer.
Auf diese Weise schreitet die Raumladungszone voran, bis die Zone unterhalb des n-leitenden Bereiches 15, 25 innerhalb der Epitaxieschicht 2 erreicht wird. Beim Einschalten sorgt der Injektor 10 dafür, daß die p-leitenden Bereiche entladen wer den und keine vollständige Ausräumung an Ladungsträgern ein tritt. Bei hoher Spannung wird der Strom durch Elektronen ge führt, welche mit der Grenzgeschwindigkeit durch die Raumla dungszone laufen. Somit wird ein niederohmiger Durchlaßwider stand bei gleichzeitig hoher Spannungsfestigkeit erreicht.In this way, the space charge zone proceeds until the zone below the n-conducting region 15 , 25 within the epitaxial layer 2 is reached. When the injector 10 is switched on, it ensures that the p-conducting regions are discharged and the complete removal of charge carriers does not occur. At high voltage, the current is led by electrons, which run through the space charge zone at the limit speed. Thus, a low-resistance resistance was achieved with high dielectric strength.
Ein mögliches Herstellungsverfahren kann durch einen schicht weisen Aufbau derartiger Strukturen erfolgen. Dabei könnte jede Schicht bzw. Lage der einzelnen Bereiche 16 durch Im plantieren an der jeweiligen Oberfläche oder durch Eindiffun dieren in praktisch beliebiger Form gebildet werden.A possible production process can be carried out by building up such structures in layers. Each layer or layer of the individual regions 16 could be formed in virtually any shape by implantation on the respective surface or by diffusion.
Die Größe des schichtweise eingebrachten und in den Schichten gegebenenfalls unterschiedlich dotierten n-leitenden Berei ches 15, 25 soll so gewählt werden, daß jede Schicht eher ausgeräumt wird, bevor ein Durchbruch auftritt.The size of the n-type regions 15 , 25 introduced in layers and optionally doped differently in the layers should be chosen so that each layer is cleared before a breakthrough occurs.
Der in Fig. 1 dargestellte Feldeffekttransistor kann gegebe nenfalls in einen IGBT umgewandelt werden, wenn als Injektor nicht ein schwacher Injektor sondern ein p⁺-leitendes Sub strat vorgesehen wird. The field effect transistor shown in Fig. 1 can be converted if necessary into an IGBT if the injector is not a weak injector but a p⁺-conducting substrate is provided.
Die Fig. 3 bis 7 zeigen weitere Ausführungsbeispiele der Er findung, wobei hier links von einer Strichpunktlinie 11 ein Randbereich eines Feldeffekttransistors mit Feldplatten 12 und mit p-dotierten Schutzringen 13 gezeigt ist, die mit den jeweiligen Feldplatten 12 verbunden sind. Die äußerste Feld platte 12 ist mit dem Bereich 15 verbunden. Außerdem ist eine Drainelektrode 14 aus Metall gezeigt, auf der ein schwacher Injektor 10 aus einem Schottkykontakt oder einer Legierung angeordnet ist. FIGS. 3 to 7 show further embodiments of he invention, wherein an edge portion is shown a field effect transistor with field plates 12 and p-type guard rings 13 here left of a dash-dot line 11, which are connected to the respective field plates 12. The outermost field plate 12 is connected to the area 15 . In addition, a metal drain electrode 14 is shown, on which a weak injector 10 made of a Schottky contact or an alloy is arranged.
Die p-leitenden Bereiche 16 sind durch Implantation in drei Ebenen in den Bereich 15 eingebracht, der zwischen den ein zelnen Ebenen Leitfähigkeiten n1, n2, n3 und n4 hat, was durch unterschiedliche Epitaxieschritte erreicht werden kann. Im Randbereich sind die Bereiche 16 inselartig und nicht zusam menhängend, während sie im Bereich des eigentlichen Feldef fekttransistors, also auf der rechten Seite der Strichpunkt linie 11, gitterartig oder auch alleinstehend, also inselar tig, sein können aber nicht sein müssen.The p-type regions 16 are introduced by implantation in three planes into the region 15 , which has conductivities n 1 , n 2 , n 3 and n 4 between the individual planes, which can be achieved by different epitaxial steps. In the edge area, the areas 16 are island-like and not coherent, while in the area of the actual field effect transistor, that is, on the right side of the dash-dot line 11 , lattice-like or also standalone, so insular, but they need not be.
Das Ausführungsbeispiel von Fig. 4 unterscheidet sich vom Ausführungsbeispiel von Fig. 3 dadurch, daß unterhalb der Drainelektrode 14 eine n⁺-leitende Schicht 17 vorgesehen ist, in die ein schwacher Injektor 10 in der Form eines Schottky kontaktes oder einer Legierung oder einer p-leitenden Zone eingebettet ist. Ein solcher schwacher Injektor ist ausrei chend, um eine vollständige Ausräumung von Ladungsträgern im Gebiet um die p-leitenden Bereiche 16 im Bereich 15 zu ver hindern.The embodiment of FIG. 4 differs from the embodiment of FIG. 3 in that an n⁺-conducting layer 17 is provided below the drain electrode 14 , into which a weak injector 10 in the form of a Schottky contact or an alloy or a p- conductive zone is embedded. Such a weak injector is sufficient to prevent complete removal of charge carriers in the area around the p-type regions 16 in the region 15 .
Fig. 5 zeigt ein weiteres Ausführungsbeispiel des erfindungs gemäßen Halbleiterbauelements, bei dem der schwache Injekto ren 10 aus einer p-leitenden Schicht oder einem Schottkykon takt bestehen, wobei diese Schicht 10 weiter in den Bereich 15 hineinragt als die n⁺-leitende Schicht 17. Anstelle dieser Schicht 17 kann gegebenenfalls auch ein ohmscher Kontakt für den Bereich 15 mit der Leitfähigkeit n1 verwendet werden. Der Injektor 10 kann auch so gestaltet sein, daß er weniger tief in den Bereich 15 hineinragt als die n⁺-leitende Schicht 17. Im übrigen zeigt dieses Ausführungsbeispiel, daß hier nur zwei Ebenen für die p-leitenden Bereiche 16 vorgesehen sind. Auf der "linken" Seite der Strichpunktlinie 11, also im Rand bereich des Halbleiterbauelements, sind unterhalb der Feld platten 12 die p-leitenden Bereiche 16 inselartig und nicht zusammenhängend, während diese Bereiche 16 rechts von der Strichpunktlinie 11 gitterartig, also zusammenhängend, oder auch inselartig sein können. Fig. 5 shows another embodiment of the semiconductor component according to fiction, in which the weak Injekto ren 10 conductive p-out of a layer or Schottkykon clock exist, said layer 10 extends further into the area 15 as the n⁺-type layer 17. Instead of this layer 17 , an ohmic contact for the region 15 with the conductivity n 1 can optionally also be used. The injector 10 can also be designed in such a way that it projects less deeply into the region 15 than the n⁺-conducting layer 17. Moreover, this exemplary embodiment shows that only two planes are provided for the p-conducting regions 16 here. On the "left" side of the chain line 11 , that is to say in the edge region of the semiconductor component, the p-type regions 16 below the field plates 12 are island-like and not connected, while these regions 16 to the right of the chain line 11 are grid-like, that is connected, or else can be island-like.
Während in den Ausführungsbeispielen der Fig. 1 und 3 bis 5 der Injektor an der Unterseite im Gebiet des Drainkontakts vorgesehen ist, zeigen die Fig. 6 und 7 noch Ausführungsbei spiele, bei denen der Injektor, ähnlich wie in Fig. 2, auf der Oberseite des Halbleiterbauelementes, im Gebiet der Sour ce- und Drainelektrode, angebracht ist. Im Unterschied zum Ausführungsbeispiel von Fig. 2 zeigen die Fig. 6 und 7 aber keine Lateralanordnungen, sondern vielmehr ebenfalls Verti kalstrukturen wie die Ausführungsbeispiele der Fig. 1 und 3 bis 5.While the injector is provided on the underside in the area of the drain contact in the embodiments of FIGS. 1 and 3 to 5, FIGS. 6 and 7 still Ausführungsbei games, in which the injector, similarly as in Fig. 2, on the top of the semiconductor device, in the area of the source and drain electrode, is attached. In contrast to the exemplary embodiment of FIG. 2, FIGS. 6 and 7 do not show any lateral arrangements, but rather also vertical structures like the exemplary embodiments of FIGS . 1 and 3 to 5.
Fig. 6 zeigt einen Injektoranschluß I, der über eine Leiter bahn mit einer p-leitenden Injektorzone 10 verbunden ist, die zwischen den p-leitenden Bereichen 3 angeordnet ist, in die die Sourcezonen 4 eingebettet sind. Der Injektoranschluß I kann über einen Widerstand mit dem Gateanschluß G von Gate 6 aus n⁺-leitendem polykristallinem Silizium verbunden werden. Dieser Widerstand kann gegebenenfalls in die Halbleiteranord nung integriert werden. Fig. 6 shows an injector connection I, which is connected via a conductor track to a p-type injector zone 10, which is arranged between the p-type regions 3 , in which the source zones 4 are embedded. The injector connection I can be connected via a resistor to the gate connection G of gate 6 made of n⁺-conducting polycrystalline silicon. This resistor can optionally be integrated into the semiconductor arrangement.
Bei dem Ausführungsbeispiel von Fig. 6 befindet sich also der Injektor 10 im Bereich von Source und Gate auf der "Obersei te" der Halbleiteranordnung und nicht im Bereich der Drain elektrode. Es sind hier also Injektoren 10 auf der "Vorder seite" in der Gestalt von p-leitenden Zonen eingebaut, welche im eingeschalteten Zustand den gesamten Bereich 15 mit Lö chern geringfügig überfluten. Es entsteht dabei eine geringe Speicherladung, wobei die Leitfähigkeit gut bleibt, da alle p-leitenden Bereiche 16, auch wenn diese nicht direkt an die p-leitenden Sourcezonen 3 angeschlossen sind, auf 0 V entla den werden. Damit wird ein Hochspannungs- bzw. HV-MOSFET mit niedrigem Einschaltwiderstand erhalten, der eine Speicherla dung hat, welche wesentlich kleiner ist als dies bei IGBT's üblich ist.In the embodiment of FIG. 6, the injector 10 is therefore in the region of the source and gate on the “upper side” of the semiconductor arrangement and not in the region of the drain electrode. So there are injectors 10 installed on the "front side" in the form of p-type zones which, when switched on, flood the entire area 15 with holes slightly. This results in a low storage charge, the conductivity remaining good since all p-type regions 16 , even if they are not directly connected to the p-type source zones 3 , are discharged to 0 V. A high-voltage or HV-MOSFET with a low on-resistance is thus obtained, which has a storage charge which is considerably smaller than is usual with IGBTs.
Fig. 7 zeigt schließlich eine vorteilhafte Weiterbildung ei nes aus der DE 196 04 043 Al bekannten Halbleiterbauelements in der Form eines vertikalen MOSFETs, bei dem zusätzlich zu p-leitenden Bereichen 16 noch n-leitende Bereiche 30 in den schwach n-leitenden Bereich 15 eingebaut sind, der außerdem noch n-leitende vertikale Gebiete 31 und p-leitende vertikale Gebiet 32 besitzt. Im Unterschied zu dem bekannten Halblei terbauelement sind zusätzlich noch Injektoren 10 mit Injek toranschlüssen I vorhanden, die bewirken, daß auch bei floa tenden p-leitenden Bereichen die gute Leitfähigkeit im On- bzw. Einschaltzustand erhalten bleibt. Fig. 7 shows egg nes from DE 196 04 043 Al known semiconductor device in the form of a vertical MOSFET, in addition conductive p-to areas 16 nor n-type regions 30 conductive n-in the weak region 15, an advantageous development incorporated , which also has n-type vertical regions 31 and p-type vertical regions 32 . In contrast to the known semiconductor component, injectors 10 with injector gate connections I are additionally present, which have the effect that the good conductivity in the on or on state is maintained even in the case of floating p-conducting regions.
11
n⁺-dotiertes Substrat
n⁺-doped substrate
22nd
Epitaxieschicht
Epitaxial layer
33rd
Sourcebereich
Source area
44th
n⁺-leitende Bereiche
n⁺-conducting areas
55
Sourcemetallisierung
Source metallization
66
Gate
Gate
77
Isolierschicht
Insulating layer
1010th
Injektor
Injector
1111
Strichpunktlinie
Semicolon
1212th
Feldplatten
Field plates
1313
Schutzringe
Guard rings
1414
Drainanschluß
Drain connection
1515
n-dotierter Bereich
n-doped region
1616
p-dotierte Bereiche
p-doped areas
1717th
n⁺-dotierte Schicht
n⁺-doped layer
1818th
n⁺-dotiertes Polysilizium
n⁺-doped polysilicon
1919th
p-dotiertes Gebiet
p-doped area
2020th
Drainzone
Drain zone
2121
Drainkontakt
Drain contact
2222
Sourcezone
Source zone
2323
Kontaktierungszone
Contact zone
2525th
n-leitender Bereich
n-type area
2626
Gate
Gate
2727
Isolationsschicht
Insulation layer
3030th
, ,
3131
n-leitende Bereiche
n-type areas
3232
p-leitendes Gebiet
I Injektoranschluß
G Gateanschluß
S Sourceanschluß
D Drainanschluß
p-type area
I injector connection
G gate connection
S source connection
D drain connection
Claims (17)
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DE1998115907 DE19815907C1 (en) | 1998-04-08 | 1998-04-08 | Field effect semiconductor element |
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DE1998115907 DE19815907C1 (en) | 1998-04-08 | 1998-04-08 | Field effect semiconductor element |
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DE19948901B4 (en) * | 1999-10-11 | 2008-05-08 | Infineon Technologies Ag | Field effect controllable semiconductor device |
WO2001028002A1 (en) * | 1999-10-11 | 2001-04-19 | Infineon Technologies Ag | Semiconductor component, controlled by field effect |
US6903413B2 (en) | 1999-12-22 | 2005-06-07 | Stmicroelectronics S.A. | Single-pole component manufacturing |
WO2001047028A1 (en) * | 1999-12-22 | 2001-06-28 | Stmicroelectronics S.A. | Production of single-pole components |
FR2803094A1 (en) * | 1999-12-22 | 2001-06-29 | St Microelectronics Sa | Single pole monolithic component structure manufacture having p type conductivity regions n type region embedded and having inner isolating material section. |
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FR2817658A1 (en) * | 2000-10-31 | 2002-06-07 | Fuji Electric Co Ltd | Semiconductor MOSFET device, has n-type tape-like surface regions as up-to-surface extensions of drift layer surrounded by p-type wells region, and determined limits |
FR2826184A1 (en) * | 2000-10-31 | 2002-12-20 | Fuji Electric Co Ltd | SEMICONDUCTOR DEVICE WITH HIGH BREAKDOWN VOLTAGE |
DE10061528C1 (en) * | 2000-12-11 | 2002-07-25 | Infineon Technologies Ag | Semiconductor component controllable by field effect |
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US7821064B2 (en) | 2005-03-15 | 2010-10-26 | Infineon Technologies Austria Ag | Lateral MISFET and method for fabricating it |
WO2008035134A1 (en) | 2006-09-22 | 2008-03-27 | Freescale Semiconductor, Inc. | Semiconductor device and method of forming a semiconductor device |
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US8779465B2 (en) | 2006-09-22 | 2014-07-15 | Freescale Semiconductor, Inc. | Semiconductor device and method of forming a semiconductor device |
DE102007018631A1 (en) | 2007-04-19 | 2008-10-30 | Infineon Technologies Austria Ag | Semiconductor device with compensation zones and discharge structures for the compensation zones |
US7750397B2 (en) | 2007-04-19 | 2010-07-06 | Infineon Technologies Austria Ag | Semiconductor component including compensation zones and discharge structures for the compensation zones |
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