DE112006002430B4 - Method for producing superlattices using alternating high and low temperature layers for blocking parasitic current paths - Google Patents
Method for producing superlattices using alternating high and low temperature layers for blocking parasitic current paths Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 230000003071 parasitic effect Effects 0.000 title description 8
- 230000000903 blocking effect Effects 0.000 title 1
- 150000004767 nitrides Chemical class 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims description 35
- 239000000956 alloy Substances 0.000 claims description 8
- 229910045601 alloy Inorganic materials 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 239000013078 crystal Substances 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 230000001174 ascending effect Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 235000015095 lager Nutrition 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
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- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
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- C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
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Abstract
Verfahren zur Herstellung eines Halbleiter-Bauteils mit den folgenden Schritten: Bereitstellen eines Substrates; und Aufwachsen eines Gruppe-III-Nitridkörpers über einer Hauptfläche des Substrates bis zu einer abschließenden Dicke über eine Wachstums-Zeitperiode, wobei die Wachstums-Temperatur in Zyklen über die Wachstums-Zeitperiode geändert wird, wobei jeder Zyklus eine Periode eines Niedrigtemperatur-Wachstums bei einer ersten Temperatur und eine Periode eines Hochtemperatur-Wachstums bei einer zweiten Temperatur einschließt, wobei die erste Temperatur niedriger als die zweite Temperatur ist; wobei die Periode des Niedrigtemperatur-Wachstums, die erste Temperatur, die Periode des Hochtemperatur-Wachstums oder/und die zweite Temperatur in aufeinanderfolgenden Zyklen variiert wird.A method of manufacturing a semiconductor device, comprising the steps of: providing a substrate; and growing a Group III nitride body over a major surface of the substrate to a final thickness over a growth time period, wherein the growth temperature is changed in cycles over the growth time period, each cycle having a period of low temperature growth at a first temperature and a period of high temperature growth at a second temperature, wherein the first temperature is lower than the second temperature; wherein the period of low temperature growth, the first temperature, the period of high temperature growth and / or the second temperature is varied in successive cycles.
Description
Verwandte AnmeldungRelated Application
Diese Anmeldung beruht auf der provisorischen US-Patentanmeldung Nr. 60/171,102 vom 14. September 2005 mit dem Titel ”Process For Manufacture of Super Lattice Using Alternating High and Low Temperature Lagers to Block Parasitic Current Path”, deren Priorität hiermit beansprucht wird, deren Vergünstigungen in Anspruch genommen werden und deren Offenbarung durch diese, Bezugnahme hier mit aufgenommen wird.This application is based on US Provisional Patent Application No. 60 / 171,102, filed on Sep. 14, 2005, entitled "Process For Manufacture of Super Lattice Using Alternating High and Low Temperature Lagers to Block Parasitic Current Path," the priority of which is claimed Benefits and the disclosure of which is incorporated herein by reference.
Definitiondefinition
Gruppe-III-Nitrid, wie es hier verwendet wird, bezieht sich auf eine Halbleiter-Legierung aus dem InAlGaN-System, das zumindest Stickstoff und ein anderes Legierungselement aus der Gruppe III einschließt. Beispiele von Gruppe-III-Nitrid-Legierungen sind AlN, GaN, AlGaN, InGaN, InAlGaN oder irgendeine Kombination, die Stickstoff oder zumindest ein Element aus der Gruppe III einschließt.Group III nitride as used herein refers to a semiconductor alloy of the InAlGaN system including at least nitrogen and another Group III alloying element. Examples of Group III nitride alloys are AlN, GaN, AlGaN, InGaN, InAlGaN or any combination including nitrogen or at least one Group III element.
Hintergrund der ErfindungBackground of the invention
Die vorliegende Erfindung bezieht sich auf ein Verfahren zur Herstellung eines Leistungs-Halbleiterbauteils und insbesondere eines Gruppe-III-Nitrid-Leistungs-Halbleiterbauteils.The present invention relates to a method of manufacturing a power semiconductor device, and more particularly, a group III nitride power semiconductor device.
Wie dies gut bekannt ist, schließen Gruppe-III-Nitrid-Leistungs-Halbleiterbauteile ein Substrat, eine Gruppe-III-Nitrid-Übergangsschicht und ein Gruppe-III-Nitrid-Heteroübergangs-Element über der Übergangsschicht ein. Derartige Bauteile sind dafür bekannt, dass sie einen parasitären Leitungspfad von dem Heteroübergangs-Element zu dem Substrat einschließen. Der parasitäre Leitungspfad ist unerwünscht, weil er die Fähigkeit des Bauteils zum effektiven Schalten eines Stromes unterminiert.As is well known, Group III nitride power semiconductor devices include a substrate, a Group III nitride transition layer, and a Group III nitride heterojunction element over the transition layer. Such devices are known to include a parasitic conduction path from the heterojunction element to the substrate. The parasitic conduction path is undesirable because it undermines the ability of the device to effectively switch a current.
Es ist wünschenswert, die Wirkung des parasitären Leitungspfades in Gruppe-III-Nitrid-Heteroübergangs-Bauteilen zu einem Minimum zu machen oder zu beseitigen.It is desirable to minimize or eliminate the effect of the parasitic conduction path in Group III nitride heterojunction devices.
Das Dokument
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Zusammenfassung der ErfindungSummary of the invention
Es ist ein Ziel der vorliegenden Erfindung, ein Verfahren zur Herstellung eines Gruppe-III-Nitrid-Leistungs-Halbleiterbauteils zu schaffen, das keinen parasitären Leitungspfad einschließt.It is an object of the present invention to provide a method of fabricating a Group III nitride power semiconductor device that does not include a parasitic conduction path.
Es wird angenommen, dass die parasitäre Leitung, wie sie oben erläutert wurde, Defekt-unterstützt ist. Daher beinhaltet das Verfahren gemäß der vorliegenden Erfindung ein Verfahren, das die Defekte zu einem Minimum macht, die die Förderung von parasitären Leitungspfaden unterstützen.It is believed that the parasitic conduction discussed above is defect-assisted. Therefore, the method according to the present invention includes a method that the Minimizing defects that support the promotion of parasitic conduction paths.
Im Einzelnen schließt ein Verfahren gemäß Anspruch 1 die Bereitstellung eines Substrates und das Aufwachsen eines Gruppe-III-Nitrid-Körpers über eine Hauptfläche des Substrates bis zu einer abschließenden Dicke über eine Wachstums-Zeitperiode, wobei die Wachstums-Temperatur über die Wachstums-Zeitperiode geändert wird.Specifically, a method according to
Bei der vorliegenden Erfindung wird die Wachstums-Temperatur in Zyklen geändert, wobei jeder Zyklus eine Periode eines Hochtemperatur-Wachstums bei einer hohen Temperatur und eine Periode eines Niedrigtemperatur-Wachstums bei einer niedrigen Temperatur einschließt.In the present invention, the growth temperature is changed into cycles, each cycle including a period of high-temperature growth at a high temperature and a period of low-temperature growth at a low temperature.
Bei einer Ausführungsform der vorliegenden Erfindung sind die hohe Temperatur und die niedrige Temperatur in allen Zyklen die gleichen.In one embodiment of the present invention, the high temperature and the low temperature are the same in all cycles.
Bei einer anderen Ausführungsform der vorliegenden Erfindung wird die niedrige Temperatur in jedem Zyklus geändert, während die hohe Temperatur von Zyklus zu Zyklus die gleiche bleibt.In another embodiment of the present invention, the low temperature is changed in each cycle while the high temperature remains the same from cycle to cycle.
Bei einer weiteren Ausführungsform der vorliegenden Erfindung werden die niedrige Temperatur und die hohe Temperatur in jedem Zyklus geändert, bis die zwei Temperaturen konvergieren.In another embodiment of the present invention, the low temperature and the high temperature are changed in each cycle until the two temperatures converge.
Bei allen den Ausführungsformen kann die Zeitperiode für die niedrige Temperatur oder die hohe Temperatur in jedem Zyklus nach Wunsch geändert werden.In all the embodiments, the time period for the low temperature or the high temperature in each cycle may be changed as desired.
Bei einer weiteren Variation der vorliegenden Erfindung wird die Wachstums-Temperatur kontinuierlich entweder in einer aufsteigenden Richtung oder einer absteigenden Richtung geändert.In a further variation of the present invention, the growth temperature is continuously changed in either an ascending direction or a descending direction.
Weitere Merkmale und Vorteile der vorliegenden Erfindung werden aus der folgenden Beschreibung der Erfindung ersichtlich, die sich auf die beigefügten Zeichnungen bezieht.Other features and advantages of the present invention will become apparent from the following description of the invention, which refers to the accompanying drawings.
Kurze Beschreibung der ZeichnungenBrief description of the drawings
Die
Die
Die
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Ausführliche Beschreibung der FigurenDetailed description of the figures
In den
Es ist festzustellen, dass beobachtet wurde, dass die besten Ergebnisse erzielt werden können, wenn ein Verfahren gemäß der vorliegenden Erfindung mit einem Niedrigtemperatur-Wachstums-Schritt als erstem beginnt. Somit wird es bevorzugt, dass ein Verfahren gemäß der vorliegenden Erfindung mit einem Niedrigtemperatur-Wachstums-Schritt beginnt, auf den dann andere Schritte folgen, wie dies anhand der nachfolgend beschriebenen Ausführungsformen erläutert wird.It is noted that it has been observed that the best results can be achieved when a method according to the present invention begins with a low-temperature growth step first. Thus, it is preferred that a method according to the present invention begins with a low-temperature growth step, then followed by other steps, as will be explained with reference to the embodiments described below.
Bei einem Verfahren gemäß der ersten Ausführungsform sind die hohen Wachstums-Temperaturen T1 in allen Zyklen untereinander gleich, und die niedrigen Wachstums-Temperaturen T2 sind in allen Zyklen untereinander gleich. Es sei bemerkt, dass die ersten Zeitperioden
Gemäß den
Gemäß den
Es wird nunmehr auf die
Gemäß
Es sei weiterhin bemerkt, dass in einem Verfahren gemäß der vorliegenden Erfindung die Legierungs-Zusammensetzung während der Änderung der Temperatur geändert werden kann. So kann beispielsweise die Legierungs-Zusammensetzung eines III-Nitrid-Halbleiterkörpers, der bei einer hohen Temperatur aufgewachsen wird, von der Legierungs-Zusammensetzung eines anderen Gruppe-III-Nitridkörpers verschieden sein, der bei einer niedrigen Temperatur aufgewachsen wird. Bei einer weiteren Abänderung kann die Legierungs-Zusammensetzung in dem Körper eines Gruppe-III-Nitridkörpers, der bei einer hohen Temperatur oder einer niedrigen Temperatur aufgewachsen wird, ebenfalls geändert werden; das heißt ein Gruppe-III-Nitridkörper kann eine sich ändernde Legierungs-Zusammensetzung haben.It should be further noted that in a method according to the present invention, the alloy composition may be changed during the change of the temperature. For example, the alloy composition of a III-nitride semiconductor body grown at a high temperature may be different from the alloy composition of another Group III nitride body grown at a low temperature. In another modification, the alloy composition in the body of a group III nitride body grown at a high temperature or a low temperature may also be changed; that is, a Group III nitride body may have a changing alloy composition.
Bei einem Verfahren gemäß der vorliegenden Erfindung kann das Substrat
Obwohl die vorliegende Erfindung anhand spezieller Ausführungsformen hiervon beschrieben wurde, werden viele andere Abänderungen und Modifikationen und andere Anwendungen für den Fachmann ersichtlich. Es wird daher bevorzugt, dass die vorliegende Erfindung nicht durch diese ausführliche Beschreibung sondern lediglich durch die beigefügten Ansprüche beschränkt ist.Although the present invention has been described in terms of particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is therefore to be understood that the present invention is not limited by this detailed description but by the appended claims only.
Claims (16)
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Application Number | Priority Date | Filing Date | Title |
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US71710205P | 2005-09-14 | 2005-09-14 | |
US60/717,102 | 2005-09-14 | ||
US11/531,508 | 2006-09-13 | ||
US11/531,508 US9157169B2 (en) | 2005-09-14 | 2006-09-13 | Process for manufacture of super lattice using alternating high and low temperature layers to block parasitic current path |
PCT/US2006/035800 WO2007033312A2 (en) | 2005-09-14 | 2006-09-14 | Process for manufacture of super lattice using alternating high and low temperature layers to block parasitic current path |
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DE112006002430T5 DE112006002430T5 (en) | 2008-07-03 |
DE112006002430B4 true DE112006002430B4 (en) | 2013-08-22 |
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JP (1) | JP5475286B2 (en) |
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US9911600B2 (en) | 2018-03-06 |
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JP2009509341A (en) | 2009-03-05 |
US20070056506A1 (en) | 2007-03-15 |
US9157169B2 (en) | 2015-10-13 |
WO2007033312A2 (en) | 2007-03-22 |
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US20160027643A1 (en) | 2016-01-28 |
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