DE10338030B3 - Integrierte Schaltung zum Testen von Schaltungskomponenten eines Halbleiterchips - Google Patents

Integrierte Schaltung zum Testen von Schaltungskomponenten eines Halbleiterchips Download PDF

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Publication number
DE10338030B3
DE10338030B3 DE10338030A DE10338030A DE10338030B3 DE 10338030 B3 DE10338030 B3 DE 10338030B3 DE 10338030 A DE10338030 A DE 10338030A DE 10338030 A DE10338030 A DE 10338030A DE 10338030 B3 DE10338030 B3 DE 10338030B3
Authority
DE
Germany
Prior art keywords
circuit
component
external terminal
semiconductor chip
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10338030A
Other languages
English (en)
Inventor
Fabien Funfrock
Michael Bernhard Sommer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Polaris Innovations Ltd
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE10338030A priority Critical patent/DE10338030B3/de
Priority to US10/920,204 priority patent/US7102362B2/en
Application granted granted Critical
Publication of DE10338030B3 publication Critical patent/DE10338030B3/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

Eine integrierte Schaltung (1) umfaßt eine erste Schaltungskomponente (50), eine zweite Schaltungskomponente (42) und einen externen Anschluß (11) zur Kontaktierung der Schaltung, bei der die erste Schaltungskomponente über die zweite Komponente mit dem externen Anschluß verbunden ist. Sie umfaßt weiterhin eine Überbrückungsschaltung (41), mit der die erste Schaltungskomponente mit dem externen Anschluß verbindbar ist und die von einem Testmodus Signal (TMS/TMS) aktivierbar ist. Im aktiven Zustand verbindet die Überbrückungsschaltung den externen Anschluß unter Überbrückung der zweiten Schaltungskomponente mit der ersten Schaltungskomponente, während sie im deaktivierten Zustand nicht leitend ist. Mit Hilfe der Schaltung lassen sich im Halbleiterchip integrierte Schaltungskomponenten zerstörungsfrei elektrisch vermessen. Dazu werden über aktivierbare Schalter leitende Verbindungen von einem zugänglichen externen Anschluß bis zum zu vermessenden Bauelement im Inneren des Halbleiterchips erzeugt. Schaltungskomponenten, die zwischen dem externen Anschluß und dem zu vermessenden Bauelement liegen, können durch Überbrückungsschaltungen von der Messung ausgeschlossen werden. Das Verfahren ermöglicht es, auch mehrere integrierte Bauteile parallel oder seriell zu vermessen.
DE10338030A 2003-08-19 2003-08-19 Integrierte Schaltung zum Testen von Schaltungskomponenten eines Halbleiterchips Expired - Fee Related DE10338030B3 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE10338030A DE10338030B3 (de) 2003-08-19 2003-08-19 Integrierte Schaltung zum Testen von Schaltungskomponenten eines Halbleiterchips
US10/920,204 US7102362B2 (en) 2003-08-19 2004-08-18 Integrated circuit for testing circuit components of a semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10338030A DE10338030B3 (de) 2003-08-19 2003-08-19 Integrierte Schaltung zum Testen von Schaltungskomponenten eines Halbleiterchips

Publications (1)

Publication Number Publication Date
DE10338030B3 true DE10338030B3 (de) 2005-04-28

Family

ID=34177684

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10338030A Expired - Fee Related DE10338030B3 (de) 2003-08-19 2003-08-19 Integrierte Schaltung zum Testen von Schaltungskomponenten eines Halbleiterchips

Country Status (2)

Country Link
US (1) US7102362B2 (de)
DE (1) DE10338030B3 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5061593B2 (ja) * 2005-11-21 2012-10-31 富士通セミコンダクター株式会社 制御装置、半導体集積回路装置及び供給制御システム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10146149B4 (de) * 2001-09-19 2004-04-29 Infineon Technologies Ag Schaltungsanordnung zum Empfang eines Datensignals

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US5613128A (en) * 1990-12-21 1997-03-18 Intel Corporation Programmable multi-processor interrupt controller system with a processor integrated local interrupt controller
US5844921A (en) * 1996-02-28 1998-12-01 International Business Machines Corporation Method and apparatus for testing a hybrid circuit having macro and non-macro circuitry
US5687325A (en) * 1996-04-19 1997-11-11 Chang; Web Application specific field programmable gate array
US5745772A (en) * 1996-08-02 1998-04-28 Micron Electronics, Inc. Advanced programmable interrupt controller
US5859442A (en) * 1996-12-03 1999-01-12 Micron Technology, Inc. Circuit and method for configuring a redundant bond pad for probing a semiconductor
US5905897A (en) * 1997-03-20 1999-05-18 Industrial Technology Research Institute Method and apparatus for selecting a nonblocked interrupt request
US6055643A (en) * 1997-09-25 2000-04-25 Compaq Computer Corp. System management method and apparatus for supporting non-dedicated event detection
US6253304B1 (en) * 1999-01-04 2001-06-26 Advanced Micro Devices, Inc. Collation of interrupt control devices
US6081479A (en) * 1999-06-15 2000-06-27 Infineon Technologies North America Corp. Hierarchical prefetch for semiconductor memories
JP2000349130A (ja) * 1999-06-03 2000-12-15 Nec Ic Microcomput Syst Ltd 半導体集積回路基板とその製造方法およびその特性チェック方法
DE10052211A1 (de) * 2000-10-20 2002-05-08 Infineon Technologies Ag Integrierte Schaltung mit Testbetriebsart und Verfahren zum Testen einer Vielzahl solcher integrierter Schaltungen
EP1172661B1 (de) * 2001-03-10 2003-02-19 Agilent Technologies, Inc. (a Delaware corporation) Umschaltbare Testschaltung für asymmetrischen und differentiellen Abschluss
WO2002075341A1 (en) * 2001-03-19 2002-09-26 Hitachi, Ltd. Semiconductor device and its test method
US6775730B2 (en) * 2001-04-18 2004-08-10 Sony Corporation System and method for implementing a flexible interrupt mechanism
GB2382662B (en) * 2001-11-29 2003-12-10 Univ Cardiff High frequency circuit analyzer
US6593771B2 (en) * 2001-12-10 2003-07-15 International Business Machines Corporation Method and system for use of a field programmable interconnect within an ASIC for configuring the ASIC
US6930500B2 (en) * 2003-08-01 2005-08-16 Board Of Supervisors Of Louisiana State University And Agricultural And Mechanical College IDDQ testing of CMOS mixed-signal integrated circuits
DE102004056133B4 (de) * 2004-02-20 2007-04-12 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Erfassung einer Offsetdrift bei einer Wheatstone-Meßbrücke

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10146149B4 (de) * 2001-09-19 2004-04-29 Infineon Technologies Ag Schaltungsanordnung zum Empfang eines Datensignals

Also Published As

Publication number Publication date
US20050040830A1 (en) 2005-02-24
US7102362B2 (en) 2006-09-05

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Legal Events

Date Code Title Description
8100 Publication of the examined application without publication of unexamined application
8364 No opposition during term of opposition
8325 Change of the main classification

Ipc: G11C 29/00 AFI20030819BHDE

8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

R081 Change of applicant/patentee

Owner name: INFINEON TECHNOLOGIES AG, DE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE

R081 Change of applicant/patentee

Owner name: POLARIS INNOVATIONS LTD., IE

Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee