DE10245671B4 - Manufacturing method for a semiconductor structure by selective isotropic etching of a silicon dioxide layer on a silicon nitride layer - Google Patents
Manufacturing method for a semiconductor structure by selective isotropic etching of a silicon dioxide layer on a silicon nitride layer Download PDFInfo
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- DE10245671B4 DE10245671B4 DE10245671A DE10245671A DE10245671B4 DE 10245671 B4 DE10245671 B4 DE 10245671B4 DE 10245671 A DE10245671 A DE 10245671A DE 10245671 A DE10245671 A DE 10245671A DE 10245671 B4 DE10245671 B4 DE 10245671B4
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- silicon nitride
- silicon dioxide
- nitride layer
- dioxide layer
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title claims abstract description 83
- 238000005530 etching Methods 0.000 title claims abstract description 55
- 229910052581 Si3N4 Inorganic materials 0.000 title claims abstract description 49
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 title claims abstract description 48
- 235000012239 silicon dioxide Nutrition 0.000 title claims abstract description 40
- 239000000377 silicon dioxide Substances 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000001020 plasma etching Methods 0.000 claims abstract description 26
- 239000007789 gas Substances 0.000 claims abstract description 15
- 239000000203 mixture Substances 0.000 claims abstract description 12
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims abstract description 10
- 238000009616 inductively coupled plasma Methods 0.000 claims abstract description 9
- 239000011261 inert gas Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052786 argon Inorganic materials 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 22
- 238000001514 detection method Methods 0.000 claims description 5
- 238000001636 atomic emission spectroscopy Methods 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 230000008569 process Effects 0.000 description 10
- 238000011161 development Methods 0.000 description 5
- 230000018109 developmental process Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000000379 polymerizing effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZHVOBYWXERUHMN-KVJKMEBSSA-N 3-[(3s,5r,8r,9s,10s,13s,14s,17s)-10,13-dimethyl-3-[(2r,3r,4s,5s,6r)-3,4,5-trihydroxy-6-(hydroxymethyl)oxan-2-yl]oxy-2,3,4,5,6,7,8,9,11,12,14,15,16,17-tetradecahydro-1h-cyclopenta[a]phenanthren-17-yl]-2h-furan-5-one Chemical compound O([C@@H]1C[C@H]2CC[C@@H]3[C@@H]([C@]2(CC1)C)CC[C@]1([C@H]3CC[C@@H]1C=1COC(=O)C=1)C)[C@@H]1O[C@H](CO)[C@@H](O)[C@H](O)[C@H]1O ZHVOBYWXERUHMN-KVJKMEBSSA-N 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 238000004611 spectroscopical analysis Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Herstellungsverfahren für eine Halbleiterstruktur durch selektives isotropes Ätzen einer Siliziumdixidschicht (10) auf einer Siliziumnitridschicht (3) mit den Schritten:
Bereitstellen eines Halbleitersubstrats (1);
Vorsehen einer Siliziumnitridschicht (3) auf einer Oberfläche (OF1) des Halbleitersubstrats (1);
Vorsehen einer Siliziumdioxidschicht (10) auf mindestens einer Oberfläche (OF2, OF3) der Siliziumnitridschicht (3); und
selektives isotropes Ätzen der Siliziumdioxidschicht (10) gegenüber der Siliziumnitridschicht (3) auf der mindestens einen Oberfläche (OF2, OF3) der Siliziumnitridschicht (3) in einem Plasmaätzschritt (E2) in einer induktiv gekoppelten Plasmaätzkammer bei einer an die Kathode angelegten Biasleistung von ungefähr 0 W mit einer Gasmischung aus CF4 und einem Inertgas, insbesondere Argon.Manufacturing method for a semiconductor structure by selective isotropic etching of a silicon dioxide layer (10) on a silicon nitride layer (3) with the steps:
Providing a semiconductor substrate (1);
Providing a silicon nitride layer (3) on a surface (OF1) of the semiconductor substrate (1);
Providing a silicon dioxide layer (10) on at least one surface (OF2, OF3) of the silicon nitride layer (3); and
selective isotropic etching of the silicon dioxide layer (10) with respect to the silicon nitride layer (3) on the at least one surface (OF2, OF3) of the silicon nitride layer (3) in a plasma etching step (E2) in an inductively coupled plasma etching chamber with a bias power of approximately 0 applied to the cathode W with a gas mixture of CF 4 and an inert gas, in particular argon.
Description
Die vorliegende Erfindung betrifft ein Herstellungsverfahren für eine Halbleiterstruktur, durch selektives isotropes Ätzen einer Siliziumdioxidschicht auf einer Siliziumnitridschicht.The present invention relates to a manufacturing process for a semiconductor structure, by selective isotropic etching of a Silicon dioxide layer on a silicon nitride layer.
Aus der
Die
Gemäß der Druckschrift von W.S. Cho et. al. mit dem Titel Selective oxide trench for dual damascene process in a transformer coupled plasma system. In: 6th International Conference on VLSI and CAD, ICVC'99, Seoul, South Korea, 26–27 Oct. 1999, Piscataway, NJ, USA, IEEE, 1999, ISBN 0-7803-5727-2, S. 147–150 bewirkt eine Verringerung der Bias-Leistung in einem C4F8-Plasmasystem ein Anwachsen der Siliziumoxyd-Siliziumnitrid-Selektivität.According to the publication by WS Cho et. al. entitled Selective oxide trench for dual damascene process in a transformer coupled plasma system. In: 6 th International Conference on VLSI and CAD, ICVC'99, Seoul, South Korea, Oct. 26-27 1999, Piscataway, NJ, USA, IEEE, 1999, ISBN 0-7803-5727-2, pp. 147-150 causes a decrease in the bias performance in a C 4 F 8 plasma system to increase the silicon oxide-silicon nitride selectivity.
Aus der
Aus der
Obwohl prinzipiell auf beliebige integrierte Schaltungen anwendbar, werden die vorliegende Erfindung sowie die hier zugrundeliegende Problematik in Bezug auf Halbleiterstrukturen in Silizium-Technologie erläutert.Although in principle on any Integrated circuits applicable, the present invention as well as the underlying problem with regard to semiconductor structures explained in silicon technology.
Bei vielen Halbleiterstrukturen ist es erforderlich, eine Siliziumdioxidschicht sehr selektiv gegenüber einer Siliziumnitridschicht, d.h. ohne merkbare Siliziumnitridverluste, zu ätzen. Bisher wurde dieses Problem dadurch gelöst, daß eine Ätzung mit polymerisierender Chemie in einem reaktiven Ionenätzschritt vorgenommen wurde. Bisher wurden hohe Selektivitäten meist unter Nutzung kohlenstoffreicher Fluorkohlen-Wasserstoffe (CxFy/Ar) erreicht. CF4/Ar-Gemische gelten als nicht besonders selektiv.With many semiconductor structures, it is necessary to etch a silicon dioxide layer very selectively with respect to a silicon nitride layer, ie without noticeable silicon nitride losses. So far, this problem has been solved by etching with polymerizing chemistry in a reactive ion etching step. So far, high selectivities have mostly been achieved using carbon-rich fluorocarbons (CxFy / Ar). CF 4 / Ar mixtures are not considered to be particularly selective.
Nachteile einer derartigen polymerisierenden Chemie sind die dadurch bewirkte Verschmutzung der Ätzkammer und das zum Teil komplizierte Handling der eingesetzten Spezialgase. Beispielsweise muß beim Einsatz von C4F8, welches im Normalzustand flüssig ist, eine Hardware-Modifikation durchgeführt werden, um die Gasleitung zu beheizen.Disadvantages of such a polymerizing chemistry are the pollution of the etching chamber caused thereby and the sometimes complicated handling of the special gases used. For example, when using C 4 F 8 , which is liquid in the normal state, a hardware modification must be carried out in order to heat the gas line.
Die Aufgabe der vorliegenden Erfindung besteht deshalb darin, ein verbessertes Herstellungsverfahren für eine Halbleiterstruktur bereitzustellen, das es ermöglicht, auf einfachere Weise eine Siliziumdioxidschicht sehr selektiv zu einer darunter liegenden Siliziumnitridschicht zu entfernen.The object of the present invention is therefore an improved manufacturing process for a semiconductor structure to provide, which enables a silicon dioxide layer very selectively in a simpler way to remove an underlying silicon nitride layer.
Erfindungsgemäss wird diese Aufgabe durch das in Anspruch 1 angegebene Herstellungsverfahren gelöst.According to the invention, this object is achieved by solved manufacturing method specified in claim 1.
Die Vorteile des erfindungsgemässen Herstellungsverfahrens liegen insbesondere darin, dass sich mit dem erfindungsgemässen Verfahren der Siliziumnitridverlust auf einen sehr geringen Wert bzw. nahezu Null einstellen lässt. Mit dem erfindungsgemäßen Plasmaätzschritt kann also unter den eingestellten Bedingungen Siliziumdioxid selektiv zu Siliziumnitrid entfernt werden. Die Selektivität kann dabei über die Biasleistung in einem gewissen Rahmen gesteuert werden. CF4 und inerte Gase, wie z.B. Argon, sind Standardgase und können ohne Probleme und weiteren Aufwand auf allen Kammertypen eingesetzt werden. An vielen Ätzkammern sind sie standardmäßig verfügbar.The advantages of the manufacturing method according to the invention are, in particular, that the silicon nitride loss can be set to a very low value or almost zero using the method according to the invention. With the plasma etching step according to the invention, silicon dioxide can be selectively removed to silicon nitride under the set conditions. The selectivity can be controlled to a certain extent via the bias power. CF 4 and inert gases, such as argon, are standard gases and can be used on all types of chamber without any problems or additional effort. They are available as standard on many etching chambers.
Die der vorliegenden Erfindung zugrundeliegende Idee besteht darin, dass ein selektives Ätzen der Siliziumdioxidschicht auf der mindestens einen Oberfläche der Siliziumnitridschicht in einem Plasmaätzschritt in einer induktiv gekoppelten Plasmaätzkammer bei einer sehr geringen oder verschwindenden an die Kathode angelegten Biasleistung mit einer Gasmischung aus CF4 und einem inerten Gas, insbesondere Ar, durchgeführt wird. Mit anderen Worten wurde erfindungsgemäß ein Prozeßregime für ein CF4/Ar-Plasma in einer induktiv gekoppelten Ätzkammer gefunden, bei dem unerwarteterweise hohe Selektivitäten der Ätzung von Siliziumdioxid zu Siliziumnitrid auftreten.The idea underlying the present invention is that selective etching of the silicon dioxide layer on the at least one surface of the silicon nitride layer in a plasma etching step in an inductively coupled plasma etching chamber with a very low or vanishing bias power applied to the cathode with a gas mixture of CF 4 and an inert one Gas, especially Ar, is carried out. In other words, according to the invention, a process regime for a CF 4 / Ar plasma was found in an inductively coupled etching chamber, in which unexpectedly high selectivities of the etching of silicon dioxide to silicon nitride occur.
Erklärt wird das beobachtete und unerwartete Phänomen mit der Ausbildung einer dünnen Passivierungsschicht auf dem Siliziumnitrid, welches ohne Bias-Leistung, d.h. ohne Sputter-Angriff durch eine angelegte Bias-Leistung, einen chemischen Angriff reaktiver Spezies aus dem Plasma verhindert. Auf dem Siliziumdioxid bildet sich diese Passivierung nicht aus. Dabei sei erwähnt, daß die Ätzrate der erfindungsgemäßen Plasmaätzung bei Gräben mit steigender Tiefe abnimmt, da hier eine Verarmung der Ätzradikale auftritt. Die Selektivitätsverhältnisse ändern sich nicht. Somit eignet sich das erfin dungsgemäße Verfahren insbesondere für oberflächennahe Ätzungen.The observed and is explained unexpected phenomenon with the formation of a thin Passivation layer on the silicon nitride, which has no bias performance, i.e. without sputter attack through an applied bias, a chemical attack more reactive Species from the plasma prevented. Forms on the silicon dioxide this passivation is not out. It should be mentioned that the etching rate of the plasma etching according to the invention at trenches decreases with increasing depth because the etching radicals become depleted occurs. The selectivity ratios change Not. The method according to the invention is therefore particularly suitable for near-surface etching.
In den Unteransprüchen finden sich vorteilhafte Weiterbildungen und Verbesserungen des Gegenstandes der Erfindung.There are advantageous ones in the subclaims Developments and improvements to the subject matter of the invention.
Gemäss einer bevorzugten Weiterbildung wird vor dem Vorsehen einer Siliziumdioxidschicht die Siliziumnitridschicht zur einer Hartmaske strukturiert und werden mit der Hartmaske ein oder mehrere Gräben in das Halbleitersubstrat in einem Grabenätzschritt geätzt.According to a preferred development, the silicon nitride layer becomes a hard mask before the provision of a silicon dioxide layer and one or more trenches are etched into the semiconductor substrate in a trench etching step using the hard mask.
Gemäss einer weiteren bevorzugten Weiterbildung wird die Siliziumdioxidschicht über der Hartmaske und den Gräben abgeschieden, so dass durch sie eine obere Oberfläche der Siliziumnitridschicht, seitliche Oberflächen der Siliziumnitridschicht, Seitenflächen der Gräben und Bodenflächen der Gräben bedeckt werden.According to another preferred Further training, the silicon dioxide layer is deposited over the hard mask and the trenches, so that through them an upper surface of the silicon nitride layer, lateral surfaces the silicon nitride layer, side surfaces of the trenches and bottom surfaces of the Trenches covered become.
Gemäss einer weiteren bevorzugten Weiterbildung wird ein anisotropes Vorätzen der Siliziumdioxidschicht auf der mindestens einen Oberfläche der Siliziumnitridschicht in einem weiteren Plasmaätzschritt in der induktiv gekoppelten Plasmaätzkammer bei einer höheren an die Kathode angelegten Biasleistung von mindestens 100 W mit einer Gasmischung aus CF4 und einem Inertgas, insbesondere Ar, sowie SiF4 und Sauerstoff durchgeführt.According to a further preferred development, anisotropic pre-etching of the silicon dioxide layer on the at least one surface of the silicon nitride layer is carried out in a further plasma etching step in the inductively coupled plasma etching chamber with a higher bias power of at least 100 W applied to the cathode with a gas mixture of CF 4 and an inert gas, in particular Ar, as well as SiF 4 and oxygen.
Gemäss einer weiteren bevorzugten Weiterbildung wird beim selektiven isotropen Ätzen im Plasmaätzschritt das Siliziumdioxid zumindest im oberen Bereich von den seitlichen und horizontalen Oberflächen der Siliziumnitridschicht entfernt.According to another preferred Further training is in selective isotropic etching in the plasma etching step the silicon dioxide at least in the upper area from the side and horizontal surfaces removed the silicon nitride layer.
Gemäss einer weiteren bevorzugten Weiterbildung wird beim anisotropen Vorätzen der Siliziumdioxidschicht im weiteren Plasmaätzschritt eine Endpunkterkennung mittels optischer Emissionsspektroskopie durchgeführt.According to another preferred Further training is in the anisotropic pre-etching of the silicon dioxide layer in the further plasma etching step endpoint detection using optical emission spectroscopy carried out.
Gemäss einer weiteren bevorzugten Weiterbildung wird das anisotrope Vorätzen der Siliziumdioxidschicht im weiteren Plasmaätzschritt eine vorbestimmte Zeitspanne lang durchgeführt, welche z.B. derart bemessen ist, dass eine stark verdünnte Siliziumdioxidschicht auf der oberen Oberfläche der Siliziumnitridschicht zurückbleibt. Es muß nicht notwendigerweise SiO2 auf der Oberfläche verbleiben, es kann auch eine blanke Siliziumnitrid-Oberfläche sein. In diesem Fall wird beim selektiven Ätzen nur das SiO2 im Graben zurückgenommen und die Siliziumnitrid-Oberfläche bleibt unangetastet.According to a further preferred development, the anisotropic pre-etching of the silicon dioxide layer is carried out in the further plasma etching step for a predetermined period of time, which is dimensioned, for example, such that a highly diluted silicon dioxide layer remains on the upper surface of the silicon nitride layer. SiO 2 does not necessarily have to remain on the surface, it can also be a bare silicon nitride surface. In this case, only the SiO 2 in the trench is removed during the selective etching and the silicon nitride surface remains untouched.
Gemäss einer weiteren bevorzugten Weiterbildung wird das Inertgas beim selektiven isotropen Ätzen der Siliziumdioxidschicht im Plasmaätzschritt im Verhältnis 1 : 1 zum CF4 zugeführt.According to a further preferred development, the inert gas is supplied during the selective isotropic etching of the silicon dioxide layer in the plasma etching step in a ratio of 1: 1 to CF 4 .
Ein Ausführungsbeispiel der Erfindung ist in den Zeichnungen dargestellt und in der nachfolgenden Beschreibung näher erläutert.An embodiment of the invention is shown in the drawings and in the description below explained in more detail.
Das hier angeführte Ausführungsbeispiel entstammt einem Kragenätzprozeß zur Herstellung von Halbleiterspeicherzellen mit Grabenkondensatoren.The exemplary embodiment mentioned here comes from one Collar etching process for the production of Semiconductor memory cells with trench capacitors.
In
Unter Verwendung der strukturierten
Siliziumnitridschicht
Wie in
Im folgenden wird die resultierende
Struktur in einer induktiv gekoppelten Plasmaätzkammer einem ersten Plasmaätzschritt
E1 unterworfen. Bei diesem ersten in
Im folgenden Schritt, welcher nachstehend mit
Bezug auf
In diesem Zusammenhang sei noch erwähnt, daß die Siliziumdioxidschicht
Aufgrund der hohen Selektivität des zweiten Plasmaätzschritts
läßt sich
weiterhin erreichen, daß die
Dicke d1 der Siliziumnitridschicht
Die vorliegende Erfindung ist nicht nur für die Herstellung von Grabenkondensatoren für Halbleiterspeicher zellen anwendbar, sondern prinzipiell immer dann, wenn vorzugsweise dünne Siliziumdioxidschichten sehr selektiv gegenüber Siliziumnitrid geätzt werden sollen, insbesondere in Verbindung mit vorhergehenden anisotropen Ätzprozessen mit ähnlichen Gasmischungen.The present invention is not only for the production of trench capacitors for semiconductor memory cells applicable, but in principle whenever thin silicon dioxide layers are preferred very selective towards Etched silicon nitride should be, especially in connection with previous anisotropic etching processes with similar ones Gas mixtures.
- 11
- Silizium-HalbleitersubstratSilicon semiconductor substrate
- 5a, 5b5a, 5b
- Grabendig
- 33
- Hartmaske aus Siliziumnitridhard mask made of silicon nitride
- 1010
- Siliziumdioxidschichtsilicon dioxide
- OF1, OF2, OF3OF1, OF2, OF3
- Oberflächesurface
- SFSF
- Seitenflächenfaces
- BFBF
- Bodenflächenfloor surfaces
- d0, d1d0, d1
- Dicke der Hartmaske aus Siliziumnitridthickness the hard mask made of silicon nitride
- E1, E2E1, E2
- Ätzschritteetching
Claims (9)
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Application Number | Priority Date | Filing Date | Title |
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DE10245671A DE10245671B4 (en) | 2002-09-30 | 2002-09-30 | Manufacturing method for a semiconductor structure by selective isotropic etching of a silicon dioxide layer on a silicon nitride layer |
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Publication Number | Publication Date |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5783475A (en) * | 1995-11-13 | 1998-07-21 | Motorola, Inc. | Method of forming a spacer |
US6037262A (en) * | 1998-06-15 | 2000-03-14 | Lsi Logic Corporation | Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure |
DE10016938A1 (en) * | 1999-05-05 | 2000-11-16 | Ibm | Etching oxide layer on nitride layer, comprises preparing plasma derived from carbonaceous and fluorine-containing gas and gas containing nitrogen, and etching in plasma |
US6387287B1 (en) * | 1998-03-27 | 2002-05-14 | Applied Materials, Inc. | Process for etching oxide using a hexafluorobutadiene and manifesting a wide process window |
DE10053780A1 (en) * | 2000-10-30 | 2002-05-16 | Infineon Technologies Ag | Process for structuring a silicon oxide layer |
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2002
- 2002-09-30 DE DE10245671A patent/DE10245671B4/en not_active Expired - Fee Related
Patent Citations (5)
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US5783475A (en) * | 1995-11-13 | 1998-07-21 | Motorola, Inc. | Method of forming a spacer |
US6387287B1 (en) * | 1998-03-27 | 2002-05-14 | Applied Materials, Inc. | Process for etching oxide using a hexafluorobutadiene and manifesting a wide process window |
US6037262A (en) * | 1998-06-15 | 2000-03-14 | Lsi Logic Corporation | Process for forming vias, and trenches for metal lines, in multiple dielectric layers of integrated circuit structure |
DE10016938A1 (en) * | 1999-05-05 | 2000-11-16 | Ibm | Etching oxide layer on nitride layer, comprises preparing plasma derived from carbonaceous and fluorine-containing gas and gas containing nitrogen, and etching in plasma |
DE10053780A1 (en) * | 2000-10-30 | 2002-05-16 | Infineon Technologies Ag | Process for structuring a silicon oxide layer |
Non-Patent Citations (1)
Title |
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CHO, W.S., u.a.: Selective oxide trench for dual damascence process in a transformator coupled plasma system, in: 6th International Conference on VLSI and CAD, ICVC '99, Seoul, South Korea, 26-27 Oct. 1999, Piscataway, NJ, USA, IEEE, 1999, ISBN 0-7803-5727-2, S. 147-150 * |
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