DE102015212383B4 - electronic component - Google Patents

electronic component Download PDF

Info

Publication number
DE102015212383B4
DE102015212383B4 DE102015212383.9A DE102015212383A DE102015212383B4 DE 102015212383 B4 DE102015212383 B4 DE 102015212383B4 DE 102015212383 A DE102015212383 A DE 102015212383A DE 102015212383 B4 DE102015212383 B4 DE 102015212383B4
Authority
DE
Germany
Prior art keywords
electronic component
conductor track
circuit board
layer
protective layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE102015212383.9A
Other languages
German (de)
Other versions
DE102015212383A1 (en
Inventor
Karin Beart
Frank Fella
Wolfgang Grübl
Thomas Schmidt
Bernhard Schuch
Martin Steinau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vitesco Technologies Germany GmbH
Original Assignee
Vitesco Technologies Germany GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vitesco Technologies Germany GmbH filed Critical Vitesco Technologies Germany GmbH
Priority to DE102015212383.9A priority Critical patent/DE102015212383B4/en
Publication of DE102015212383A1 publication Critical patent/DE102015212383A1/en
Application granted granted Critical
Publication of DE102015212383B4 publication Critical patent/DE102015212383B4/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894Materials of the insulating layers or coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367Cooling facilitated by shape of device
    • H01L23/3677Wire-like or pin-like cooling fins or heat sinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85447Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909Post-treatment of the connector or wire bonding area
    • H01L2224/8592Applying permanent coating, e.g. protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01Dielectrics
    • H05K2201/0137Materials
    • H05K2201/0179Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/049Wire bonding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • H05K3/282Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

Elektronische Komponente (E), umfassend eine Leiterplatte (1) mit wenigstens einer elektrisch leitenden Leiterbahn (1.1), wobei die wenigstens eine Leiterbahn (1.1) mit einer Schutzschicht (6) versehen ist, wobei die Schutzschicht (6) eine SiCN-Schicht umfasst, wobei die elektronische Komponente (E) mindestens ein elektronisches Bauteil (2) umfasst, wobei das mindestens eine elektronische Bauteil (2) mittels mindestens eines Bonddrahts (3) elektrisch leitend mit der wenigstens einen Leiterbahn (1.1) in einem Verbindungsbereich verbunden ist, von dem die Schutzschicht (6) entfernt ist.Electronic component (E), comprising a printed circuit board (1) with at least one electrically conductive conductor track (1.1), the at least one conductor track (1.1) being provided with a protective layer (6), the protective layer (6) comprising a SiCN layer , wherein the electronic component (E) comprises at least one electronic component (2), wherein the at least one electronic component (2) is electrically conductively connected to the at least one conductor track (1.1) in a connection area by means of at least one bonding wire (3), from which the protective layer (6) is removed.

Description

Die Erfindung betrifft eine elektronische Komponente gemäß dem Oberbegriff des Anspruchs 1. Die Erfindung betrifft weiterhin ein Verfahren zur Herstellung einer solchen elektronischen Komponente.The invention relates to an electronic component according to the preamble of claim 1. The invention also relates to a method for producing such an electronic component.

Elektronische Komponenten in Form integrierter Schaltungen umfassen üblicherweise elektronische Baugruppen, die auf einer Leiterplatte zu einer elektronischen Schaltungsanordnung zusammengeführt sind. Derartige elektronische Komponenten werden beispielsweise in Steuergeräten für Kraftfahrzeuge, z. B. in Getriebesteuergeräten, eingesetzt.Electronic components in the form of integrated circuits usually include electronic assemblies that are combined on a printed circuit board to form an electronic circuit arrangement. Such electronic components are used, for example, in control units for motor vehicles, e.g. B. in transmission control units used.

Zur Herstellung derartiger elektronischer Komponenten wird üblicherweise eine Leiterplatte eingesetzt, die mehrere Lagen mit elektrisch leitenden Leiterbahnen umfasst. Die Leiterbahnen werden beispielsweise aus Kupfer gefertigt und mittels Durchkontaktierungen elektrisch leitend miteinander verbunden. Die Leiterbahnen auf einer obersten Lage der Leiterplatte können zudem mit einer Oberseitenmetallisierung versehen werden, welche beispielsweise eine Kombination aus Nickel und Gold oder Nickel, Gold und Palladium umfasst. Mittels der Oberseitenmetallisierung wird zum einen eine Korrosion des Kupfers der Leiterbahnen verringert. Zum anderen wird eine Oberfläche der Leiterplatte zur stoffschlüssigen Aufnahme elektrisch passiver und aktiver Bauteile konditioniert. Die stoffschlüssige Aufnahme erfolgt beispielsweise mittels eines elektrisch leitfähigen Klebstoffs, z. B. Silberleitkleber. Alternativ können die Bauteile auch auf die Oberfläche der Leiterplatte gelötet werden. Die elektrische Kontaktierung der Bauteile erfolgt anschließend mittels Bonddrähten, z. B. Gold- und/oder Aluminiumbonddrähte.To produce such electronic components, a printed circuit board is usually used, which includes a number of layers with electrically conductive conductor tracks. The conductor tracks are made of copper, for example, and are connected to one another in an electrically conductive manner by means of vias. The conductor tracks on an uppermost layer of the printed circuit board can also be provided with a topside metallization, which includes a combination of nickel and gold or nickel, gold and palladium, for example. On the one hand, corrosion of the copper of the conductor tracks is reduced by means of the top-side metallization. On the other hand, a surface of the printed circuit board is conditioned for the cohesive acceptance of electrically passive and active components. The integral recording takes place, for example, by means of an electrically conductive adhesive, z. B. Silver conductive adhesive. Alternatively, the components can also be soldered onto the surface of the printed circuit board. The components are then electrically contacted using bonding wires, e.g. B. gold and / or aluminum bonding wires.

Aus der US 2015 / 0 054 017 A1 ist ein LED-Chip-Gehäuse mit einer topographischen Glasbeschichtung auf der Oberseite zur Verbesserung der Wärmeableitung bekannt. Eine kreisförmige Wand wird optional gebaut, um den LED-Chip zu umgeben, um Lichtstrahlen von den LED-Chips zu reflektieren. Die Glasbeschichtung erstreckt sich weiter, um die innere Wandoberfläche der kreisförmigen Wand zu bedecken. Je größer die Fläche ist, die die Glasbeschichtung bedeckt, desto mehr Wärme leitet das Gehäuse in einer Zeiteinheit ab. Das LED-Chip-Gehäuse weist dadurch eine höhere Wärmeableitung auf und trägt zu einer längeren Lebensdauer des LED-Chip-Gehäuses bei als ein herkömmliches. Der Erfindung liegt die Aufgabe zu Grunde, eine gegenüber dem Stand der Technik verbesserte elektronische Komponente anzugeben. Der Erfindung liegt weiterhin die Aufgabe zu Grunde ein geeignetes Verfahren zur Herstellung einer solchen elektronischen Komponente anzugeben.US 2015/0 054 017 A1 discloses an LED chip package with a topographical glass coating on the top to improve heat dissipation. A circular wall is optionally built to surround the LED chip to reflect light rays from the LED chips. The glass coating continues to cover the inner wall surface of the circular wall. The larger the area covered by the glass coating, the more heat the case dissipates in a unit of time. As a result, the LED chip package has higher heat dissipation and contributes to the longer lifespan of the LED chip package than a conventional one. The invention is based on the object of specifying an electronic component that is improved over the prior art. The invention is also based on the object of specifying a suitable method for producing such an electronic component.

Hinsichtlich der elektronischen Komponente wird die Aufgabe erfindungsgemäß mit den in Anspruch 1 angegebenen Merkmalen gelöst. Hinsichtlich des Verfahrens wird die Aufgabe erfindungsgemäß mit den in Anspruch 7 angegebenen Merkmalen gelöst.With regard to the electronic component, the object is achieved according to the invention with the features specified in claim 1 . With regard to the method, the object is achieved according to the invention with the features specified in claim 7 .

Vorteilhafte Ausgestaltungen der Erfindung sind Gegenstand der Unteransprüche.Advantageous configurations of the invention are the subject matter of the dependent claims.

Eine elektronische Komponente umfasst eine Leiterplatte mit wenigstens einer elektrisch leitenden Leiterbahn, welche mit einer Schutzschicht versehen ist. Erfindungsgemäß ist vorgesehen, dass die Schutzschicht eine SiCN-Schicht umfasst.An electronic component includes a printed circuit board with at least one electrically conductive conductor track, which is provided with a protective layer. According to the invention it is provided that the protective layer comprises a SiCN layer.

Die elektronische Komponente ist zur Anordnung in einem Steuergerät für ein Kraftfahrzeug, beispielsweise in einem Getriebesteuergerät, geeignet. Die SiCN-Schicht umfasst als Bestandteile Silicium, Kohlenstoff und Stickstoff (SiCN ist auch als Silicon Carbon Nitride bekannt), welche sich selektiv an ein elektrisch leitendes Material der Leiterbahn, die vorzugsweise aus Kupfer gebildet ist, anlagern. Dadurch wird zuverlässig das Eindringen von Feuchtigkeit und Sauerstoff in das elektrisch leitende Material der Leiterbahn verhindert oder zumindest verringert, so dass eine Ausbildung von Oxidschichten auf der Leiterbahn verhindert wird. Oxidschichten sind insbesondere deshalb zu verhindern, da diese eine elektrische Kontaktierung von Bauteilen auf der Leiterplatte mittels Drahtbonden, z. B. mittels Kupfer-Drahtbonden, erschwert oder gar nicht erst ermöglicht.The electronic component is suitable for arrangement in a control unit for a motor vehicle, for example in a transmission control unit. The components of the SiCN layer are silicon, carbon and nitrogen (SiCN is also known as silicon carbon nitride), which selectively attaches to an electrically conductive material of the conductor track, which is preferably made of copper. This reliably prevents or at least reduces the penetration of moisture and oxygen into the electrically conductive material of the conductor track, so that the formation of oxide layers on the conductor track is prevented. Oxide layers are to be prevented in particular because they prevent electrical contacting of components on the printed circuit board by means of wire bonding, e.g. B. by means of copper wire bonding, difficult or not even possible.

Die Verwendung einer SiCN-Schichtverringert dabei das Risiko von Korrosionsvorgängen, wie es beispielsweise bei nickelhaltigen Schutzschichten bekannt ist.The use of a SiCN layer reduces the risk of corrosion processes, as is known, for example, with protective layers containing nickel.

Eine Ausgestaltung der Erfindung sieht vor, dass die wenigstens eine Leiterbahn aus Kupfer gebildet ist, welches eine sehr gute elektrische Leitfähigkeit aufweist und zudem kostengünstig ist.One embodiment of the invention provides that the at least one conductor track is formed from copper, which has very good electrical conductivity and is also inexpensive.

Erfindungsgemäß umfasst die elektronische Komponente mindestens ein elektronisches Bauteil, welches elektrisch leitend mit der wenigstens einen Leiterbahn verbunden ist. Das elektronische Bauteil ist beispielsweise eine gehäuste und/oder ungehäuste Halbleiterkomponente, ein Sensor, ein elektrischer Widerstand und/oder ein elektrischer Kondensator, wobei das elektronische Bauteil Bestandteil einer auf der Leiterplatte angeordneten Schaltung ist.According to the invention, the electronic component comprises at least one electronic component which is electrically conductively connected to the at least one conductor track. The electronic component is, for example, a housed and/or unhoused semiconductor component, a sensor, an electrical resistor and/or an electrical capacitor, the electronic component being part of a circuit arranged on the printed circuit board.

Das mindestens eine elektronische Bauteil wird erfindungsgemäß mittels eines Bonddrahts oder mehrerer Bonddrähte elektrisch leitend mit der wenigstens einen Leiterbahn verbunden, wobei der Bonddraht vorzugsweise aus Kupfer gebildet ist. Aufgrund der Verwendung von Kupfer sowohl für die wenigstens eine Leiterbahn als auch für den Bonddraht wird eine Monometallverbindung hergestellt, bei welcher Korrosionsvorgänge, insbesondere eine bei Bimetallverbindungen bekannte Halogenkorrosion, sowie ein sogenannter Kirkendall-Effekt (auch als „Purpurpest“ bekannt), bei welchem in einer Bimetallverbindung beide Metalle ineinander diffundieren und intermetallische Phasen ausgebildet werden, zuverlässig verhinderbar sind.According to the invention, the at least one electronic component is electrically conductively connected to the at least one conductor track by means of a bonding wire or a plurality of bonding wires, the bonding wire preferably being made of copper. Due to the use of copper both for the at least one conductor track and for the bonding wire, a monometal connection is produced in which corrosion processes, in particular halogen corrosion known in bimetal connections, as well as a so-called Kirkendall effect (also known as "purple plague"), in which in a bimetallic connection, both metals diffuse into each other and intermetallic phases are formed, can be reliably prevented.

Darüber hinaus kann mittels der Verwendung von Kupfer für die Leiterbahn und den Bonddraht auf zusätzliche kostenintensive Metallisierungsschichten, z. B. Nickel/Gold (NiAu) oder Nickel/Palladium/Gold (NiPdAu) verzichtet werden, wie es bei der Verwendung von Goldbonddrähten erforderlich wäre, um eine elektrische Anbindung eines Bauteils zu ermöglichen.In addition, by using copper for the conductor track and the bonding wire, additional cost-intensive metallization layers, e.g. B. nickel / gold (NiAu) or nickel / palladium / gold (NiPdAu) are dispensed with, as would be required when using gold bonding wires to enable electrical connection of a component.

Gemäß einer weiteren Ausgestaltung der Erfindung umfasst die Leiterplatte einen Trägerkörper, der aus einer Mehrzahl von Schichten gebildet ist. Die Schichten sind beispielsweise Glasfasermatten, die zur adhäsiven Verbindung untereinander mit einem Harz vorimprägniert sind.
Die wenigstens eine Leiterbahn ist dabei auf einer ersten Schicht der Leiterplatte angeordnet, wobei die erste Schicht eine Oberflächenseite der Leiterplatte bildet. Zwischen den Schichten können elektrisch leitende Innenlagen angeordnet sein, die beispielsweise analog zu den Leiterbahnen aus Kupfer gebildet sind. Eine elektrische Verbindung der Innenlagen unterschiedlicher Schichten erfolgt z. B. mittels Durchkontaktierungen (auch als „Vias“ bekannt).
According to a further embodiment of the invention, the printed circuit board includes a carrier body which is formed from a plurality of layers. The layers are, for example, glass fiber mats that are pre-impregnated with a resin for adhesive connection to one another.
The at least one conductor track is arranged on a first layer of the printed circuit board, with the first layer forming a surface side of the printed circuit board. Electrically conductive inner layers can be arranged between the layers, which are formed from copper, for example, analogously to the conductor tracks. An electrical connection of the inner layers of different layers is made z. B. by means of platings (also known as “vias”).

Zum Schutz des mindestens einen elektronischen Bauteils, der Bonddrähte sowie der Leiterbahnen werden diese form- und stoffschlüssig von einer Kapselung (Molding) umgeben, die beispielsweise aus einem aushärtbaren, elektrisch isolierenden Material gebildet ist. Damit wird die elektronische Komponente vor äußeren Einflüssen, wie z. B. Späne und korrosiven Medien, wie z. B. Getriebeöle, geschützt. Weiterhin ist damit die auf der Leiterplatte angeordnete Schaltung vor Kurzschlüssen geschützt.To protect the at least one electronic component, the bonding wires and the conductor tracks, these are surrounded by an encapsulation (molding) in a form-fitting and material-locking manner, which is formed, for example, from a hardenable, electrically insulating material. This protects the electronic component from external influences, such as B. chips and corrosive media such. B. gear oils protected. Furthermore, the circuit arranged on the printed circuit board is thus protected against short circuits.

Bei einem Verfahren zur Herstellung der beschriebenen elektronischen Komponente wird die Leiterplatte mit der wenigstens einen Leiterbahn bereitgestellt. Anschließend wird die wenigstens eine Leiterbahn mit einer Schutzschicht versehen, wobei die Schutzschicht aus einer SiCN-Schicht hergestellt wird. In a method for producing the electronic component described, the printed circuit board is provided with the at least one conductor track. The at least one conductor track is then provided with a protective layer, the protective layer being produced from a SiCN layer.

Mittels der Verwendung einer SiCN-Schicht ist eine gegenüber dem Stand der Technik kostengünstigere Herstellung der elektronischen Komponente möglich. Dies ist insbesondere dadurch begründet, dass die Schutzschicht die Verwendung kostengünstiger Kupferbonddrähte ermöglicht, und somit ein zusätzliches, kostenintensives Metallisieren (Plating) der Leiterbahnen mit NiAu oder NiPdAu, wie es bei Goldbonddrähten Voraussetzung ist, nicht erforderlich ist.By using a SiCN layer, it is possible to produce the electronic component more cost-effectively than in the prior art. This is due in particular to the fact that the protective layer enables the use of inexpensive copper bonding wires, and therefore an additional, cost-intensive metallization (plating) of the conductor tracks with NiAu or NiPdAu, as is required with gold bonding wires, is not necessary.

Gemäß einer Ausgestaltung des Verfahrens wird die Schutzschicht mittels chemischer Gasphasenabscheidung auf die Oberfläche der Leiterplatte aufgebracht. Eine Schichtdicke der Schutzschicht ist vorzugsweise sehr gering, z. B. beträgt die Schichtdicke fünf Nanometer. Während der Kontaktierung des Bonddrahtes, insbesondere Kupferbonddrahts, im Kaltpressschweißverfahren wird die Schutzschicht in einem Verbindungsbereich der Leiterbahn und des Kupferbonddrahts durchgerieben.According to one configuration of the method, the protective layer is applied to the surface of the printed circuit board by means of chemical vapor deposition. A layer thickness of the protective layer is preferably very small, e.g. B. is the layer thickness five nanometers. During the contacting of the bonding wire, in particular copper bonding wire, in the cold pressure welding process, the protective layer is rubbed through in a connection area of the conductor track and the copper bonding wire.

Die Erfindung wird im Folgenden anhand einer Zeichnung näher erläutert.The invention is explained in more detail below with reference to a drawing.

Dabei zeigt:

  • 1 schematisch eine Schnittdarstellung eines erfindungsgemäßen Ausführungsbeispiels einer elektronischen Komponente.
It shows:
  • 1 schematically shows a sectional view of an exemplary embodiment of an electronic component according to the invention.

Die einzige 1 zeigt ein erfindungsgemäßes Ausführungsbeispiel einer elektronischen Komponente E in einer schematischen Schnittdarstellung.The only 1 shows an exemplary embodiment of an electronic component E in a schematic sectional view.

Die elektronische Komponente E ist beispielsweise ein Steuergerät für ein Kraftfahrzeug, z. B. ein Getriebesteuergerät, und umfasst eine Leiterplatte 1 als Schaltungsträger, auf der im vorliegenden Ausführungsbeispiel ein elektronisches Bauteil 2 als Bestandteil einer Schaltung angeordnet ist. Alternativ kann auch eine Mehrzahl elektronischer Bauteile 2 auf der Leiterplatte 1 angeordnet sein.The electronic component E is, for example, a control unit for a motor vehicle, z. B. a transmission control unit, and includes a printed circuit board 1 as a circuit carrier on which an electronic component 2 is arranged as part of a circuit in the present embodiment. Alternatively, a plurality of electronic components 2 can also be arranged on circuit board 1 .

Die Leiterplatte 1 umfasst einen mehrschichtigen Trägerkörper, welcher eine Mehrzahl von Schichten S1 bis Sn aufweist, die in Richtung einer Hochachse z übereinander angeordnet sind. Beispielsweise ist jede Schicht S1 bis Sn aus einer Glasfasermatte gebildet, die zur adhäsiven Verbindung mit einer angrenzenden Glasfasermatte mit einem Harz vorimprägniert ist. Derartige Glasfasermatten sind auch als Prepregs bekannt.The printed circuit board 1 comprises a multilayer carrier body which has a plurality of layers S1 to Sn which are arranged one above the other in the direction of a vertical axis z. For example, each layer S1 through Sn is formed of a glass fiber mat pre-impregnated with a resin for adhesive bonding to an adjacent glass fiber mat. Such glass fiber mats are also known as prepregs.

Auf einer oberen, ersten Schicht S1 sind elektrisch leitende Leiterbahnen 1.1 angeordnet, die aus Kupfer gebildet sind. Die Leiterbahnen 1.1 sind beispielsweise durch Ätzprozesse, wie z. B. Kupferätzung, herstellbar.Electrically conductive conductor tracks 1.1, which are made of copper, are arranged on an upper, first layer S1. The conductor tracks 1.1 are, for example, by etching processes such. B. copper etching, produced.

Weiterhin sind in Schichten S2 bis Sn unterhalb der ersten Schicht S1 elektrisch leitende Innenlagen 1.2 angeordnet, die vorzugsweise analog zu den Leiterbahnen 1.1 aus Kupfer gebildet sind und die einer elektrisch leitenden Verbindung der elektronischen Komponente E mit weiteren nicht gezeigten Komponenten und/oder einer elektrischen Verbindung einer auf der Leiterplatte 1 integrierten Schaltung dienen. Die Innenlagen 1.2 sind mittels Durchkontaktierungen 1.3 elektrisch und thermisch leitend miteinander verbunden. Die unterhalb des elektronischen Bauteil 2 angeordnete Leiterbahn 1.1, welche alternativ auch mehrere Leiterbahnen 1.1 repräsentieren kann, ist mittels einer Mehrzahl von Mikrovias 1.4 mit einer ersten Innenlage 1.2 unterhalb der ersten Schicht S1 elektrisch und thermisch leitend verbunden. Im gezeigten Ausführungsbeispiel ist diese erste Innenlage 1.2 weiterhin mit einer Rückseite 1.2.1 der Leiterplatte 1 mittels zwei Durchkontaktierungen 1.3 elektrisch und thermisch leitend verbunden, wobei die Rückseite 1.2.1 von einer weiteren elektrisch leitenden Kupferlage gebildet wird.Furthermore, electrically conductive inner layers 1.2 are arranged in layers S2 to Sn below the first layer S1 serve an integrated circuit on the printed circuit board 1. The inner layers 1.2 are connected to one another in an electrically and thermally conductive manner by means of vias 1.3. The conductor track 1.1 arranged below the electronic component 2, which can alternatively also represent a plurality of conductor tracks 1.1, is electrically and thermally conductively connected to a first inner layer 1.2 below the first layer S1 by means of a plurality of microvias 1.4. In the exemplary embodiment shown, this first inner layer 1.2 is also electrically and thermally conductively connected to a rear side 1.2.1 of the printed circuit board 1 by means of two vias 1.3, the rear side 1.2.1 being formed by a further electrically conductive copper layer.

Im vorliegenden Ausführungsbeispiel sind die Durchkontaktierungen 1.3 und die Mikrovias 1.4 als Bohrungen im Substrat der Leiterplatte 1 ausgebildet, die jeweils eine elektrisch leitende Innenbeschichtung aufweisen. Die Mikrovias 1.4 sind im Durchmesser kleiner ausgebildet als die Durchkontaktierungen 1.3.In the present exemplary embodiment, the vias 1.3 and the microvias 1.4 are designed as bores in the substrate of the printed circuit board 1, each of which has an electrically conductive inner coating. The microvias 1.4 have a smaller diameter than the vias 1.3.

Die auf der ersten Schicht S1 angeordneten Leiterbahnen 1.1 dienen der elektrischen Verbindung des gezeigten elektronischen Bauteils 2.The conductor tracks 1.1 arranged on the first layer S1 are used for the electrical connection of the electronic component 2 shown.

Das elektronische Bauteil 2 stellt im vorliegenden Ausführungsbeispiel eine Halbleiterkomponente, z. B. einen Mikrocontroller, dar. Alternativ kann das elektronische Bauteil 2 auch z. B. einen Sensor, einen elektrischen Widerstand oder einen elektrischen Kondensator darstellen.In the present exemplary embodiment, the electronic component 2 is a semiconductor component, e.g. B. a microcontroller. Alternatively, the electronic component 2 can also z. B. represent a sensor, an electrical resistor or an electrical capacitor.

Das elektronische Bauteil 2 ist auf einer Leiterbahn 1.1 angeordnet und mit dieser stoffschlüssig und elektrisch leitend verbunden, z. B. adhäsiv mittels eines elektrisch leitfähigen Klebstoffs.The electronic component 2 is arranged on a conductor track 1.1 and is connected to it in a cohesive and electrically conductive manner, e.g. B. adhesively by means of an electrically conductive adhesive.

Das elektronische Bauteil 2 ist mittels jeweils eines Bonddrahts 3 elektrisch leitend mit einer weiteren Leiterbahn 1.1 der Leiterplatte 1 verbunden. Die Bonddrähte 3 sind analog zu den Leiterbahnen 1.1 jeweils aus Kupfer gebildet. Alternativ kann das elektronische Bauteil 2 auch mittels eines Bonddrahts 3 oder mehrerer Bonddrähte 3 mit der Leiterplatte 1 elektrisch leitend verbunden werden.The electronic component 2 is electrically conductively connected to a further conductor track 1.1 of the printed circuit board 1 by means of a bonding wire 3 in each case. The bonding wires 3 are each made of copper, analogously to the conductor tracks 1.1. Alternatively, the electronic component 2 can also be electrically conductively connected to the printed circuit board 1 by means of a bonding wire 3 or a plurality of bonding wires 3 .

Zum Schutz vor Korrosions- und Oxidationsvorgängen des Kupfers der Leiterbahnen 1.1 sind diese mit einer Schutzschicht 6 versehen, die eine Schichtdicke von ca. fünf Nanometer aufweist. Die Bestandteile der Schutzschicht 6 lagern sich dabei selektiv an das Kupfer an und verhindern oder verringern zumindest dadurch Korrosions- und Oxidationsprozesse auf der Oberfläche der Leiterplatte 1, welche ein Drahtbonden der elektronischen Bauteile 2 erschwert oder gar nicht erst ermöglicht.To protect against corrosion and oxidation of the copper conductor tracks 1.1 these are provided with a protective layer 6, which has a layer thickness of about five nanometers. The components of the protective layer 6 accumulate selectively on the copper and thereby prevent or at least reduce corrosion and oxidation processes on the surface of the printed circuit board 1, which makes wire bonding of the electronic components 2 more difficult or not possible at all.

Die Schutzschicht 6 umfasst eine SiCN-Schicht, welche Silicium, Kohlenstoff und Stickstoff umfasst. Die Schutzschicht 6 schützt dabei die Oberfläche der Leiterplatte 1 insbesondere im Bereich der elektrisch leitenden Leiterbahnen 1.1 bis zur Kontaktierung der Bonddrähte 3. Wobei die Schutzschicht 6 im Verbindungsbereich der Leiterbahn 1.1 und des Bonddrahts 3 durchgerieben wird, so dass sich die Materialien der Leiterbahn 1.1 und des Bonddrahts 3, hierbei Kupfer, direkt miteinander verbindbar sind.The protective layer 6 comprises a SiCN layer comprising silicon, carbon and nitrogen. The protective layer 6 protects the surface of the printed circuit board 1, in particular in the area of the electrically conductive conductor tracks 1.1 up to the point where the bonding wires 3 are contacted. The protective layer 6 is worn through in the connection area of the conductor track 1.1 and the bonding wire 3, so that the materials of the conductor track 1.1 and of the bonding wire 3, in this case copper, can be connected directly to one another.

Die Schutzschicht 6 kann beim Kontaktieren der Bonddrähte 3 sowie beim Fixieren des elektronischen Bauteils 2 auf der Leiterplatte 1 durch mechanische Reibung auf einfache Art und Weise entfernt werden. Hierbei wird auf besonders vorteilhafte Art und Weise eine Monometallverbindung zwischen den Leiterbahnen 1.1 und den Bonddrähten 3 hergestellt, da diese jeweils aus Kupfer gebildet sind. Damit ist die mechanische Verbindung zwischen den Bonddrähten 3 und den Leiterbahnen 1.1 besonders stabil ausgebildet, wobei intermetallische Phasen, Korrosionsvorgänge und der Kirkendall-Effekt gegenüber Bimetallverbindungen zuverlässig verhindert werden können.The protective layer 6 can be removed in a simple manner by mechanical friction when contact is made with the bonding wires 3 and when the electronic component 2 is fixed on the printed circuit board 1 . In this case, a monometal connection is produced in a particularly advantageous manner between the conductor tracks 1.1 and the bonding wires 3, since these are each made of copper. The mechanical connection between the bonding wires 3 and the conductor tracks 1.1 is thus designed to be particularly stable, with intermetallic phases, corrosion processes and the Kirkendall effect being able to be reliably prevented in comparison with bimetallic connections.

Weiterhin ermöglicht eine derartige Monometallverbindung eine Kostenreduzierung bei der Herstellung der elektronischen Bauteile 2, da hierbei keine kostenintensive, zusätzliche Metallisierungsschicht erforderlich ist, wie es beispielsweise bei Goldbonddrähten der Fall ist.Furthermore, such a monometal connection enables a cost reduction in the manufacture of the electronic components 2, since no cost-intensive, additional metallization layer is required here, as is the case with gold bonding wires, for example.

Die Schutzschicht 6 selbst kann im Herstellungsverfahren der elektronischen Komponente E mittels chemischer Gasphasenabscheidung aufgebracht werden.The protective layer 6 itself can be applied in the manufacturing process of the electronic component E by means of chemical vapor deposition.

Zum weiteren Schutz der elektronischen Komponente E vor äußeren Einflüssen im Betrieb der elektronischen Komponente E, z. B. vor korrosiven Medien, wie z. B. Getriebeöle, vor Spänen und/oder Schadgasen etc., ist eine Kapselung 7 angeordnet, welche in Form eines Gehäuses (Molding) die erste Schicht S1 der Leiterplatte 1 sowie alle darauf angeordneten Komponenten, d. h. in Bezug auf das vorliegende Ausführungsbeispiel: das elektronische Bauteil 2 und die Bonddrähte 3, form- und stoffschlüssig umgibt.To further protect the electronic component E from external influences during operation of the electronic component E, z. B. against corrosive media such. B. gear oils, from chips and / or harmful gases, etc., an encapsulation 7 is arranged, which in the form of a housing (molding), the first layer S1 of the circuit board 1 and all components arranged thereon, d. H. in relation to the present exemplary embodiment: the electronic component 2 and the bonding wires 3 are surrounded in a form-fitting and cohesive manner.

Die Kapselung 7 ist aus einem elektrisch isolierenden Material, z. B. einem Duroplast, gebildet, welches mittels Spritzpressen (Transfer-Molding) oder Formpressen (Compression-Molding) auf die Leiterplatte 1 aufgebracht wird.The encapsulation 7 is made of an electrically insulating material, e.g. B. a thermoset, formed, which is applied to the circuit board 1 by means of transfer molding or compression molding.

BezugszeichenlisteReference List

11
Leiterplattecircuit board
1.11.1
Leiterbahntrace
1.21.2
Innenlageinner layer
1.2.11.2.1
Rückseiteback
1.31.3
Durchkontaktierungvia
1.41.4
Mikroviasmicrovias
22
elektronisches Bauteilelectronic component
33
Bonddrahtbonding wire
44
Bondverbindungbond connection
55
Leitlackconductive paint
66
Schutzschichtprotective layer
77
Kapselung encapsulation
EE
elektronische Komponenteelectronic component
S1S1
erste Schichtfirst layer
S2 bis SnS2 to Sn
Schicht layer
ze.g
Hochachsevertical axis

Claims (8)

Elektronische Komponente (E), umfassend eine Leiterplatte (1) mit wenigstens einer elektrisch leitenden Leiterbahn (1.1), wobei die wenigstens eine Leiterbahn (1.1) mit einer Schutzschicht (6) versehen ist, wobei die Schutzschicht (6) eine SiCN-Schicht umfasst, wobei die elektronische Komponente (E) mindestens ein elektronisches Bauteil (2) umfasst, wobei das mindestens eine elektronische Bauteil (2) mittels mindestens eines Bonddrahts (3) elektrisch leitend mit der wenigstens einen Leiterbahn (1.1) in einem Verbindungsbereich verbunden ist, von dem die Schutzschicht (6) entfernt ist.Electronic component (E), comprising a printed circuit board (1) with at least one electrically conductive conductor track (1.1), the at least one conductor track (1.1) being provided with a protective layer (6), the protective layer (6) comprising a SiCN layer , wherein the electronic component (E) comprises at least one electronic component (2), wherein the at least one electronic component (2) is electrically conductively connected to the at least one conductor track (1.1) in a connection area by means of at least one bonding wire (3), from which the protective layer (6) is removed. Elektronische Komponente (E) nach Anspruch 1, dadurch gekennzeichnet, dass die wenigstens eine Leiterbahn (1.1) aus Kupfer gebildet ist.Electronic component (E) after claim 1 , characterized in that the at least one conductor track (1.1) is made of copper. Elektronische Komponente (E) nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass der Bonddraht (3) aus Kupfer gebildet ist.Electronic component (E) after claim 1 or 2 , characterized in that the bonding wire (3) is made of copper. Elektronische Komponente (E) nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass die Leiterplatte (1) einen Trägerkörper umfasst, der aus einer Mehrzahl von Schichten (S1 bis Sn) gebildet ist.Electronic component (E) according to one of the preceding claims, characterized in that the circuit board (1) comprises a carrier body which is formed from a plurality of layers (S1 to Sn). Elektronische Komponente (E) nach Anspruch 4, dadurch gekennzeichnet, dass die wenigstens eine Leiterbahn (1.1) auf einer ersten Schicht (S1) der Leiterplatte (1) angeordnet ist, wobei die erste Schicht (S1) eine Oberflächenseite der Leiterplatte (1) bildet.Electronic component (E) after claim 4 , characterized in that the at least one conductor track (1.1) is arranged on a first layer (S1) of the printed circuit board (1), the first layer (S1) forming a surface side of the printed circuit board (1). Elektronische Komponente (E) nach Anspruch 4 oder 5, gekennzeichnet durch eine Kapselung (7), welche die erste Schicht (S1), den Bonddraht (3) und das mindestens eine elektronische Bauteil (2) form- und stoffschlüssig umgibt.Electronic component (E) after claim 4 or 5 , characterized by an encapsulation (7) which surrounds the first layer (S1), the bonding wire (3) and the at least one electronic component (2) in a form-fitting and cohesive manner. Verfahren zur Herstellung einer elektronischen Komponente (E) gemäß einem der vorhergehenden Ansprüche, wobei - die Leiterplatte (1) mit der wenigstens einen Leiterbahn (1.1) bereitgestellt wird, - die wenigstens eine Leiterbahn (1.1) mit einer Schutzschicht (6) versehen wird, - die Schutzschicht (6) aus einer SiCN-Schicht hergestellt wird, und - das mindestens eine elektronische Bauteil (2) mittels mindestens eines Bonddrahts (3) elektrisch leitend mit der wenigstens einen Leiterbahn (1.1) in einem Verbindungsbereich verbunden wird, von dem die Schutzschicht (6) entfernt wird, insbesondere durchgerieben wird.A method for producing an electronic component (E) according to any one of the preceding claims, wherein - the printed circuit board (1) is provided with the at least one conductor track (1.1), - the at least one conductor track (1.1) is provided with a protective layer (6), - the protective layer (6) is made of a SiCN layer, and - The at least one electronic component (2) is electrically conductively connected to the at least one conductor track (1.1) by means of at least one bonding wire (3) in a connection area from which the protective layer (6) is removed, in particular rubbed through. Verfahren nach Anspruch 7, dadurch gekennzeichnet, dass die Schutzschicht (6) mittels chemischer Gasphasenabscheidung auf die wenigstens eine Leiterbahn (1.1) aufgebracht wird.procedure after claim 7 , characterized in that the protective layer (6) is applied to the at least one conductor track (1.1) by means of chemical vapor deposition.
DE102015212383.9A 2015-07-02 2015-07-02 electronic component Active DE102015212383B4 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE102015212383.9A DE102015212383B4 (en) 2015-07-02 2015-07-02 electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102015212383.9A DE102015212383B4 (en) 2015-07-02 2015-07-02 electronic component

Publications (2)

Publication Number Publication Date
DE102015212383A1 DE102015212383A1 (en) 2017-01-05
DE102015212383B4 true DE102015212383B4 (en) 2023-06-01

Family

ID=57582863

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102015212383.9A Active DE102015212383B4 (en) 2015-07-02 2015-07-02 electronic component

Country Status (1)

Country Link
DE (1) DE102015212383B4 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007188911A (en) 2006-01-11 2007-07-26 Matsushita Electric Ind Co Ltd Semiconductor device, and method of manufacturing same
US20150054017A1 (en) 2013-08-20 2015-02-26 Prolight Opto Technology Corporation Led chip package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007188911A (en) 2006-01-11 2007-07-26 Matsushita Electric Ind Co Ltd Semiconductor device, and method of manufacturing same
US20150054017A1 (en) 2013-08-20 2015-02-26 Prolight Opto Technology Corporation Led chip package

Also Published As

Publication number Publication date
DE102015212383A1 (en) 2017-01-05

Similar Documents

Publication Publication Date Title
DE102005047856B4 (en) Semiconductor component with semiconductor device components embedded in a plastic housing composition, system carrier for accommodating the semiconductor device components and method for producing the system carrier and semiconductor components
DE102005028951B4 (en) Arrangement for the electrical connection of a semiconductor circuit arrangement with an external contact device
DE10333841B4 (en) A method of producing a benefit having semiconductor device locations arranged in rows and columns and methods of making a semiconductor device
DE10250538B4 (en) Electronic component as multichip module and method for its production
DE102005006333A1 (en) Semiconductor device with multiple bond terminals and method of making the same
DE102011053149B4 (en) The structure, die arrangement, and method of processing a die
DE102009001461A1 (en) Method for producing an electronic assembly
EP3271943B1 (en) Power module and method for producing a power module
DE102006022254A1 (en) Semiconductor device having semiconductor device components embedded in plastic package
DE102006003137A1 (en) Electronic package for mobile telephone, has encapsulating medium e.g. epoxy resin, to connect upper and lower substrates such that substrates engage with one another and encapsulate electronic components
DE112006003861B4 (en) Semiconductor module and method for producing a semiconductor module
DE102008063401A1 (en) Semiconductor device with a cost-efficient chip package, which is connected on the basis of metal acids
DE102020108851A1 (en) THE-TO-CONDUCTOR CONNECTION IN THE ENCAPSULATION OF A CAST SEMI-CONDUCTOR ENCLOSURE
DE102007036841B4 (en) Semiconductor device with semiconductor chip and method for its production
DE102006023998B4 (en) Electronic circuit arrangement and method for producing such
DE10336747A1 (en) Semiconductor component used as a power transistor comprises a layer structure with a semiconductor chip, a support for the chip and an electrically insulating layer made from nano-particles of an electrically insulating material
DE10144704A1 (en) Chip components connecting method, involves producing electrically conductive and flexible microparticles on any of two terminal regions and detachably connecting the regions via microparticles
DE102006017115B4 (en) Semiconductor device with a plastic housing and method for its production
DE102015212383B4 (en) electronic component
DE102012206362B4 (en) Circuit arrangement for thermally conductive chip assembly and manufacturing process
DE102017200504A1 (en) Electronic component and method for producing an electronic component
WO2018065483A1 (en) Power electronics circuit
DE19741436A1 (en) Semiconductor device suitable for wire bond and flip-chip mounting
DE102015211843A1 (en) Electronic component and method for producing an electronic component
DE102020108846B4 (en) CHIP-TO-CHIP CONNECTION IN THE PACKAGE OF A MOLDED SEMICONDUCTOR PACKAGE AND METHOD FOR ITS MANUFACTURE

Legal Events

Date Code Title Description
R163 Identified publications notified
R081 Change of applicant/patentee

Owner name: VITESCO TECHNOLOGIES GERMANY GMBH, DE

Free format text: FORMER OWNER: CONTI TEMIC MICROELECTRONIC GMBH, 90411 NUERNBERG, DE

R081 Change of applicant/patentee

Owner name: VITESCO TECHNOLOGIES GERMANY GMBH, DE

Free format text: FORMER OWNER: VITESCO TECHNOLOGIES GERMANY GMBH, 30165 HANNOVER, DE

R012 Request for examination validly filed
R016 Response to examination communication
R018 Grant decision by examination section/examining division
R020 Patent grant now final