DE102012200329B4 - Halbleiteranordnung mit einem Heatspreader und Verfahren zur Herstellung einer Halbleiteranordnung - Google Patents
Halbleiteranordnung mit einem Heatspreader und Verfahren zur Herstellung einer Halbleiteranordnung Download PDFInfo
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- DE102012200329B4 DE102012200329B4 DE102012200329A DE102012200329A DE102012200329B4 DE 102012200329 B4 DE102012200329 B4 DE 102012200329B4 DE 102012200329 A DE102012200329 A DE 102012200329A DE 102012200329 A DE102012200329 A DE 102012200329A DE 102012200329 B4 DE102012200329 B4 DE 102012200329B4
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- heatspreader
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Abstract
Eine Halbleiteranordnung weist einen Halbleiterchip (106, 136, 216) mit einer Rückseitenmetallisierung (214), einem ersten Substrat (102, 130, 202) und einem elektrisch leitfähigen ersten Heatspreader (212, 300A, 300B, 300C), der die Rückseitenmetallisierung (214) unmittelbar kontaktiert. Der Halbleiterchip (106, 136, 216) weist eine erste Sinterverbindung (126, 210) auf, die den ersten Heatspreader (212, 300A, 300B, 300C) unmittelbar kontaktiert und diesen elektrisch an das erste Substrat (102, 130, 202) koppelt.
Description
- ALLGEMEINER STAND DER TECHNIK
- Leistungselektronikmodule sind Halbleiterbaugruppen, die in Leistungselektronikschaltungen zum Einsatz kommen. Leistungselektronikmodule kommen üblicherweise in Fahrzeug- und Industrieanwendungen zum Einsatz, wie in Invertern und Gleichrichtern. Die Halbleiterkomponenten, die in den Leistungselektronikmodulen enthalten sind, sind üblicherweise IGBT(Insulated Gate Bipolar Transistor)-Halbleiterchips oder MOSFET(Metalloxidhalbleiter-Feldeffekttransistor)-Halbleiterchips. Die IGBT- und MOSFET-Halbleiterchips weisen variierende Nennspannungen und -leistungen auf. Einige Leistungselektronikmodule weisen zum Überspannungsschutz auch zusätzliche Halbleiterdioden (d. h. Freilaufdioden) im Halbleiterpaket auf.
- Im Allgemeinen kommen zwei unterschiedliche Leistungselektronikmodul-Designs zum Einsatz. Ein Design dient für höhere Leistungsanwendungen und das andere Design für niedrigere Leistungsanwendungen. Für höhere Leistungsanwendungen weist ein Leistungselektronikmodul üblicherweise mehrere Halbleiterchips integriert auf einem einzelnen Substrat auf. Das Substrat weist üblicherweise ein isolierendes Keramiksubstrat, wie Al2O3, AlN, Si3N4 oder ein anderes geeignetes Material auf, um das Leistungselektronikmodul elektrisch zu isolieren. Mindestens die Oberseite des Keramiksubstrates ist entweder mit reinem oder plattiertem Cu, Al oder einem anderen geeigneten Material metallbeschichtet, um elektrischer und mechanische Kontakte für die Halbleiterchips bereitzustellen. Die Metallschicht wird üblicherweise mit Hilfe eines direkten Kupfer-Bonding-Verfahrens (DCB), eines direkten Aluminium-Bonding-Verfahrens (DAB) oder eines aktiven Metallhartlötverfahrens (AMB) an das Keramiksubstrat gebondet.
- Üblicherweise kommt Weichlöten mit Sn-Pb, Sn-Ag, Sn-Ag-Cu oder einer anderen geeigneten Lötlegierung zum Anbringen eines Halbleiterchips auf einem metallbeschichteten Keramiksubstrat zum Einsatz. Üblicherweise werden mehrere Substrate auf einer Metallgrundplatte kombiniert. In diesem Fall wird die Rückseite des Keramiksubstrates auch entweder mit reinem oder plattiertem Cu, Al oder einem anderen geeigneten Material zum Anbringen der Substrate auf der Metallgrundplatte metallbeschichtet. Zum Anbringen der Substrate auf der Metallgrundplatte kommt üblicherweise Weichlöten mit Sn-Pb, Sn-Ag, Sn-Ag-Cu oder einer anderen geeigneten Lötlegierung zum Einsatz.
- Für niedrigere Leistungsanwendungen kommen anstelle von Keramiksubstraten üblicherweise Leadframe-Substrate (z. B. reine Cu-Substrate) zum Einsatz. In Abhängigkeit von der Anwendung werden die Leadframe-Substrate üblicherweise mit Ni, Ag, Au und/oder Pd plattiert. Üblicherweise kommt Weichlöten mit Sn-Pb, Sn-Ag, Sn-Ag-Cu oder einer anderen geeigneten Lötlegierung zum Anbringen eines Halbleiterchips auf einem Leadframe-Substrat zum Einsatz.
- Für Hochtemperaturanwendungen wird der niedrige Schmelzpunkt der Lötverbindungen (Tm = 180°C–220°C) zu einem kritischen Parameter für Leistungselektronikmodule. Während des Betriebes von Leistungselektronikmodulen werden die Bereiche unter den Halbleiterchips hohen Temperaturen ausgesetzt. In diesen Bereichen überlagern sich die Umgebungslufttemperatur und die innerhalb des Halbleiterchips dissipierte Wärme. Dies führt zu einer Temperaturwechselbeanspruchung während des Betriebes der Leistungselektronikmodule. Üblicherweise kann in Bezug auf die Temperaturwechselbeanspruchungs-Zuverlässigkeit keine zuverlässige Funktion einer Lötverbindung über 150°C garantiert werden.
- Oberhalb von 150°C können sich innerhalb der Lötregion nach wenigen thermischen Zyklen Risse bilden. Die Risse können sich leicht über die gesamte Lötregion ausbreiten und zum Versagen des Leistungselektronikmoduls führen.
- Mit dem zunehmenden Wunsch der Verwendung von Leistungselektronik in rauen Umgebungen (z. B. Automobilanwendungen) und der fortschreitenden Integration von Halbleiterchips steigt die extern und intern abgeleitete Hitze weiter an. Daher besteht wachsender Bedarf an Hochtemperatur-Leistungselektronikmodulen, die in der Lage sind, bei internen und externen Temperaturen von bis zu 200°C und darüber zu funktionieren. Außerdem steigt die derzeitige Integrationsdichte in der Leistungselektronik weiter an, was zu einem Anstieg in der Dichte der Leistungsverluste führt. Daher gewinnt die thermische Schnittstelle zwischen dem Halbleiterchip und dem Substrat, über welche die Verluste abgeleitet werden müssen, zunehmend an Bedeutung.
- Aus diesen und anderen Gründen besteht Bedarf an der vorliegenden Erfindung.
- Aus der
US 6 812 559 B2 ist eine Anordnung mit einem Kühlkörper bekannt, auf dem ein Leistungsbauelement angeordnet ist. Auf der dem Kühlkörper abgewandte Seite des Leistungsbauelements ist eine thermische Kapazität vorgesehen, die mittels einer druckgesinterten Schicht mit dem Leistungsbauelement verbunden ist. Eine ähnlich Anordnung ist auch in derJP 2006 352 080 A - KURZDARSTELLUNG DER ERFINDUNG
- Eine Halbleiteranordnung weist einen Halbleiterchip einschließlich einer Rückseitenmetallisierung auf, sowie ein Substrat und einen elektrisch leitfähigen Heatspreader, der in direktem Kontakt mit dem Rückseitenmetall steht. Die Halbleiteranordnung weist außerdem eine Sinterverbindung auf, die den Heatspreader direkt kontaktiert und diesen elektrisch an das Substrat koppelt.
- KURZBESCHREIBUNG DER ZEICHNUNGEN
- Die beigefügten Zeichnungen, welche zur Bereitstellung eines breiteren Verständnisses von Ausführungsformen dienen, sind Bestandteil dieser Beschreibung und stellen einen Teil von dieser dar. Die Zeichnungen veranschaulichen Ausführungsformen, und zusammen mit der Beschreibung dienen sie der Erläuterung der Prinzipien von Ausführungsformen. Weitere Ausführungsformen und viele der beabsichtigten Vorteile von Ausführungsformen werden leicht ersichtlich sein, wenn sie durch Verweis auf die nachfolgende detaillierte Beschreibung besser verstanden werden. Die Elemente der Zeichnungen sind relativ zueinander nicht notwendigerweise maßstabsgerecht dargestellt. Gleiche Bezugszeichen bezeichnen entsprechende ähnliche Teile.
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1 veranschaulicht eine Querschnittansicht einer Ausführungsform einer Halbleiterbaugruppe. -
2 veranschaulicht eine Querschnittansicht einer weiteren Ausführungsform einer Halbleiterbaugruppe. -
3 veranschaulicht eine Querschnittansicht einer Ausführungsform eines Abschnittes einer Halbleiteranordnung, welche eine elektrische und thermische Schnittstelle zwischen einem Halbleiterchip und einem Substrat aufweist. -
4 veranschaulicht eine Querschnittansicht einer Ausführungsform eines Abschnittes einer Halbleiteranordnung, welche elektrischer und thermischer Schnittstellen zwischen einem Halbleiterchip und zwei Substraten umfasst. -
5A veranschaulicht eine Querschnittansicht einer Ausführungsform eines Heatspreaders. -
5B veranschaulicht eine Querschnittansicht einer weiteren Ausführungsform eines Heatspreaders. -
5C veranschaulicht eine Querschnittansicht einer weiteren Ausführungsform eines Heatspreaders. - DETAILLIERTE BESCHREIBUNG
- In der folgenden detaillierten Beschreibung wird auf die beigefügten Zeichnungen Bezug genommen, welche einen Teil hiervon bilden, und in welchen mittels Veranschaulichung spezifischer Ausführungsformen gezeigt wird, wie die Offenbarung in der Praxis umgesetzt werden kann. In diesem Zusammenhang wird richtungsabhängige Terminologie, wie „Ober-”, „Unter-”, „Vorder-”, „Rück-”, „Front-”, „End-” usw. mit Bezug auf die Ausrichtung der beschriebenen Figur(en) verwendet. Da Komponenten von Ausführungsformen in einer Reihe unterschiedlicher Ausrichtungen positioniert sein können, wird die richtungsabhängige Terminologie zum Zweck der Veranschaulichung verwendet und ist in keiner Weise einschränkend zu verstehen. Es wird darauf hingewiesen, dass im Rahmen der Erfindung weitere Ausführungsformen verwendet werden können, und dass im Rahmen der Erfindung strukturelle und/oder logische Veränderungen vorgenommen werden können.
- Es wird außerdem darauf hingewiesen, dass die Merkmale der hierin beschriebenen verschiedenen beispielhaften Ausführungsformen miteinander kombiniert werden können, soweit nicht anders angegeben oder soweit eine Kombination solcher Merkmale aus technischen Gründen nicht ausgeschlossen ist.
- Der hierin verwendete Begriff „elektrisch gekoppelt” bedeutet nicht zwingend, dass die Elemente unmittelbar miteinander gekoppelt sein müssen. Vielmehr können „elektrisch gekoppelte” Elemente unmittelbar gekoppelt sein, oder es können zwischen diesen noch zusätzliche, zwischengeschaltete Elemente vorgesehen sein.
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1 veranschaulicht eine Querschnittansicht einer Ausführungsform einer Halbleiteranordnung100 . Bei der Halbleiteranordnung100 kann es sich um ein Hochtemperatur-(d. h. um ein Modul, das für den Betrieb bei Temperaturen von wenigstens 200°C ausgelegt ist) oder um ein Niedrigleistungselektronikmodul handeln. Das Elektronikmodul100 weist ein Leadframe-Substrat102 , eine elektrische und thermische Schnittstelle104 , ein(en) Halbleiterchip oder -plättchen106 , Bonddrähte108 , elektrische Anschlüsse112 und ein Gehäuse110 auf. Das Leadframe-Substrat102 umfasst Cu, Al oder ein anderes geeignetes Material. Optional kann das Leadframe-Substrat102 mit einem oder mehreren von Ni, Ag, Au, Pd plattiert sein. Die elektrische und thermische Schnittstelle104 weist einen Heatspreader und eine gesinterte Verbindung auf, die unten mit Bezugnahme auf die3 bis5C detaillierter beschrieben werden wird. Die elektrische und thermische Schnittstelle104 verbindet das Leadframe-Substrat102 mit dem Halbleiterchip106 . - Die gesinterte Verbindung kann aufgrund des Herstellungsprozesses Fehlstellen oder Störstellen aufweisen. Die Fehlstellen oder Störstellen der gesinterten Verbindung können in einem Größenbereich zwischen wenigen Mikrometern und 20 μm liegen. Diese Fehlstellen oder Störstellen der gesinterten Verbindung verringern die Effektivität der gesinterten Verbindung bei der Ableitung von Hitze aus dem Halbleiterchip
106 . Um die nachteilige Wirkung der Fehlstellen oder Störstellen der gesinterten Verbindung bei der Ableitung von Hitze aus dem Halbleiterchip106 zu verringern ist ein Heatspreader zwischen dem Halbleiterchip106 und der gesinterten Verbindung ausgebildet. Der Heatspreader stellt einen Puffer zwischen dem Halbleiterchip106 und der gesinterten Verbindung zum Ableiten der Hitze aus dem Halbleiterchip106 um die Fehlstellen oder Störstellen der gesinterten Verbindung herum bereit. Durch das Verteilen der abgeleiteten Hitze aus dem Halbleiterchip106 um die Fehlstellen oder Störstellen der gesinterten Verbindung herum wird die thermische Schnittstelle zwischen dem Halbleiterchip106 und dem Leadframe-Substrat102 im Vergleich zu einer thermischen Schnittstelle, die nur die gesinterte Verbindung und keinen Heatspreader aufweist, wesentlich verbessert. - Der Halbleiterchip
106 ist durch die Bonddrähte108 elektrisch an die Anschlüsse112 gekoppelt. Die Bonddrähte108 weisen Al, Cu, Al-Mg, Au oder ein anderes geeignetes Material auf. Die Bonddrähte108 können z. B. mittels Ultraschall-Drahtbonden oder einer anderen Drahtbondtechnik an den Halbleiterchip106 und die Anschlüsse112 gebondet sein. Das Leadframe-Substrat102 kann beispielsweise eine Dicke im Bereich von 125 μm bis 200 μm aufweisen. Das Leadframe-Substrat102 ist mittels eines Niedrigtemperatur-Verbindungsverfahrens (LTJ) über die elektrische und thermische Schnittstelle104 mit dem Halbleiterchip106 verbunden. Das Gehäuse110 weist einen Formwerkstoff oder ein anderes geeignetes Material auf. Das Gehäuse110 umschließt das Leadframe-Substrat102 , die elektrische und thermische Schnittstelle104 , den Halbleiterchip106 , die Bonddrähte108 und Abschnitte der Anschlüsse112 . -
2 veranschaulicht eine Querschnittansicht einer weiteren Ausführungsform einer Halbleiteranordnung120 . Bei der Halbleiteranordnung120 kann es sich um ein Hochtemperatur-(d. h. um ein Modul mit zumindest einem Halbleiterchip, der für den Betrieb bei Temperaturen von wenigstens 200°C ausgelegt ist) Hochleistungselektronikmodul handeln. Das Elektronikmodul120 weist eine metallische Grundplatte124 auf, gesinterte Verbindungen126 , metallisierte Keramiksubstrate130 mit Metallflächen oder -schichten128 und132 , elektrische und thermische Schnittstellen134 , Halbleiterchips136 , Bonddrähte138 , eine Leiterplatte140 , Steueranschlüsse142 , die Leistungsanschlüsse144 , Vergussmassen146 und148 , sowie ein Gehäuse150 . - Die Keramiksubstrate
130 können Al2O3, AlN, Si3N4 oder ein anderes Keramikmaterial aufweisen oder daraus bestehen. Die Keramiksubstrate130 können jeweils eine Dicke im Bereiches von 0,2 mm bis 2,0 mm aufweisen. Die Metallschichten128 und132 können Cu, Al oder ein anderes geeignetes Material aufweisen. Optional können die Metallschichten128 und/oder132 mit einem oder mehreren der Materialien Ni, Ag, Au, Pd plattiert sein. Die Metallschichten128 und132 können jeweils eine Dicke im Bereich von 0,1 mm bis 0,6 mm aufweisen. Die gesinterten Verbindungen126 verbinden die Metallschichten128 mit der Metallgrundplatte124 . Die elektrischen und thermischen Schnittstellen134 verbinden die Metallschichten132 mit den Halbleiterchips136 . Jede elektrische und thermische Schnittstelle134 weist einen Heatspreader und eine gesinterte Verbindung ähnlich der zuvor beschriebenen und unter Bezugnahme auf1 veranschaulichten elektrischen und thermischen Schnittstelle104 auf. - Die Halbleiterchips
136 sind durch die Bonddrähte138 elektrisch an die Metallschichten132 gekoppelt. Die Bonddrähte138 weisen Al, Cu, Al-Mg, Au oder ein anderes geeignetes Material auf. Die Bonddrähte138 können z. B. durch Ultraschall-Drahtbonden oder ein anderes Drahtbondverfahren an die Halbleiterchips136 und die Metallschichten132 gebondet sein. Die Metallschichten132 sind elektrisch an die Leiterplatte140 und die Leistungsanschlüsse144 gekoppelt. Die Leiterplatte140 ist elektrisch an die Steueranschlüsse142 gekoppelt. - Das Gehäuse
150 umschließt die gesinterten Verbindungen126 , die metallbeschichteten Keramiksubstrate130 einschließlich der Metallschichten128 und132 , die elektrischen und thermischen Schnittstellen134 , die Halbleiterchips136 , die Bonddrähte138 , die Leiterplatte140 , Abschnitte der Steueranschlüsse142 und Abschnitte der Leistungsanschlüsse144 . Das Gehäuse150 weist Kunststoff, beispielsweise einen Thermoplast oder Duroplast, oder ein anderes geeignetes Material auf. Das Gehäuse150 ist mit der Metallgrundplatte124 verbunden. Optional kann nur genau ein einziges metallbeschichtetes Keramiksubstrat130 zum Einsatz kommen, und zwar derart, dass keine Metallgrundplatte124 vorhanden ist und das Gehäuse150 direkt mit dem metallbeschichteten Keramiksubstrat130 verbunden ist. - Das Vergussmaterial
146 , beispielsweise eine Weichvergussmasse wie z. B. ein Silikongel, füllt Bereiche unter der Leiterplatte140 innerhalb des Gehäuses150 um die gesinterten Verbindungen126 , die metallbeschichteten Keramiksubstrate130 einschließlich der Metallschichten128 und132 , die elektrischen und thermischen Schnittstellen134 , die Halbleiterchips136 und die Bonddrähte138 herum. Das Vergussmaterial148 , beispielsweise eine Hartvergussmasse wie z. B. ein Isolierharz, füllt den Bereich über der Platine150 innerhalb des Gehäuses150 um Abschnitte der Steueranschlüsse142 und Abschnitte der Leistungsanschlüsse144 herum. Die Vergussmaterialien146 und148 verhindern eine Beschädigung des Leistungselektronikmoduls120 durch einen dielektrischen Durchschlag. -
3 veranschaulicht eine Querschnittansicht eines Abschnittes200 einer Halbleiteranordnung, die eine elektrische und thermische Schnittstelle zwischen einem Halbleiterchip216 und einem Substrat202 aufweist. Der Abschnitt200 kann auf dieselbe Weise verwendet werden, wie die vorangehend unter Bezugnahme auf die in den1 bzw.2 veranschaulichten Module100 oder120 erläutert wurde. Der Abschnitt200 weist ein metallbeschichtetes Keramiksubstrat202 , eine gesinterte Verbindung210 , einen Heatspreader212 , eine Halbleiterchip-Rückseitenmetallisierung214 , einen Halbleiterchip216 , eine Halbleiterchip-Vorderseitenmetallisierung218 , sowie einen Bonddraht220 auf. - Das metallbeschichtete Keramiksubstrat
202 weist ein Keramiksubstrat206 , eine erste Metallschicht204 , die mit einer ersten Seite des Keramiksubstrates206 in direktem Kontakt steht, und eine zweite Metallschicht208 , die mit einer zweiten Seite des Keramiksubstrates206 in direktem Kontakt steht, wobei die erste Seite und die zweite Seite einander abgewandte Seiten des Keramiksubstrates206 bilden. Das Keramiksubstrat206 weist Al2O3, AlN, Si3N4 oder ein anderes geeignetes Material auf oder besteht aus einem der genannten Materialien. Die Metallschichten204 und208 weisen Cu, Al oder ein anderes Material auf. Optional können die Metallschichten204 und/oder208 mit zumindest einem der Metalle Ni, Ag, Au, Pd plattiert sein. Die Metallschichten204 und208 können mittels eines direkten Kupfer-Bonding-Verfahrens (DCB), eines direkten Aluminium-Bonding-Verfahrens (DAB) oder eines aktiven Metallhartlötverfahrens (AMB) an das Keramiksubstrat206 gebondet sein. Alternativ zu einem metallbeschichteten Keramiksubstrat202 kann ein Leadframe-Substrat aus oder mit einem metallischen Leadframe entsprechend dem vorangehend in1 veranschaulichten und erläuterten Leadframe-Substrat102 vorgesehen sein. - Die gesinterte Verbindung
210 koppelt die Metallschicht208 des metallbeschichteten Keramiksubstrates202 elektrisch an den Heatspreader212 . Wenn anstelle des Keramiksubstrates ein Leadframe-Substrat vorgesehen ist, koppelt die gesinterte Verbindung210 das Leadframe-Substrat elektrisch an den Heatspreader212 . Die gesinterte Verbindung210 ist eine gesinterte Metallschicht, die gesinterte Nanopartikel, z. B. aus einem Edelmetall wie beispielsweise Ag-Nanopartikel, Au-Nanopartikel, Cu-Nanopartikel, oder andere geeignete Nanopartikel, oder eine Mischung mit wenigstens zwei der genannten Nanopartikelarten aufweist. Die gesinterte Verbindung210 kann aufgrund des Herstellungsprozesses Fehlstellen oder Störstellen aufweisen. - Der Heatspreader
212 steht in unmittelbarem Kontakt mit der gesinterten Verbindung210 und dem Halbleiterchip-Rückseitenmetall214 und stellt einen Puffer zwischen dem Halbleiterchip216 und der gesinterten Verbindung210 zum Ableiten von Hitze aus dem Halbleiterchip216 um die Fehlstellen oder Störstellen der gesinterten Verbindung210 herum bereit. Der Heatspreader212 kann eine feste ebene Materialschicht aufweisen, welche die gleiche Länge und Breite wie der Halbleiterchip216 besitzt, und zwar derart, dass der Heatspreader212 die gesamte, dem Keramiksubstrat202 bzw. einem Leadframe-Substrat102 zugewandte Rückseite des Halbleiterchips216 bedeckt. Der Heatspreader212 kann eine Materialschicht mit hoher thermischer Leitfähigkeit wie beispielsweise Cu, Ag, Kohlenstoff-Nanoröhrchen oder ein anderes geeignetes Material aufweisen. - Zur Realisierung eines Heatspreaders
212 können Kohlenstoff-Nanoröhrchen, die eine thermische Leitfähigkeit von bis zu 2000 W/(m·K) besitzen, in eine oder mehrere Metallschichten gemischt werden. - In einer Ausführungsform wird während der Waferbearbeitung zur Herstellung des Halbleiterchips eine Materialschicht für den Heatspreader
212 auf dem Halbleiterchip-Rückseitenmetall214 abgelagert oder gezüchtet. Durch das Ablagern oder Züchten der Materialschicht während der Waferbearbeitung kann eine Schicht erreicht werden, welche eine niedrige Defektdichte aufweist. Der Heatspreader212 weist eine Dicke von mindestens 4 μm zwischen dem Halbleiterchip-Rückseitenmetall214 und der gesinterten Verbindung210 auf. In weiteren Ausführungsformen weist der Heatspreader212 eine Dicke zwischen 4 μm und 100 μm, wie 5 μm, 8 μm, 10 μm, 20 μm, 50 μm oder 100 μm, auf. Außerdem kann der Heatspreader212 eine thermische Leitfähigkeit von mindestens 300 W/(m·K) aufweisen. - Das Halbleiterchip-Rückseitenmetall
214 koppelt die Rückseite des Halbleiterchips216 elektrisch und thermisch an den Heatspreader212 . Das Halbleiterchip-Rückseitenmetall214 kann jegliche(n) geeignete(n) Metallschicht oder Stapel an Metallschichten aufweisen. Beispielsweise kann Halbleiterchip-Rückseitenmetall214 einen Cr/Ni/Ag-, Al/X/Y/Ni/Ag- oder Al/X/Y/Ni/Au-Schichtstapel aufweisen, wobei es sich bei „X” und „Y” um beliebige Metalle handeln kann. Die Dicke des Halbleiterchip-Rückseitenmetalls214 kann 1 μm oder weniger betragen. Aufgrund der relativ geringen Dicke von 1 μm oder weniger des Halbleiterchip-Rückseitenmetalls214 trägt das Halbleiterchip-Rückseitenmetall allein nicht signifikant zur Hitzeverteilung bei. - Der Halbleiterchip
216 kann ein Leistungshalbleiterbauelement wie beispielsweise einen Insulated Gate Bipolar Transistor (IGBT), einen Metalloxidhalbleiter-Feldeffekttransistor (MOSFET) und/oder Dioden (z. B. Freilaufdioden) umfassen. Ohne den Heatspreader212 müsste das Halbleitermaterial des Halbleiterchips216 , beispielsweise Si oder SiC, das eine thermische Leitfähigkeit von höchstens einem Drittel der thermischen Leitfähigkeit des Heatspreaders212 aufweist, die Hitze um die Fehlstellen oder Störstellen der gesinterten Verbindung210 herum verteilen. Das Halbleiterchip-Vorderseitenmetall218 koppelt die Vorderseite des Halbleiterchips216 elektrisch an den Bonddraht220 . Das Halbleiterchip-Vorderseitenmetall218 weist Cu, Al oder ein anderes Material auf. In einer Ausführungsform ist das Halbleiterchip-Vorderseitenmetall218 mit einem oder mehreren der Materialien Ni, Ag, Au, Pd plattiert. Der Bonddraht220 weist Al, Cu, Al-Mg, Au oder ein anderes Material auf. -
4 veranschaulicht eine Querschnittansicht einer Ausführungsform eines Abschnittes250 einer Halbleiteranordnung, einschließlich elektrischer und thermischer Schnittstellen zwischen einem Halbleiterchip216 und Substraten202 und256 . Der Abschnitt250 kann beispielsweise in dem zuvor beschriebenen und unter Bezugnahme auf2 veranschaulichten Modul120 verwendet werden. Der Abschnitt250 weist ein erstes metallbeschichtetes Keramiksubstrat202 , eine erste gesinterte Verbindung210 , einen ersten Heatspreader212 , ein Halbleiterchip-Rückseitenmetall214 , einen Halbleiterchip216 , einen zweiten Heatspreader252 , eine zweite gesinterte Verbindung254 und ein zweites metallbeschichtetes Keramiksubstrat256 auf. - Das erste metallbeschichtete Keramiksubstrat
202 , die erste gesinterte Verbindung210 , der erste Heatspreader212 , das Halbleiterchip-Rückseitenmetall214 und der Halbleiterchip216 sind die gleichen wie sie zuvor beschrieben und unter Bezugnahme auf3 veranschaulicht wurden. Das zweite metallbeschichtete Keramiksubstrat256 kann genauso oder ähnlich dem metallbeschichteten Keramiksubstrat202 aufgebaut sein. Es weist ein Keramiksubstrat260 , eine erste Metallschicht258 in direktem Kontakt mit einer ersten Seite des Keramiksubstrates260 und eine zweite Metallschicht262 in direktem Kontakt mit einer zweiten Seite des Keramiksubstrates260 auf, wobei die erste Seite und die zweite Seite einander entgegengesetzte Seiten des Keramiksubstrates260 bilden. - Die zweite gesinterte Verbindung
254 koppelt die Metallschicht258 des zweiten metallbeschichteten Keramiksubstrates256 elektrisch an den zweiten Heatspreader252 . Die gesinterte Verbindung254 kann genauso oder ähnlich der gesinterten Verbindung210 aufgebaut sein. Sie ist durch eine gesinterte Metallschicht gebildet, die gesinterte Nanopartikel wie beispielsweise Edelmetallall-Nanopartikel, z. B. Ag-Nanopartikel, Au-Nanopartikel, Cu-Nanopartikel, oder andere geeignete Nanopartikel umfasst. Die gesinterte Verbindung254 kann aufgrund des Herstellungsverfahrens Fehlstellen oder Störstellen aufweisen. - Der zweite Heatspreader
252 steht in direktem Kontakt mit der gesinterten Verbindung254 und dem Halbleiterchip216 und stellt einen Puffer zwischen dem Halbleiterchip216 und der gesinterten Verbindung254 dar, der zum Ableiten der Hitze aus dem Halbleiterchip216 um die Fehlstellen oder Störstellen der gesinterten Verbindung254 herum dient. In einer Ausführungsform weist der zweite Heatspreader252 eine feste ebene Materialschicht auf, welche eine etwas geringere Länge und/oder Breite als der Halbleiterchip216 aufweist, und zwar derart, dass der zweite Heatspreader252 den Hauptteil der Vorderseite des Halbleiterchips216 bedeckt. In einer Ausführungsform weist der zweite Heatspreader252 eine Materialschicht mit hoher thermische Leitfähigkeit auf, die beispielsweise Cu, Ag, Kohlenstoff-Nanoröhrchen oder ein anderes geeignetes Material enthalten kann. Im Fall von Kohlenstoff-Nanoröhrchen, die eine thermische Leitfähigkeit von bis zu 2000 W/(m·K) aufweisen können, können diese zur Ausbildung des zweiten Heatspreaders252 in Metallschichten gemischt werden. - In einer Ausführungsform wird während der Waferbearbeitung eine Materialschicht für den zweiten Heatspreader
252 auf der Vorderseite des Halbleiterchips216 abgelagert oder gezüchtet. Durch das Ablagern oder Züchten der Materialschicht während der Waferbearbeitung zur Herstellung des Halbleiterchips216 kann eine Schicht mit niedriger Defektdichte erzielt werden. Der zweite Heatspreader252 weist eine Dicke von mindestens 4 μm zwischen der dem ersten Keramiksubstrat202 abgewandten Vorderseite des Halbleiterchips216 und der gesinterten Verbindung254 auf. Der zweite Heatspreader252 kann z. B. eine Dicke von 4 μm bis 100 μm aufweisen, beispielsweise 5 μm, 8 μm, 10 μm, 20 μm, 50 μm oder 100 μm. Die Dicke des zweiten Heatspreaders252 kann derart gewählt sein, dass zwischen dem Halbleiterchip216 und dem zweiten metallbeschichteten Keramiksubstrat256 ein Abstand264 besteht, durch den eine für den Betrieb der Anordnung erforderliche elektrische Isolation eines Randabschlusses des Halbleiterchips216 gegenüber dem zweiten metallbeschichteten Keramiksubstrat256 erreicht wird. Außerdem kann der zweite Heatspreader212 eine Ausführungsform eine thermische Leitfähigkeit von mindestens 300 W/(m·K) aufweisen. -
5A veranschaulicht eine Querschnittansicht eines Heatspreaders300A . Der Heatspreader300A kann anstelle der zuvor beschriebenen und unter Bezugnahme auf die3 und4 veranschaulichten Heatspreader212 und/oder252 verwendet werden. Der Heatspreader300A weist einen Stapel aus einer ersten festen ebenen Metallschicht302 und einer zweiten festen ebenen Metallschicht304 auf. In dieser Ausführungsform ist die erste Metallschicht302 eine Ag-Schicht und die zweite Metallschicht304 ist eine Cu-Schicht zum Bereitstellen eines Cu/Ag-Schichtstapels. Die Dicke der zweiten Metallschicht304 ist größer als die Dicke der ersten Metallschicht302 . Bei Verwendung des Heatspreaders300A in einer Halbleiteranordnung steht die erste Metallschicht302 in direktem Kontakt mit der gesinterten Verbindung, während die zweite Metallschicht304 in direktem Kontakt mit dem Halbleiterchip oder dem Rückseitenmetall des Halbleiterchips steht. -
5B veranschaulicht eine Querschnittansicht einer weiteren Ausführungsform eines Heatspreaders300B . Der Heatspreader300B kann anstelle der zuvor beschriebenen und unter Bezugnahme auf die3 und4 veranschaulichten Heatspreader212 und/oder252 verwendet werden. Der Heatspreader300B weist einen Stapel aus einer ersten festen ebenen Metallschicht310 , einer zweiten festen ebenen Metallschicht312 und einer dritten festen ebenen Metallschicht314 auf. In dieser Ausführungsform handelt es sich bei der ersten Metallschicht310 um eine Ag-Schicht, bei der zweiten Metallschicht312 um eine Cu-Schicht und bei der dritten Metallschicht314 um eine Ni-Schicht zum Bereitstellen eines Ni/Cu/Ag-Schichtstapels. - Die Dicke der zweiten Metallschicht
312 ist größer als die Dicke der ersten Metallschicht310 und die Dicke der dritten Metallschicht314 . In einer Ausführungsform ist die Dicke der zweiten Metallschicht312 größer als die Dicken der ersten Metallschicht310 und der dritten Metallschicht314 zusammen. Bei Verwendung des Heatspreaders300B in einer Halbleiteranordnung steht die erste Metallschicht310 in direktem Kontakt mit der gesinterten Verbindung, während die dritte Metallschicht314 in direktem Kontakt mit dem Halbleiterchip oder dem Rückseitenmetall des Halbleiterchips steht. -
5C veranschaulicht eine Querschnittansicht einer weiteren Ausführungsform eines Heatspreaders300C . Der Heatspreader300C kann anstelle der zuvor beschriebenen und unter Bezugnahme auf die3 und4 veranschaulichten Heatspreader212 und/oder252 verwendet werden. Der Heatspreader300C weist einen Stapel aus einer ersten festen ebenen Metallschicht320 , einer zweiten festen ebenen Metallschicht322 , einer dritten festen ebenen Metallschicht324 und einer vierten festen ebenen Metallschicht326 auf. In dieser Ausführungsform ist die erste Metallschicht320 eine Au-Schicht, die zweite Metallschicht322 ist eine Ni-Schicht, die dritte Metallschicht324 ist eine Cu-Schicht und die vierte Metallschicht326 ist eine Ni-Schicht zum Bereitstellen eines Ni/Cu/Ni/Au-Schichtstapels. - Die Dicke der dritten Metallschicht
324 ist größer als die Dicke der ersten Metallschicht320 , die Dicke der zweiten Metallschicht322 und die Dicke der vierten Metallschicht326 . In einer Ausführungsform ist die Dicke der dritten Metallschicht324 größer als die Dicken der ersten Metallschicht320 , der zweiten Metallschicht322 und der vierten Metallschicht326 zusammen. Bei Verwendung des Heatspreaders300C in einer Halbleiteranordnung steht die erste Metallschicht320 in direktem Kontakt mit der gesinterten Verbindung, während die vierte Metallschicht326 in direktem Kontakt mit dem Halbleiterchip oder dem Rückseitenmetall des Halbleiterchips steht. - Die Ausführungsformen sehen ein Halbleiterbauelement vor, bei welchem während der Waferbearbeitung eine relativ dicke Leiterschicht als ein Puffer erzeugt wird, die sich nach der Montage des Halbleiterchips auf einem Substrat durch Sintern zwischen dem Halbleiterchip und der Sinterverbindung befindet. Die Leiterschicht verteilt die in dem Halbleiterchip dissipierte Wärme um jegliche Fehlstellen oder Störstellen der gesinterten Verbindung herum, wodurch die thermische Schnittstelle zwischen dem Halbleiterchip und dem/den Substrat(en), an dem/denen der Halbleiterchip befestigt ist, verbessert wird.
Claims (20)
- Halbleiteranordnung mit: einem Halbleiterchip (
106 ,136 ,216 ), welcher eine Rückseitenmetallisierung (214 ) aufweist; einem ersten Substrat (102 ,130 ,202 ); einem elektrisch leitenden ersten Heatspreader (212 ,300A ,300B ,300C ), der die Rückseitenmetallisierung (214 ) unmittelbar kontakiert; und einer ersten Sinterverbindung (126 ,210 ), die den ersten Heatspreader (212 ,300A ,300B ,300C ) unmittelbar kontaktiert und die den ersten Heatspreader (212 ,300A ,300B ,300C ) elektrisch an das erste Substrat (102 ,130 ,202 ) koppelt. - Halbleiteranordnung nach Anspruch 1, bei der der erste Heatspreader (
212 ,300A ,300B ,300C ) entweder eine feste ebene Cu-Schicht oder eine feste ebene Ag-Schicht aufweist. - Halbleiteranordnung nach Anspruch 1 oder 2, bei der der erste Heatspreader (
212 ,300A ,300B ,300C ) eine Dicke von mehr als 4 μm aufweist. - Halbleiteranordnung nach einem der vorangehenden Ansprüche, bei der der erste Heatspreader (
212 ,300A ,300B ,300C ) eine thermische Leitfähigkeit von wenigstens 300 W/(m·K) aufweist. - Halbleiteranordnung nach einem der vorangehenden Ansprüche, bei der der erste Heatspreader (
212 ,300A ,300B ,300C ) Kohlenstoff-Nanoröhrchen aufweist. - Halbleiteranordnung nach einem der Ansprüche 1 bis 4, bei der der erste Heatspreader (
212 ,300A ,300B ,300C ) aus einem Cu/Ag-Schichtstapel besteht, und wobei die Ag-Schicht die erste Sinterverbindung (126 ,210 ) unmittelbar kontaktiert. - Halbleiteranordnung nach einem der Ansprüche 1 bis 4, bei der der erste Heatspreader (
212 ,300A ,300B ,300C ) aus einem Ni/Cu/Ag-Schichtstapel besteht, und wobei die Ag-Schicht die erste Sinterverbindung (126 ,210 ) unmittelbar kontaktiert, und wobei die Cu-Schicht eine Dicke aufweist, die größer ist als eine jede der Dickender Ni-Schicht und der Ag-Schicht. - Halbleiteranordnung nach einem der Ansprüche 1 bis 4, bei der der erste Heatspreader (
212 ,300A ,300B ,300C ) aus einem Ni/Cu/Ni/Au-Schichtstapel besteht und wobei die Au-Schicht die erste Sinterverbindung (126 ,210 ) unmittelbar kontaktiert, und wobei die Cu-Schicht eine Dicke aufweist, die größer ist als eine jede der Dicken der Ni-Schichten und der Au-Schicht. - Halbleiteranordnung nach einem der vorangehenden Ansprüche, bei der das erste Substrat (
130 ,202 ) als metallbeschichtetes Keramiksubstrat ausgebildet ist. - Halbleiteranordnung nach einem der Ansprüche 1 bis 9, bei der das erste Substrat (
102 ) als Leadframe ausgebildet ist. - Halbleiteranordnung nach einem der vorangehenden Ansprüche mit: einem zweiten Heatspreader (
252 ,300A ,300B ,300C ), der eine Vorderseite des Halbleiterchips (103 ,136 ,216 ) unmittelbar kontaktiert und mit dieser elektrisch gekoppelt ist; einem zweiten Substrat (256 ); und einer zweiten Sinterverbindung (254 ), die den zweiten Heatspreader (252 ,300A ,300B ,300C ) unmittelbar kontaktiert und die den zweiten Heatspreader (252 ,300A ,300B ,300C ) elektrisch an das zweite Substrat (256 ) koppelt. - Halbleiteranordnung nach Anspruch 11, bei der der zweite Heatspreader (
252 ,300A ,300B ,300C ) entweder Cu oder Ag aufweist. - Halbleiteranordnung nach Anspruch 11 oder 12, bei der der zweite Heatspreader (
252 ,300A ,300B ,300C ) Kohlenstoff-Nanoröhrchen aufweist. - Halbleiteranordnung nach einem der Ansprüche 11 bis 13, bei der das zweite Substrat (
256 ) als metallbeschichtetes Keramiksubstrat ausgebildet ist. - Halbleiteranordnung nach einem der vorangehenden Ansprüche, bei der der Halbleiterchip (
106 ,136 ,216 ) als Leistungshalbleiterchip ausgebildet ist. - Verfahren zur Herstellung einer Halbleiteranordnung, wobei das Verfahren Folgendes umfasst: Bereitstellen eines Halbleiterchips (
106 ,136 ,216 ), welcher eine Rückseitenmetallisierung (214 ) aufweist; Bilden eines ersten Heatspreaders (212 ,300A ,300B ,300C ), der die Rückseitenmetallisierung (214 ) unmittelbar kontaktiert; und elektrisches Koppeln des ersten Heatspreaders (212 ,300A ,300B ,300C ) mit einem ersten Substrat (102 ,130 ,202 ) mittels eines Sinterverfahrens, bei dem eine erste Sinterverbindung (126 ,210 ) erzeugt wird, die den ersten Heatspreader (212 ,300A ,300B ,300C ) und das erste Substrat (102 ,130 ,202 ) unmittelbar kontaktiert. - Verfahren nach Anspruch 16 umfassen die Schritte: Bilden eines zweiten Heatspreaders (
252 ,300A ,300B ,300C ) an einer Vorderseite des Halbleiterchips (106 ,136 ,216 ); und elektrisches Koppeln des zweiten Heatspreaders (252 ,300A ,300B ,300C ) an ein zweites Substrat (256 ) mittels eines Sinterverfahrens, bei dem eine zweite Sinterverbindung (254 ) erzeugt wird, die den zweiten Heatspreader (252 ,300A ,300B ,300C ) und das zweite Substrat (256 ) unmittelbar kontaktiert. - Verfahren nach einem der Ansprüche 16 oder 17, bei dem das Bilden des ersten Heatspreaders (
212 ,300A ,300B ,300C ) das Bilden eines Cu/Ag-Schichtstapels umfasst. - Verfahren nach einem der Ansprüche 16 oder 17, bei dem das Bilden des ersten Heatspreaders (
212 ,300A ,300B ,300C ) das Bilden eines Ni/Cu/Ag-Schichtstapels umfasst. - Verfahren nach einem der Ansprüche 16 oder 17, bei dem das Bilden des ersten Heatspreaders (
212 ,300A ,300B ,300C ) das Bilden eines Ni/Cu/Ni/Au-Schichtstapels umfasst.
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US6812559B2 (en) * | 2000-12-13 | 2004-11-02 | Daimlerchrysler Ag | Power module with improved transient thermal impedance |
JP2006352080A (ja) * | 2005-05-16 | 2006-12-28 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法および半導体装置 |
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ATE5115T1 (de) * | 1980-04-17 | 1983-11-15 | The Post Office | Gold-metallisierung in halbleiteranordnungen. |
JPH0494576A (ja) * | 1990-08-11 | 1992-03-26 | Sharp Corp | 縦型パワーmos fet |
JPH04209576A (ja) * | 1990-12-07 | 1992-07-30 | Kanegafuchi Chem Ind Co Ltd | 光電変換素子 |
US5561321A (en) * | 1992-07-03 | 1996-10-01 | Noritake Co., Ltd. | Ceramic-metal composite structure and process of producing same |
JP3092603B2 (ja) * | 1998-11-02 | 2000-09-25 | 日本電気株式会社 | 半導体素子実装基板又は放熱板とその製造方法及び該基板又は放熱板と半導体素子との接合体 |
US6507104B2 (en) * | 2000-09-07 | 2003-01-14 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with embedded heat-dissipating device |
US6787435B2 (en) * | 2001-07-05 | 2004-09-07 | Gelcore Llc | GaN LED with solderable backside metal |
FR2831714B1 (fr) * | 2001-10-30 | 2004-06-18 | Dgtec | Assemblage de cellules photovoltaiques |
US7745927B2 (en) * | 2004-06-29 | 2010-06-29 | Agere Systems Inc. | Heat sink formed of multiple metal layers on backside of integrated circuit die |
CN100481346C (zh) * | 2004-08-09 | 2009-04-22 | 中国科学院微电子研究所 | 适用于氮化镓器件的铝/钛/铝/镍/金欧姆接触*** |
JP4688647B2 (ja) * | 2005-11-21 | 2011-05-25 | パナソニック株式会社 | 半導体装置とその製造方法 |
US20080026555A1 (en) * | 2006-07-26 | 2008-01-31 | Dubin Valery M | Sacrificial tapered trench opening for damascene interconnects |
US7947331B2 (en) * | 2008-04-28 | 2011-05-24 | Tsinghua University | Method for making thermal interface material |
KR101497412B1 (ko) * | 2008-07-16 | 2015-03-02 | 주식회사 뉴파워 프라즈마 | 공유 결합 탄소나노튜브를 갖는 복합 소재로 구성된 히트싱크 |
CN201293295Y (zh) * | 2008-11-14 | 2009-08-19 | 青岛海信电器股份有限公司 | 散热结构 |
US8304884B2 (en) * | 2009-03-11 | 2012-11-06 | Infineon Technologies Ag | Semiconductor device including spacer element |
-
2011
- 2011-01-12 US US13/005,279 patent/US20120175755A1/en not_active Abandoned
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2012
- 2012-01-11 DE DE102012200329A patent/DE102012200329B4/de active Active
- 2012-01-12 CN CN201210008411.6A patent/CN102593081B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US6812559B2 (en) * | 2000-12-13 | 2004-11-02 | Daimlerchrysler Ag | Power module with improved transient thermal impedance |
JP2006352080A (ja) * | 2005-05-16 | 2006-12-28 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法および半導体装置 |
Also Published As
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CN102593081A (zh) | 2012-07-18 |
DE102012200329A1 (de) | 2012-07-12 |
US20120175755A1 (en) | 2012-07-12 |
CN102593081B (zh) | 2016-01-20 |
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