DE102012112328A1 - Packaging integrated circuit by fabricating package module from successive build-up layers having circuit interconnections, and forming cavity on top-side of package module - Google Patents
Packaging integrated circuit by fabricating package module from successive build-up layers having circuit interconnections, and forming cavity on top-side of package module Download PDFInfo
- Publication number
- DE102012112328A1 DE102012112328A1 DE201210112328 DE102012112328A DE102012112328A1 DE 102012112328 A1 DE102012112328 A1 DE 102012112328A1 DE 201210112328 DE201210112328 DE 201210112328 DE 102012112328 A DE102012112328 A DE 102012112328A DE 102012112328 A1 DE102012112328 A1 DE 102012112328A1
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- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L2924/013—Alloys
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
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- H—ELECTRICITY
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
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- H01L2924/1515—Shape
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
- H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
- H01L2924/15156—Side view
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15333—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a land array, e.g. LGA
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
Description
Querverweis zu verwandten AnmeldungenCross reference to related applications
Die vorliegende Anmeldung ist eine Teilfortsetzungsanmeldung der am 9. Mai 2011 eingereichten jetzt anhängigen U.S.-Anmeldung, Serien Nummer 13/103,124, deren Gesamtheit durch Bezugnahme hierin einbezogen ist.The present application is a continuation-in-part of U.S. Pending Application Serial No. 13 / 103,124, filed May 9, 2011, the entirety of which is incorporated herein by reference.
Technisches GebietTechnical area
Diese Offenbarung betrifft eine Vorrichtung und Verfahren zum Herstellen von Schaltkreisen und, insbesondere, eine Vorrichtung und Verfahren zum Häusen von integrierten Schaltkreisen.This disclosure relates to an apparatus and method for manufacturing circuits and, more particularly, to an apparatus and method for packaging integrated circuits.
Hintergrundbackground
Integrierter-Schaltkreis-(IC)-Chips werden üblicherweise in ein Gehäuse (engl. package) eingebettet. Solch ein Häusen (engl. packaging) stellt beispielweise einen physischen Schutz und Umgebungsschutz bereit, und auch Wärmedissipation. Darüber hinaus stellen gehäuste Chips (engl. packaged chips) üblicherweise elektrische Verbindungen bereit, um eine Integration mit weiteren Komponenten zu ermöglichen.Integrated circuit (IC) chips are usually embedded in a package. Such a packaging, for example, provides physical protection and environmental protection, as well as heat dissipation. In addition, packaged chips typically provide electrical connections to allow integration with other components.
Verschiedene Häusungstechniken für einen integrierten Schaltkreis (IC) sind entwickelt worden. Eine solche Technik ist beispielsweise in: Lee et al., ”Embedded Actives and Discrete Passives in a Cavity Within Build-up Layers („In eine Aussparung innerhalb aufgebauter Schichten eingebettete Aktive und diskrete Passive”),” U.S. Patentanmeldung Seriennummer 11/494,259 eingereicht am 27. Juli 2006 und publiziert als
Im Gegensatz zu einem Chip-zuerst-Prozess oder Chip-Mitte-Prozess bettet ein Chip-zuletzt-Ansatz einen gegebenen Chip ein, nachdem alle Aufbauschichtprozesse beendet wurden. Die Vorteile von diesem Ansatz sind heutzutage wohlbekannt, jedoch ist das Chip-zuletzt-Häusen nicht dazu gedacht, für alle Chiptypen geeignet zu sein. Beispielsweise für ICs (integrierte Schaltkreise), welche einen Rückseitenkontakt aufweisen, und für jene Chips, deren Betriebsparameter eine Dissipation von größeren Wärmemengen benötigen, wie beispielsweise Leistungschips und Hochleistungslogikchips.In contrast to a chip-first process or chip-center process, a chip-last approach embeds a given chip after all build-up layer processes have been completed. The benefits of this approach are well known today, however, last-chip packaging is not intended to be suitable for all chip types. For example, for ICs (integrated circuits) having backside contact, and for those chips whose operating parameters require dissipation of larger amounts of heat, such as power chips and high performance logic chips.
Überblickoverview
In einer Implementierung, um ein Gehäusemodul bereitzustellen, welches für einen großen Bereich von Chiptypen geeignet ist, beinhaltend Leistungschips, Chips, welche einen Rückseitenkontakt aufweisen, und Hochleistungslogikchips, beinhaltet ein Verfahren zum Häusen eines integrierten Schaltkreises das Herstellen eines Gehäusemoduls aus sukzessiv aufgebauten Schichten, welche Schaltkreisverbindungen definieren, das Bilden einer Aussparung auf einer Oberseite des Gehäuse-Moduls, das Befestigen einer metallisierten Rückseite eines Chips auf einer metallischen Schicht, wobei der Chip eine Vorderseite mit mindestens einem vorderen Kontakt aufweist, das Anordnen des Chips in der Aussparung, so dass die Menge an vorderen Kontakten zu einer oder mehreren der Schaltkreisverbindungen des Gehäusemoduls elektrisch verbunden ist, und das Verbinden der metallischen Schicht, die an dem Chip befestigt ist, an das Gehäusemodul.In one implementation to provide a package module suitable for a wide range of chip types, including power chips, back-contact chips, and high-performance logic chips, a method of packaging an integrated circuit includes fabricating a package module from successively constructed layers Defining circuit connections, forming a recess on an upper surface of the package module, attaching a metallized back side of a chip to a metal layer, the chip having a front side with at least one front contact, arranging the chip in the recess such that the chip Amount of front contacts to one or more of the circuit connections of the housing module is electrically connected, and connecting the metallic layer, which is fixed to the chip, to the housing module.
In ähnlicher Weise, in einer anderen Implementierung, weist ein Integrierter-Schaltkreis-Gehäuse ein Gehäusemodul mit einer darin gebildeten Aussparung auf. Das Gehäusemodul kann als ein Schichtmaterial aus aufeinanderfolgend aufgebauten Schichten gebildet sein, welche eine Oberseite, eine Unterseite und dazwischen Schaltkreisverbindungen definieren. Einem Chip-zuletzt-Ansatz folgend, kann die Aussparung auf der Oberseite des Gehäusemoduls gebildet sein. Typischerweise legt das Bilden der Aussparung eine oder mehrere der Schaltkreisverbindungen frei, beispielsweise auf dem Boden der Aussparung. Ein Chip weist eine Vorderseite mit einer Menge an vorderen Kontakten und eine metallisierte Rückseite auf, welche an einer metallischen Schicht befestigt ist, so dass die metallische Schicht mindestens einen Teil der Rückseite des Chips bedeckt, und die Oberseite des Gehäusemoduls kann in der Aussparung angeordnet sein, so dass die Menge der vorderen Kontakte mit einer oder mehreren der Schaltkreisverbindungen des Gehäusemoduls elektrisch verbunden ist. Der Chip ist in der Aussparung derart angeordnet, dass die Menge der vorderen Kontakte mit einer oder mehreren der Schaltkreisverbindungen des Gehäusemoduls elektrisch verbunden ist und die metallische Schicht mindestens einen Teil der Oberseite des Gehäusemoduls bedeckt.Similarly, in another implementation, an integrated circuit package includes a package module having a recess formed therein. The package module may be formed as a layer material of sequentially structured layers defining a top side, a bottom side, and circuit interconnections therebetween. Following a chip-last approach, the recess may be formed on top of the housing module. Typically, the formation of the recess exposes one or more of the circuit connections, for example, to the bottom of the recess. A chip has a front surface with a set of front contacts and a metallized back surface attached to a metal layer such that the metal layer covers at least a portion of the back surface of the chip, and the top surface of the housing module may be disposed in the recess such that the amount of front contacts is electrically connected to one or more of the circuit connections of the housing module. The chip is disposed in the recess such that the set of front contacts is electrically connected to one or more of the circuit connections of the housing module and the metallic layer covers at least a portion of the top of the housing module.
Eines oder mehrere der folgenden Merkmale kann in den obigen Implementierungen enthalten sein oder kombiniert werden. Das Befestigen der metallisierten Rückseite des Chips auf der metallischen Schicht kann mit einem Hochtemperaturprozess durchgeführt werden. Das Befestigen der metallisierten Rückseite des Chips auf der metallischen Schicht kann mit einem Diffusionslötprozess durchgeführt werden. Die metallische Schicht kann eine Metallfolienschicht sein. Die Rückseite des Chips kann ein niederohmiger Kontakt sein. Senkrecht zwischen dem niederohmigen Kontakt und der Menge der vorderen Kontakte des Chips kann Strom fließen. Der Chip kann ein Leistungselektronikchip sein. Der niederohmige Kontakt kann elektrisch zu einer oder mehreren in dem Gehäusemodul gebildeten Durchkontaktierungen verbunden sein, beispielsweise durch eine elektrische Verbindung mit der metallischen Schicht. Der Chip kann ein Hochleistungslogikchip sein. Die metallische Schicht kann thermisch leitfähige Eigenschaften aufweisen, die ein Wärmeverteilen ermöglichen. Die metallische Schicht kann an einer Wärmesenke befestigt sein. Der Chip kann Silizium-Durchkontaktierungen aufweisen. Alles oder ein Teil der metallischen Schicht kann mittels einer isolierenden Mittelschicht mit der Rückseite des Chips und der Oberseite des Gehäusemoduls verbunden sein. Der Chip kann in einer umgedreht-montiert-Konfiguration befestigt sein. Eine umgedreht-montiert-Konfiguration ist es, wenn die metallisierte Rückseite des Chips in Richtung der Leiterplatte (PCB) zeigt und die Vorderseite des Chips von der Leiterplatte weg zeigt.One or more of the following features may be included or combined in the above implementations. The attachment of the metallized backside of the chip to the metallic layer can be done with a high temperature process. The attachment of the metallized backside of the chip to the metallic layer may be accomplished by a diffusion soldering process. The metallic layer may be a metal foil layer. The back of the chip may be a low resistance contact. Vertical between the low-resistance contact and the amount of the front contacts of the chip can be electricity flow. The chip can be a power electronics chip. The low-resistance contact may be electrically connected to one or more plated-through holes formed in the housing module, for example by an electrical connection to the metallic layer. The chip can be a high performance logic chip. The metallic layer may have thermally conductive properties that allow heat dissipation. The metallic layer may be attached to a heat sink. The chip may have silicon vias. All or part of the metallic layer may be connected to the back side of the chip and the top side of the package module by means of an insulating middle layer. The chip may be mounted in an upside-down configuration. An upside-down configuration is when the metallized backside of the chip points toward the printed circuit board (PCB) and points the front of the chip away from the circuit board.
Kurzbeschreibung der FigurenBrief description of the figures
Um die obigen und andere Vorteile und Merkmale der vorliegenden Erfindung weiter klarzustellen, wird eine spezifischere Beschreibung der Erfindung erbracht mittels Bezug auf deren spezifische Ausführungsformen, die in den beigefügten Figuren veranschaulicht sind. Es wird darauf Wert gelegt, dass diese Figuren nur typische Ausführungsformen der Erfindung darstellen und daher nicht als deren Umfang beschränkend betrachtet werden sollen. Die Erfindung wird mit zusätzlicher Genauigkeit und mit zusätzlichem Detail unter Verwendung der beiliegenden Figuren beschrieben und erläutert, in denen:To further clarify the above and other advantages and features of the present invention, a more specific description of the invention will be provided by reference to the specific embodiments thereof illustrated in the accompanying drawings. It is to be understood that these figures represent only typical embodiments of the invention and therefore should not be taken as limiting the scope thereof. The invention will be described and explained with additional accuracy and with additional detail using the accompanying drawings, in which:
Ausführliche BeschreibungDetailed description
Im Folgenden wird Bezug auf die Figuren genommen, wobei gleiche Strukturen mit den gleichen Bezugszeichen versehen werden. Es versteht sich, dass die Zeichnungen diagrammatische und schematische Darstellungen exemplarischer Ausführungsformen der Erfindung sind und keine Einschränkung der vorliegenden Erfindung sind, noch sind diese notwendigerweise maßstabsgetreu gezeichnet.In the following, reference is made to the figures, wherein like structures are provided with the same reference numerals. It should be understood that the drawings are diagrammatic and schematic representations of exemplary embodiments of the invention and are not limitative of the present invention, nor are they necessarily drawn to scale.
In
Die Durchkontaktierungen
Lötkugeln
In
In
Andere Konfigurationen können den Chip
In einer Implementierung, bei der die oberste Schicht
Im Gebrauch kann das IC-Gehäuse
Zusätzlich zu der Bereitstellung eines Zugangs zu einer elektrischen Rückseitenverbindung in dem IC-Gehäuse
Wenn Wärme, die während des Betriebs des Chips
Obwohl einige Chips, wie beispielsweise Hochleistungslogikchips, keinen niederohmigen Rückseitenkontakt
Falls die oberste Schicht
Verunreinigtes Plasma ist bekannt als ein Plasma mit Unterstützungsgas, welches Metallpulver in Partikelgröße darin aufgelöst hat. Dieses Verfahren ist besonders vorteilhaft im Bilden einer Schicht mit ausreichender Materialdicke und minimalem zusätzlichen Prozessieren, um die oberste Schicht
Falls die oberste Schicht
In anderen Konfigurationen, bei denen die oberste Schicht
Durchkontaktierungen
Um beispielsweise die elektrische Last in Hochleistungschips auszugleichen, können mehrere Durchkontaktierungen
Wie oben erwähnt, kann die oberste Schicht
In dem Fall, dass
In dem Fall, dass
Andere Wärme-Senk-Verfahren können ebenfalls für die Wärmesenke und/oder die Metallfolienschicht
In
Die Struktur, die mittels der Fotostrukturoberfläche
Die Befestigung des Chips
Die Fotostrukturoberfläche
In
Gehäuseverbinder
Gemäß den obigen Ausführungsformen, zeigt
Gemäß den obigen Ausführungsformen, zeigt
Der Fachmann wird erkennen, dass Kombinationen der obigen exemplarischen Ausführungsformen gebildet werden können. Beispielsweise kann jedes der Integrierter-Schaltkreis-Gehäuse
Die vorliegende Erfindung kann in anderen spezifischen Formen ausgeführt werden, ohne von dessen Idee oder essenziellen Charakteristiken abzuweichen. Die beschriebenen Ausführungsformen sind in allen Angelegenheiten nur als Anschauung zu betrachten, nicht als beschränkend. Der Schutzbereich der Erfindung ist demnach mittels der beigefügten Ansprüche aufgezeigt, eher als mittels der vorangegangenen Beschreibung. Alle Änderungen, die in die Bedeutung und in die Reichweite der Äquivalenz der Ansprüche führen, sind in deren Schutzbereich einzubeziehen.The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The described embodiments are to be considered as illustrative in all matters, not as limiting. The scope of the invention is, therefore, indicated by the appended claims, rather than by the foregoing description. Any changes that result in the meaning and scope of the equivalence of the claims are to be included in their scope.
ZITATE ENTHALTEN IN DER BESCHREIBUNG QUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- US 2007/0025092 A1 [0004] US 2007/0025092 A1 [0004]
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US13/326,527 | 2011-12-15 | ||
US13/326,527 US9105562B2 (en) | 2011-05-09 | 2011-12-15 | Integrated circuit package and packaging methods |
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DE201210112328 Withdrawn DE102012112328A1 (en) | 2011-12-15 | 2012-12-14 | Packaging integrated circuit by fabricating package module from successive build-up layers having circuit interconnections, and forming cavity on top-side of package module |
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DE (1) | DE102012112328A1 (en) |
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US9601461B2 (en) * | 2015-08-12 | 2017-03-21 | Semtech Corporation | Semiconductor device and method of forming inverted pyramid cavity semiconductor package |
Citations (1)
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US20070025092A1 (en) | 2005-08-01 | 2007-02-01 | Baik-Woo Lee | Embedded actives and discrete passives in a cavity within build-up layers |
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JP3210835B2 (en) * | 1995-06-07 | 2001-09-25 | 京セラ株式会社 | Package for storing semiconductor elements |
JP2004087700A (en) * | 2002-08-26 | 2004-03-18 | Nec Semiconductors Kyushu Ltd | Semiconductor device and its manufacturing method |
US8541876B2 (en) * | 2005-09-30 | 2013-09-24 | Intel Corporation | Microelectronic package having direct contact heat spreader and method of manufacturing same |
DE102005049687B4 (en) * | 2005-10-14 | 2008-09-25 | Infineon Technologies Ag | Power semiconductor component in flat conductor technology with vertical current path and method for the production |
WO2008056499A1 (en) * | 2006-11-06 | 2008-05-15 | Nec Corporation | Semiconductor device and method for manufacturing same |
US20080186690A1 (en) * | 2007-02-07 | 2008-08-07 | Nokia Corporation | Electronics Package And Manufacturing Method Thereof |
CN101916755B (en) * | 2010-09-03 | 2012-08-22 | 四川太晶微电子有限公司 | Plane rectifier |
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