CN87107362A - 至少包括一个双极平面型晶体管的单块集成电路的制造方法 - Google Patents
至少包括一个双极平面型晶体管的单块集成电路的制造方法 Download PDFInfo
- Publication number
- CN87107362A CN87107362A CN87107362.5A CN87107362A CN87107362A CN 87107362 A CN87107362 A CN 87107362A CN 87107362 A CN87107362 A CN 87107362A CN 87107362 A CN87107362 A CN 87107362A
- Authority
- CN
- China
- Prior art keywords
- layer
- base
- emitter
- collector
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title description 5
- 230000003647 oxidation Effects 0.000 claims abstract description 38
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 38
- 230000000873 masking effect Effects 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 25
- 239000012535 impurity Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 18
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- AHKZTVQIVOEVFO-UHFFFAOYSA-N oxide(2-) Chemical group [O-2] AHKZTVQIVOEVFO-UHFFFAOYSA-N 0.000 claims 2
- 230000005669 field effect Effects 0.000 description 12
- 239000000758 substrate Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000000203 mixture Substances 0.000 description 3
- 206010010144 Completed suicide Diseases 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
在本发明方法中发射极区(6)和集电极区分别被氧化掩蔽层部分(71、72)以一般的方式覆盖。在注入基区导电类型离子之后,用热氧化法在(6)周围形成氧化条(21)。在去除(71、72)之后,淀积至少由一个顶层(10)和下面的掺杂层(9)组成的顺序层(9、10)。采用一种被掩蔽的各向异性刻蚀工序并通过(21),(9、10)被分成发射极(61)和集电极(32),在上述电极的外部,扩散发射区(4)与集电极接触区(31)。
Description
本发明涉及一种适用于制造微波单块集成电路的方法,每一块这样的集成电路至少包括一个集成的双极平面型晶体管,即还可以进一步包括象绝缘栅场效应晶体管、集成电容或集成电阻这样的集成元件。但是为了更好地理解本发明和使说明书简要,本发明的方法和先有技术的讨论将只涉及制造至少包括一个双极平面型晶体管的单块集成电路的方法。对此,这并不应认为是一种限制,作出这种简化是由于长期以来已有这样一种惯例,这就是在公共的半导体晶片上制造很多单块集成电路,然后把该晶片分割成各个的电路芯片,最后各自封装。
这类方法在公开的申请DE-A3243059和DE-A3129539中已有描述。在那里,用掺杂多晶硅层形成带有它的基极的基极接触区和带有它的发射极的发射区,而基极接触区和发射区以自对准的结构彼此靠得很近,采用这种方法,可获得极低的基极引线电阻和相当高的工作速度。此外,这种自对准工序还具有在光刻工序中使间距可减少到最低程度的优点,这样便能减小双极平面型晶体管的横向尺寸。
上述在DE-A3129539中公开的方法,其缺点在于要用到复杂的外延工序,这便使得产量低。上述在DE-A3243059中公开的方法,其缺点在于,在发射极和基极之间的覆盖电容限制了工作速度。
本发明从EP-A-71665中公开的方法出发,它基本克服了以上缺点,并采纳了DE-A3129539中的思想,为了减少引线电阻,用表面硅化物层提供多晶硅电极的体电阻,该电极成为互连通路。这也就导致了单块集成电路工作速度的提高。
然而,上述德国公开的申请不涉及集成电极的形成,在EP-A-71665中公开的方法的一个实施例中,用自对准技术形成集电极接触区、发射区和基极接触区,但这没有应用到形成与要接触的区域接触的区。
在上述EP-A-71665公开的制造单块集成电路的方法中,单块集成电路至少包括一个双极平面型晶体管。该晶体管的集成区位于晶片形半导体基片的主表面,在场氧化层的窗口范围内在所述表面侧形成集电极。为了利用自对准技术形成发射区、基区和集电极接触区、发射极区域要用一定厚度的掩蔽氧化层部分覆盖,以使得在比较高能量的离子注入工序中基区的掺杂物能穿过该氧化层,而在比较低能量的另一离子注入工序中不让基区的掺杂物穿过氧化层。
在其中注入掩蔽限定了基区的离子注入工序后,对暴露的半导体表面进行热氧化,以形成包围发射极区的氧化条,然后去除氧化掩蔽层部分,最后,将主表面用氧化层复盖起来,该氧化层具有抵达要依靠电极形成接触的区域的窗口。象通常的平面型集成电路那样,通过导体通路与区域达到接触,这些通路被安排在多层热生长氧化层上和/或在一层淀积的氧化层上,所述通路通过这些绝缘层中的接触窗口,和接触区域或淀积在氧化层上的电极相连接。
为了在绝缘层中形成接触窗口,必须进行与要接触区域具有给定的横向间距的特殊光刻工序,以避免在半导体表面的P-N结短路。
因此,本发明要解决的问题提供了一种与上述EP-A-71665中所公开的方法相配合使用的方法,而且使得平面型晶体管的所有区域的形成与其接触区或电极达到自对准。该问题的解决利用了上述EP-A-71665中以下的先有技术方法:
制造至少包括一个双极平面型晶体管的单块集成电路,所述晶体管的集电区3位于晶片形半导体基片1的主表面,并在场氧化层2的窗口31内的所述表面侧形成集电极区,在集电区内形成发射区4和基区5,5″;
发射极区6由具有一定厚度的氧化掩蔽层部分71覆盖,使得在高能量离子注入工艺中基区5的杂质穿过所述氧化掩蔽层,在低能量离子注入工艺中基区杂质不能穿过该氧化掩蔽层;以及
在利用离子注入掩蔽M2进行离子注入工艺以定出基极区之后,对暴露的半导体表面进行热氧化,以形成围绕发射极区的氧化条21然后再去除氧化掩蔽层部分71。
本发明问题的解决采用了以下工序步骤:
a)在去除覆盖发射极区6的氧化掩蔽层部分71之后,在半导体基片1的主表面上依次制成至少由一层绝缘顶层10和一层下面的硅化物层9组成的顺序层;
b)然后,利用各向异性刻蚀,把氧化条21分成内部分15和外部分16,由此形成穿过由顶层10、硅化物层9和可能的多晶硅层8构成的顺序层的沟槽11,并使外基区部分5′和延伸至所述半导体表面的集电区3之间的P-N结部分51暴露,由此,除了发射极42之外,也定出了集电极电极32′,集电极32′迭放在场氧化层2上;
c)然后,注入基区5的导电类型的离子,把顺序层8、9、10用作掩蔽;
d)然后,淀积绝缘层17,该层覆盖沟槽11表面和顶层10的剩余部分;
e)然后,进行气相各向异性刻蚀,以使沟槽11的边缘、发射极42的边缘和集电极电极32′的边缘保持被绝缘层的剩余部分覆盖,以及
f)最后,在激活和扩散基区5的导电类型的注入离子之后,淀积用于接触所得基区接触区5″的接触层,由此,用光刻刻蚀工艺形成基极电极。
该问题的解决属于如何增加工作速度的一般问题的解决范围内。本发明的方法为这种一般问题的解决作出了贡献,这就是能够做到与发射极最接近处的基区的低电阻接触,而无需间距。
于是,本发明的方法还具有其它优点:仅有一层均匀掺杂的多晶硅被淀积,该多晶硅层可被刻蚀以限定出发射极电极和集电极电极(包括邻近的导电通路)。
这一优点既没有被上述DE-A-3129539和DE-A-3243059提供,也未被在先的欧洲专利申请86103946,9(ITT案卷L.BlossfeLd22 87年5月20日的U.S S/N 028,472)提供,所以欧洲专利申请(按54(3)条EPC)用于本发明的先有技术说明,但在该先有申请方案中,依次淀积两层多晶硅层。
在本发明方法的第一个实施例中,淀积的多晶硅层含有发射区导电类型的杂质,该导电类型与集电区导电类型相同。在用刻蚀法形成电极以后,与发射极相邻的发射区便在发射极外被扩散,相应地,相邻的集电极接触区也在集电极电极外被扩散。
相反,在另一种方法-本发明方法的第二个实施例中,在淀积要被刻蚀以定出发射极和集电极的逐层之前,把发射区导电类型的离子注入集电极区和发射极区域的暴露部分,该暴露部分分别与发射极及集电极相连接。
本发明的方法类似于EP-A-71665中所公开的方法,能与该方法配合使用,能够容易地以一定的方法得以改进,这就是CMOS电路的至少一个P沟道绝缘栅场效应晶体管和至少一个N沟道绝缘栅场效应晶体管可包含在一个集成电极中。
本发明的方法最好包括互连图形的形成,这些互连的图形如图8所表明的发射极和/或集电极。这就使得工作速度得到进一步的增加,因为与只由掺杂的多晶硅形成互连的体电阻相比,互连的体电阻得到了大大减小。
现在,参照附图说明本发明的方法及其优点,其中:
图1到图3是包含一个双极晶体管和一个CMOS电路的单块集成电路的部分剖视图,该集成电路用于说明前面已知先有技术的逐个操作过程。
图4表明依照本发明所用方法的第一步工序。
图5到图7表明图1到图3中双极晶体管的横截面图,并表明跟在图1至图3步骤之后的工艺步骤。
图1到图4也涉及到本发明方法相对于前面提到的EP-A-71665方法的改进。EP-A-71665可与本发明方法相配合使用。根据这个改进,能制成一种单块集成电路,它不仅包含有一个平面型晶体管,而且还包含有一个绝缘栅型场效应晶体管,这两个晶体管同时形成在一个半导体基片的主表面上。用同样的方法,更多的活极平面型晶体管和更多的绝缘栅型场效应晶体管,当然也能在同样的半导体基片上形成。所示的图为通常的剖面图,尺寸在半导体基片厚度方向被显著加大。
在图1到图4中,双极平面型晶体管位于基片区域31处,N沟道绝缘栅场效应晶体管位于基片区域32处,P沟道绝缘栅场效应晶体管在基片区域33处(正如图1所示)。基片区域与场氧化层2内窗口相一致,一个P+型沟道截断区域2′被安排在基片一面的场氧化层2旁边,场氧化层2由氧化掩蔽层2″形成(例如,一个二氧化硅层-氮化硅顺序层),形成方法是对氧化掩蔽层制成图形,进行离子注入以引入沟道截断区2′的杂质,然后进行热氧化。
作为固态集成电路中N沟道场效应晶体管的所有区域的替换形式,N沟道场效应管区域32通过采用一种光致抗蚀剂的注入掩蔽M1来掩蔽。正如图1箭头所指的离子注入工艺,双极平面型晶体管集电区和P沟道绝缘栅场效应晶体管的n型杂质,通过区域31和33的相当薄的氧化掩蔽层部分2″,进入基片表面,掩蔽的功能由相当厚的场氧化层2和注入掩蔽M1来完成。
在小心清除注入掩蔽M1并且在高温处理下激活注入离子之后(在高温处理工序中杂质进一步透入半导体材料中),双极晶体管的集电区3和基片区域3′被形成,如图2所示。
如图2所示,利用从图1结构的表面去除注入掩蔽M1,并且利用一个氧化掩蔽层部分71覆盖暴露的表面,该氧化掩蔽层利用一个光刻工序被刻蚀以形成部分71,双极型平面晶体管的发射极区域6被一个氧化掩蔽层部分71所覆盖。如图2所示那样,把氧化掩蔽层或其部分71形成一个下层为二氧化硅层和一个上层为氮化硅层的组合结构具有优越性。最好,覆盖集电极接触区的掩蔽层部分72留在集电极区3的边缘处,其优点在于可采用自对准技术同时制成发射极及发射区和集电极及集电极接触区。
包含集电极区3和基片区3′的结构主表面用光致抗蚀剂复盖,由此以光刻法形成注入掩蔽M2,该注入掩蔽M2留下基极区域51(包括未覆盖的发射极区域6)未覆盖光致抗蚀剂,如图2所示。
选择氧化掩蔽层的厚度,也就是选择该层的部分71的厚度,致使在杂质掺入基区的高能量离子注入工序中,这些杂质将透过这一层,而另一方面,在杂质掺入基区的低能量离子注入工序中,这一层将作为掩蔽阻挡这些杂质。在这种两级离子注入工序和接着的使得杂质被激活并扩散的热处理之后,形成的梯级基区由内部部分5和外部部分5′组成。然后,如上面提到的EP-A-71665中所述,进行热氧化以在发射极区6周围形成氧化条21,以后,氧化掩蔽层的残留部分,特别是部分71的那些残留部分被清除掉。
绝缘栅场效应晶体管的暴露区32和33,现在能按所需的阈值和所要求的类型(增强型,耗尽型)由离子注入来掺杂,而剩下的双极平面型晶体管区域31被注入掩蔽保护,最好采用光致抗蚀剂做掩蔽保护该区域。图3所示为在P沟道场效应晶体管的区域33中,使杂质从表面注入前的条件。假如选择合适的加速能量,当然,杂质能够通过氧化掩蔽层被注入,但是在仔细清除残留的光致抗蚀剂之后,氧化掩蔽层必须通过腐蚀被清除掉,以便使半导体基片位于发射极区内的部分暴露出来,仅剩下场氧化层2和氧化条21。
半导体基片1主表面被一个至少由绝缘顶层10(最好为一个氧化层)和一个在其下面的硅化物层(最好为硅化铂或者硅化钴)构成的顺序层覆盖。为此,多晶硅层8最先被淀积;它最好具有在其被淀积时已有的发射区4的导电类型杂质,或者是作为大体上纯的多晶硅层随后再以气相法或通过离子注入法提供这些杂质。接着,该下层8用一个形成有硅化物的金属层覆盖(最好用铂或钴)。根据金属层9的厚度,在适当地加热之后,获得顺序层,这些层或者仍然包括一个多晶硅层8、或者在这些层里由于金属与硅反应的结果,层8不复存在。图4示出了一种具有下层为多晶硅层8、复盖金属层9和顶层10的结构。
为了制造集成的场效应晶体管,下面的硅层8的杂质必须根据电极所需的用途来选定,也就是说,双极平面型晶体管发射区、N沟道场效应晶体管的漏区和源区以及在基片区3′上的接触区都选为n型杂质。下面的多晶层8仅在基片接触区和P沟道场放应晶体管的源区和漏区中包含P型杂质。
由于剩余工艺步骤与制造双极平面型晶体管所需要的步骤相同,图5到图8仅涉及依照本发明的方法制造双极平面型晶体管的方法。
从图4所示的结构开始(该结构已经包括了集电区3和带有其外部区5′的基区5),利用各向异性刻蚀工序,将氧化条21分成内部区15和外部区16,这样通过层8、9、10形成沟槽11。在半导体技术领域中,一般都知道各向异性刻蚀技术,用作产生垂直刻蚀剖面,正如前面从DE-A-3243059中所知道的那样。所以采用作为刻蚀掩蔽的光致抗蚀剂,它留下了未覆盖的沟槽区。接着,在一个反应容器中进行等离子体刻蚀工序,直至在位于基区5与集电区3之间的PN结部分51周围,沟槽底部的半导体表面区18被暴露出为止。此外,如图5所示定出的发射极和集电极重迭在氧化层2上。
接着,用顺序层8、9、10做为掩蔽,把基区5的导电型离子注入到在沟槽底部暴露的半导体材料中。这以后,淀积如图6所示的绝缘层17,它覆盖了沟槽11的表面,也就是,底面和侧面还有顶层10的保留部分。
然后,以气相方式再进行各向异性刻蚀,用这种方法使得沟槽11边缘,发射极电极42的边缘和集电极电极32′的边缘,仍然被所淀积的绝缘层的剩余部分所覆盖,而该绝缘层的其它部分被从顶层10上清除掉。
接着,该结构被加热到足够的高温,以激活和扩散被注入到沟槽底表面的离子,这些离子具有基区5的导电类型。这导致得到基极接触区5″,如图6和图7所示。因此,把离子注入到沟槽底部的目的变得十分明显。如果没有它们的注入,则在接着淀积要被刻蚀以限定基极电极的接触层的过程中,将导致基区与集电区之间的PN结的表面短路和对基区的接触不良,该接触层覆盖了集电极32′和发射极42的边缘。
图8是图7结构的顶视图,图7是图8中沿A-A′线的剖面图。
在图7和图8中未示出基极电极,这是因为它的形成仅要求在沟槽11底部的基极接触区5″被连接,而保持连接基极的导电通路路径具有任选性。发射极电极61和集电极电极32被绝缘顶层10覆盖,这些电极61和32′的边缘也被绝缘层保护起来。在前面描述的沟槽刻蚀工序中,集成的场效应晶体管的各区域扩散出各电极之外,这些电极是和来自顺序层8、9、10的互连通路共同形成的。
在淀积顺序层8、9、10之前,可以把发射区4的导电类型的离子注入到集电区和发射极区6的暴露部分,其优越性是能使发射区4中的杂质浓度及其厚度的设定与多晶硅层8中的杂质无关。如果制造不含有沟道场效应晶体管的集成电路,则只淀积一个仅包含发射区导电类型的杂质的均匀的多晶硅层就够了。可以在淀积之前被掺杂,也可以在其淀积之后被掺杂(例如用离子注入法)。然后,发射区4、集电极接触区31和N沟道场效应晶体管的源区和漏区被扩散到所限定的电极以外。
本发明方法的优越性是:所有电极和互连至少包含表面硅化物层或者由基极接触区的金属构成。由本发明的方法而制造的集成电路实际上具有比包含多晶硅互连的固态集成电路更低的体电阻。
Claims (3)
1、制造至少包括一个双极平面型晶体管的单块集成电路的方法,所述晶体管的集电区(3)位于晶片形半导体基片(1)的主表面,并在场氧化层(2)的窗口(31)内的所述表面侧形成集电极区,在集电区内形成发射区(4)和基区(5,5″);
发射极区(6)由具有一定厚度的氧化掩蔽层部分(71)覆盖,使得在高能量离子注入工艺中基区(5)的杂质穿过所述氧化掩蔽层,在低能量离子注入工艺中基区杂质不能穿透该氧化掩蔽层;以及
在利用离子注入掩蔽(M2)进行离子注入工艺以定出基极区后,对暴露的半导体表面进行热氧化,以形成围绕发射极区的氧化条(21),然后再去除氧化掩蔽层部分(71);
本发明方法其特征在于以下步骤:
a)在去除覆盖发射极区(6)的氧化掩蔽层部分(71)之后,在半导体基片(1)的主表面上依次制成至少由一层绝缘顶层(10)和一层下面的硅化物层(9)构成的顺序层。
b)然后,利用各向异性刻蚀,把氧化条(21)分成内部分(15)和外部分(16),由此形成穿过由顶层(10)、硅化物层(9)和可能的多晶硅层(8)构成的顺序层的沟槽(11),并使外基区部分(5′)和延伸至所述半导体表面的集电区(3)之间的PN结部分(51)暴露,由此,除了发射极(42)之外,也定出了集电极电极(32′),集电极(32′)迭放在场氧化层(2)上;
c)然后,注入基区(5)的导电类型的离子,把顺序层(8、9、10)用作掩蔽;
d)然后,淀积绝缘层(17),该层覆盖沟槽(11)表面和顶层(10)的剩余部分;
e)然后,进行气相各向异性刻蚀,以使沟槽(11)的边缘、发射极电极(42)的边缘和集电极电极(32′)的边缘保持被绝缘层的剩余部分覆盖,以及
f)最后在激活和扩散基区(5)的导电类型的注入离子后,淀积用于接触所得基区接触区(5″)的接触层,由此用光刻刻蚀工艺形成基极电极。
2、如权利要求1所述的方法,其特征在于淀积含发射区(4)的导电类型杂质的多晶硅层(8),和在所述多晶硅层(8)已被刻蚀以定出发射极电极(42)和集电极电极(32′)之后,发射区(4)被扩散出发射极电极(42)之外,至少一个集电极接触区(31)被扩散出集电极电极(32)之外。
3、如权利要求1所述的方法,其特征在于,在顺序层(8、9、10)淀积之前,把发射区(4)导电类型的离子注入发射极区(6)和集电极区的暴露部分。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP86117352A EP0270703B1 (de) | 1986-12-12 | 1986-12-12 | Verfahren zum Herstellen einer monolithisch integrierten Schaltung mit mindestens einem bipolaren Planartransistor |
EP86117352.4 | 1986-12-12 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN87107362A true CN87107362A (zh) | 1988-06-29 |
CN1007305B CN1007305B (zh) | 1990-03-21 |
Family
ID=8195643
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN87107362A Expired CN1007305B (zh) | 1986-12-12 | 1987-12-11 | 单块集成电路的制造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US4786610A (zh) |
EP (1) | EP0270703B1 (zh) |
JP (1) | JP2507499B2 (zh) |
CN (1) | CN1007305B (zh) |
DE (1) | DE3683054D1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100362636C (zh) * | 2001-07-13 | 2008-01-16 | 因芬尼昂技术股份公司 | 具多晶硅发射极双极性晶体管的制造方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR910005403B1 (ko) * | 1988-09-23 | 1991-07-29 | 삼성전자 주식회사 | 고성능 바이폴라 트랜지스터 및 그 제조방법 |
US5064773A (en) * | 1988-12-27 | 1991-11-12 | Raytheon Company | Method of forming bipolar transistor having closely spaced device regions |
FR2702307B1 (fr) * | 1993-03-05 | 1995-08-18 | Itt Ind Gmbh Deutsche | Procédé de fabrication d'un circuit intégré monolithique avec au moins un transistor à effet de champ CMOS et un transistor npn bipolaire. |
US5448085A (en) * | 1993-04-05 | 1995-09-05 | The United States Of America As Represented By The Secretary Of The Air Force | Limited current density field effect transistor with buried source and drain |
DE19540309A1 (de) * | 1995-10-28 | 1997-04-30 | Philips Patentverwaltung | Halbleiterbauelement mit Passivierungsaufbau |
US7534680B2 (en) * | 2003-11-19 | 2009-05-19 | Electronics And Telecommunications Research Institute | Bipolar transistor, BiCMOS device, and method for fabricating thereof |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56160034A (en) * | 1980-05-14 | 1981-12-09 | Fujitsu Ltd | Impurity diffusion |
NL8103032A (nl) * | 1980-08-04 | 1982-03-01 | Fairchild Camera Instr Co | Werkwijze voor het vervaardigen van een snelwerkende bipolaire transistor en transistor vervaardigd volgens deze werkwijze. |
EP0071665B1 (de) * | 1981-08-08 | 1986-04-16 | Deutsche ITT Industries GmbH | Verfahren zum Herstellen einer monolithisch integrierten Festkörperschaltung mit mindestens einem bipolaren Planartransistor |
EP0093786B1 (de) * | 1982-05-06 | 1986-08-06 | Deutsche ITT Industries GmbH | Verfahren zum Herstellen einer planaren monolithisch integrierten Festkörperschaltung mit mindestens einem Isolierschicht-Feldeffekttransistor und mit mindestens einem Bipolartransistor |
DE3243059A1 (de) * | 1982-11-22 | 1984-05-24 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von bipolartransistorstrukturen mit selbstjustierten emitter- und basisbereichen fuer hoechstfrequenzschaltungen |
DE3369030D1 (en) * | 1983-04-18 | 1987-02-12 | Itt Ind Gmbh Deutsche | Method of making a monolithic integrated circuit comprising at least one insulated gate field-effect transistor |
JPS6080267A (ja) * | 1983-10-07 | 1985-05-08 | Toshiba Corp | 半導体集積回路装置の製造方法 |
US4640721A (en) * | 1984-06-06 | 1987-02-03 | Hitachi, Ltd. | Method of forming bipolar transistors with graft base regions |
JPS6146063A (ja) * | 1984-08-10 | 1986-03-06 | Hitachi Ltd | 半導体装置の製造方法 |
US4641416A (en) * | 1985-03-04 | 1987-02-10 | Advanced Micro Devices, Inc. | Method of making an integrated circuit structure with self-aligned oxidation to isolate extrinsic base from emitter |
JPH0622238B2 (ja) * | 1985-10-02 | 1994-03-23 | 沖電気工業株式会社 | バイポ−ラ型半導体集積回路装置の製造方法 |
DE3680520D1 (de) * | 1986-03-22 | 1991-08-29 | Itt Ind Gmbh Deutsche | Verfahren zum herstellen einer monolithisch integrierten schaltung mit mindestens einem bipolaren planartransistor. |
US4721685A (en) * | 1986-04-18 | 1988-01-26 | Sperry Corporation | Single layer poly fabrication method and device with shallow emitter/base junctions and optimized channel stopper |
-
1986
- 1986-12-12 DE DE8686117352T patent/DE3683054D1/de not_active Expired - Fee Related
- 1986-12-12 EP EP86117352A patent/EP0270703B1/de not_active Expired - Lifetime
-
1987
- 1987-12-07 US US07/130,044 patent/US4786610A/en not_active Expired - Fee Related
- 1987-12-11 JP JP62313966A patent/JP2507499B2/ja not_active Expired - Lifetime
- 1987-12-11 CN CN87107362A patent/CN1007305B/zh not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100362636C (zh) * | 2001-07-13 | 2008-01-16 | 因芬尼昂技术股份公司 | 具多晶硅发射极双极性晶体管的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP0270703A1 (de) | 1988-06-15 |
CN1007305B (zh) | 1990-03-21 |
US4786610A (en) | 1988-11-22 |
EP0270703B1 (de) | 1991-12-18 |
JPH01117353A (ja) | 1989-05-10 |
DE3683054D1 (de) | 1992-01-30 |
JP2507499B2 (ja) | 1996-06-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR940011480B1 (ko) | 반도체장치 | |
KR100270796B1 (ko) | 자기정렬셀을 가진 mos게이트소자의 제조방법 | |
US4373249A (en) | Method of manufacturing a semiconductor integrated circuit device | |
KR910007377B1 (ko) | 반도체장치 | |
US4258465A (en) | Method for fabrication of offset gate MIS device | |
KR100230610B1 (ko) | 자기정렬된 웰탭을 지니는 bicmos 디바이스 및 그 제조방법 | |
KR100457413B1 (ko) | 유전체 분리구조를 갖는 절연게이트형 바이폴러트랜지스터를 갖춘 반도체장치 및 그 제조방법 | |
KR970000426B1 (ko) | 반도체 집적회로 및 그 제조방법 | |
CN1109358C (zh) | 制造双扩散mos晶体管的方法 | |
KR20020004836A (ko) | 횡형 반도체장치 | |
CN1858899A (zh) | 半导体器件及其结构的制作方法 | |
JPS622708B2 (zh) | ||
JPH08241985A (ja) | Ld−mosトランジスタ | |
CN87107362A (zh) | 至少包括一个双极平面型晶体管的单块集成电路的制造方法 | |
KR960019776A (ko) | 반도체장치 및 그 제조방법 | |
US4046607A (en) | Method of manufacturing a semiconductor device | |
WO2023169592A1 (zh) | Mosfet器件及其制造方法 | |
JPH03124065A (ja) | 集積回路素子 | |
CN1238564A (zh) | 绝缘栅晶体管、其制造方法和半导体集成电路器件 | |
CN1146970C (zh) | 金属氧化物半导体栅控结构的半导体器件 | |
EP0242893B1 (en) | Method of manufacturing a semiconductor device | |
US4216038A (en) | Semiconductor device and manufacturing process thereof | |
US6235588B1 (en) | Method of manufacturing a memory point in BICMOS technology | |
KR19990051079A (ko) | 절연막 경사식각을 이용한 전력소자 제조방법 | |
JPH06252345A (ja) | 半導体集積回路の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C13 | Decision | ||
C14 | Grant of patent or utility model | ||
C19 | Lapse of patent right due to non-payment of the annual fee |