CN86106985A - 化学淀积的导体网络中电阻器的集成方法 - Google Patents
化学淀积的导体网络中电阻器的集成方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
- H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
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- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
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- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
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Abstract
在化学或电化学方法制造的导体网络中,使高可靠性、小尺寸厚膜电阻器集成化的方法。其特征是,电阻器浆料印刷在具有导体网络的电路板基片上。该导体网络是按照丝网印刷方法印刷,并经烧结或固化。即,首先把电阻器图形和相应的连接点印刷在为了改善附着特性而进行过预处理的电路板基片上。并且在浆料烧结或固化之后,按照全加成法选择地淀积金属以制成导体线路。
Description
本发明涉及一种在化学或电化学方法制造的导体网络中,使高可靠性小尺寸厚膜电阻器集成化的方法。
用全加成工艺制造导体图形的方法在电路板技术中是已知的。同样,陶瓷基片附着金属的方法也是已知的。带有用丝网印刷、干燥并烧结浆料的厚膜工艺制成的集成电阻的网络制造方法也是已知技术。
无源元件如混合微电子电路中的电阻器的集成化,由于减少了部分焊接连接因而提高了可靠性并降低了对电路板的占用面积。越来越密的半导体封装总是要求用尽可能窄的连接导体图形。可以预见目前在厚膜技术中使用的宽度约100微米的最细线条不久就会认为是太粗了。用已知的薄膜技术或用化学金属化方法并结合适宜制造导体图形的方法可以获得更窄的导体线路宽度。这两种技术均为电阻器的集成化提供了良好的可能。但相应层的表面阻抗是如此之低,使得有较高阻值的电阻器要在电路板上占用很大的面积。用汽相淀积或阴极溅射设备涂敷电路板基片,其昂贵的价格限制了薄膜电路的应用。
本发明的目的是提供一种方法,利用这种方法,可以在化学或电化学方法制造的导体网络中,使高可靠性小尺寸的厚膜电阻器集成化目的能根据本发明用上述的方法实现,该方法的特征是,电阻浆料印刷在具有导体网络的电路板基片上,基片上的导体网络是采用经改进的印刷电路板技术制造的。按照丝网印刷工艺并经烧结或固化,或首先把电阻器图形和相应的连接点印刷在为了改善附着特性而进行预处理的电路板基片上。在浆料烧结或固化之后,按照全加成方法选择地淀积金属而制成导体线路。
根据本方法的第一类型的特定实施例包括:
a.用已知的减成技术、半加成技术或加成技术在电路板基片,最好是陶瓷基片上制造导体图形。
b.在导体图形上设置金属层,最好是镍或金。
c.用合适的浆料通过丝网印刷,干燥及烧结或固化制造电阻器图形。
根据本方法的第二类型的特定实施例包括:
d.为了粘附化学金属化,电路板基片首先进行预处理。
e.用合适的浆料通过丝网印刷、干燥及烧结或固化制成电阻器图形。
f.为避免电阻器材料不能被金属化而缺乏足够的附着力,用连接点覆盖电阻器图形,而连接点是用合适的导电浆料经丝网印刷、干燥及烧结或固化制成的。
g.用通用方法对电路板基片进行活化处理以便化学金属化,即用含钯的溶液处理,然后使之干燥。
h.用保护膜覆盖电路板基片,而露出要制造的电阻器的连接点和导体图形的部分。
i.在用保护膜覆盖电路板之后,对电路板上露出的部分进行金属化处理。金属化处理最好用铜或镍,在合适的化学还原槽中进行。
j.从电路板基片上除去保护膜,只保留那些保护电阻器图形免受环境影响的所谓永久性保护膜。
按照本发明的方法,其优点超过了已知的厚膜和薄膜工艺方法。这种方法使电路板上既有造价低廉的具有高可靠性的高电导率的导体线路,又有小尺寸的集成薄膜电阻器。从而允许进一步提高电路功能密度。
根据本发明的方法,非常适合于陶瓷基片上混合电路的制造,而且也可以用于其他无机或有机绝缘材料基片上的电路制造。
以下的实例说明按本发明的方法如何用于实际。
例1
按通常的方法,用半加成技术为玻璃纤维强化环氧树脂的粘附板提供导体图形。再用聚合的电阻器浆料印刷,并将印好的浆料干燥和固化。
例2
用化学电镀法,按铜-镍-金的层序使氧化铝陶瓷板金属化。将低温电阻器浆料印刷在该陶瓷片上,再按照生产者的规定进行干燥,并在空气中烧结。最高烧结温度为625℃。
例3
用加成技术在陶瓷基片上制成铜导体网络,再把氮气烧结的电阻器浆料印刷在陶瓷基片上,在125℃干燥、并在氮气中烧结。最高烧结温度为925℃。
例4
用合适的腐蚀剂对氧化铝陶瓷制成的电路板基片进行化学粗糙处理,使之可以附着化学金属化层。然后用电阻器浆料印刷,按照生产者的规定进行干燥、烧结。再用导电浆料印刷连接点并干燥、烧结。为进行化学金属化而在钯溶剂中将整个表面进行活化处理。然后将电路板涂敷一层耐碱的光致抗蚀剂。该光致抗蚀剂按这样的方法使之暴光和显影,即,把要进行化学镀铜的部位暴露出来。导体线路和连接点被一厚度为10微米的化学淀积的铜层所覆盖,
例5
带电阻器和相应连接点的电路板基片按例4中所说的方法进行预处理和包封。然后在电路板上涂敷光致抗蚀剂,该光致抗蚀剂按这样的方式进行暴光和显影,即,把要化学镀铜的部位(导体路线和连接点)露出。将它们用含钯的溶剂活化处理。在揭去保护层之后,露出的部位用厚度为10微米的化学淀积的铜层覆盖。
例6
陶瓷基片按例4所述的方法进行预处理,然后用电阻器浆料印刷。电阻器烧结之后,用聚合的润湿剂按例4所述的那样对电路板的整个表面进行处理和活化,以便进行化学金属淀积。在随后的工艺中,基片用光致抗蚀剂涂敷,该光致抗蚀剂按这样的方式暴光和显影,即,把导体路线和电阻器连接点这些需要金属化的部位露出。未被覆盖的部位进行化学镀镍,并在化学金槽中处理。
例7
陶瓷基片上有许多行开孔如图1所示。用激光在该陶瓷基片上划上交叉图形(如图2)。接着将陶瓷基片在熔融的碱金属氢氧化物中粗化。按图3所示的图形印刷电阻浆料,进行干燥及烧结。在窄带上(图4)印刷银-钯导电浆料,再进行干燥及烧结。然后将基片在通用的活化剂中进行活化处理,以便进行化学金属化。按图5所示的图形将合成的树脂浆料印刷在基片的背面。用模板印刷的浆料固化之后,将基片化学镀镍。沿着图形线划断基片,即可获得单片电阻器。
Claims (12)
1、在化学或电化学方法制造的导体网络中,使高可靠性、小尺寸厚膜电阻器集成化的方法,其特征在于电阻器浆料印刷在具有导体网络的电路板基片上,该导体网络是按照丝网印刷方法印刷并经烧结或固化;即,首先把电阻器图形和相应的连接点印刷在为改善附着特性而进行过预处理的电路板基片上,在浆料烧结或固化之后,按全加成法选择地淀积金属以制成导体线路。
2、按照权利要求1的方法,其特征在于用已知的减成技术、半加成技术或全加成技术在电路板基片上(最好是在陶瓷基片上)制作导体图形。
3、按照权利要求1的方法,其特征在于导体图形上设置金属层,最好用镍层或金层。
4、按照权利要求1的方法,其特征在于电阻器图形是用合适的浆料经丝网印刷、干燥及烧结或固化制成。
5、按照权利要求1的方法,其特征在于电路板基片首先进行预处理,以便粘附化学金属化层。
6、按照权利要求1的方法,其特征在于电阻器图形是用合适的浆料经丝网印刷、干燥及烧结或固化制成。
7、按照权利要求1的方法,其特征在于为避免电阻器材料不能被金属化而缺乏足够的附着力,用连接点覆盖电阻器图形,而连接点是用合适的导电浆料经丝网印刷、干燥及烧结或固化制成的。
8、按照权利要求1的方法,其特征在于用通用方法对电路板基片进行活化处理,以便化学金属化;即用含钯的溶液处理,然后使之干燥。
9、按照权利要求1的方法,其特征在于电路板基片用保护膜覆盖,而露出要制造电阻器连接点和导体图形的部分。
10、按照权利要求1的方法,其特征在于用保护膜覆盖电路板之后,对电路板上露出的部分进行金属化,金属化工艺最好用铜或镍,在合适的化学还原槽中进行。
11、按照权利要求1的方法,其特征在于从电路板基片上除去保护膜,只保留那些保护电阻器图形免受环境影响的所谓永久性保护膜。
12、按照权利要求1至11所描述的方法制成的电路板。
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Application Number | Priority Date | Filing Date | Title |
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DEP3532834.7 | 1985-09-12 | ||
DE19853532834 DE3532834A1 (de) | 1985-09-12 | 1985-09-12 | Verfahren zur integration von widerstaenden in chemisch abgeschiedene leiternetzwerke |
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CN198686106985A Pending CN86106985A (zh) | 1985-09-12 | 1986-09-11 | 化学淀积的导体网络中电阻器的集成方法 |
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EP (1) | EP0214573A3 (zh) |
JP (1) | JPS62122201A (zh) |
CN (1) | CN86106985A (zh) |
DE (1) | DE3532834A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105992452A (zh) * | 2015-02-06 | 2016-10-05 | 常熟精元电脑有限公司 | 电路板及其制造方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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DE3719219A1 (de) * | 1987-06-09 | 1988-12-22 | Grundig Emv | Verfahren zur herstellung einer leiterplatte |
JPH01319990A (ja) * | 1988-06-22 | 1989-12-26 | Sumitomo Electric Ind Ltd | 厚膜形成方法 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
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DE2553763C3 (de) * | 1975-11-29 | 1982-08-19 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Verfahren zur Herstellung einer elektronischen Schaltung |
JPS61194794A (ja) * | 1985-02-22 | 1986-08-29 | 三菱電機株式会社 | 混成集積回路基板の製造方法 |
-
1985
- 1985-09-12 DE DE19853532834 patent/DE3532834A1/de not_active Withdrawn
-
1986
- 1986-08-29 EP EP86112010A patent/EP0214573A3/de not_active Withdrawn
- 1986-09-11 CN CN198686106985A patent/CN86106985A/zh active Pending
- 1986-09-12 JP JP61214206A patent/JPS62122201A/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN105992452A (zh) * | 2015-02-06 | 2016-10-05 | 常熟精元电脑有限公司 | 电路板及其制造方法 |
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Publication number | Publication date |
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EP0214573A2 (de) | 1987-03-18 |
JPS62122201A (ja) | 1987-06-03 |
DE3532834A1 (de) | 1987-03-19 |
EP0214573A3 (de) | 1988-07-13 |
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