CN2884690Y - Clock synchronous doulbing circuit - Google Patents
Clock synchronous doulbing circuit Download PDFInfo
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- CN2884690Y CN2884690Y CN 200520132730 CN200520132730U CN2884690Y CN 2884690 Y CN2884690 Y CN 2884690Y CN 200520132730 CN200520132730 CN 200520132730 CN 200520132730 U CN200520132730 U CN 200520132730U CN 2884690 Y CN2884690 Y CN 2884690Y
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Abstract
The utility model discloses a clock synchronized frequency multiplication circuit, in particular relating to clock synchronized frequency multiplication circuit in circuit design and PLC design. The said clock synchronized frequency multiplication circuit consists of clock edge generating circuit basic module and frequency multiplication circuit basic module, high-frequency sampling clock signal and awaiting frequency multiplication clock signal are input the said clock edge generating circuit basic module, the said module generates rising and falling edge signals of awaiting frequency multiplication circuit basic module, the generated signals and the said high-frequency sampling clock signals are again input the said frequency multiplication circuit basic module, the said frequency multiplication circuit basic module generates the necessary frequency multiplication clock signals synchronized with the said awaiting frequency multiplication clock. The said utility model can, under the condition of low cost, high compatibility and without phase-locked loop, achieve a frequency multiplication clock with stability, adjustable cycle and invariable phase relationship, which overcomes the weak point of the prior art that the above problems can not be addresses simultaneously.
Description
Technical field
The utility model relates to a kind of clock multiplier circuit, relates in particular to the clock multiplier circuit in the design of circuit design and programmable logic device.
Background technology
Clock multiplier circuit is a kind of common circuit in circuit design and programmable logic device design.
In existing circuit design and programmable logic device design, the implementation method of clock multiplier circuit has following several:
1, realizes frequency multiplication with outside relative high frequency clock sampling counting.
The clock sampling that needs frequency multiplication is counted the clock after the output frequency multiplication with outside relative high frequency clock.The shortcoming of this method is, because high-frequency clock and input clock are nonsynchronous, makes clock and the input clock phase relation exported after the frequency multiplication uncertain.This frequency-doubling method can not use in many instances, and when for example clock after needing frequency multiplication and former clock had strict phase relation, this method just can not meet design requirement.
2, realize simple frequency multiplication with single d type flip flop and single XOR gate
The shortcoming of this method is that the clock width of exporting after the frequency multiplication is very narrow, can't widen.No matter be in circuit design or in the programmable logic device design, to adopt this method to realize frequency multiplication, the clock narrower in width of output, generally in 10 nanosecond, behind the circuit board cabling, clock quality can be very poor, can't use.This frequency-doubling method can not use under a lot of other occasions, for example the duty ratio of clock signal is had (being generally 40%-60%) when necessarily requiring when device, and this method can not meet the demands equally.
3, use the modulus hybrid circuit that constitutes by analogue devices such as digital logic device and capacitance-resistance, transistors to realize frequency multiplication.
The shortcoming of this method is, owing to have analogue device in the design, can't realize in programmable logic device, can only realize by circuit design, has increased the complexity and the debugging difficulty of circuit board.And the circuit that analogue device is formed can only be used for certain section specific frequency to limited bandwidth system.
4, realize frequency multiplication with PHASE-LOCKED LOOP PLL TECHNIQUE, comprise analog phase-locked look and digital delay locked loop.
It is constant that this method can be exported stable frequency doubling clock and output clock phase and input clock phase relation, and in some design, this phase relation can also be adjusted according to system's needs.But the shortcoming of this method is, phase-locked loop has certain bandwidth, frequency range to input clock has requirement, can only carry out process of frequency multiplication to the clock of certain frequency scope, for example the device that has phase-locked loop of some logical device manufacturer production can only carry out process of frequency multiplication to the clock that is higher than 25MHz, so this method for designing is restricted Change In Design; In addition, if realize PHASE-LOCKED LOOP PLL TECHNIQUE in the logical device that does not have phase-locked loop, resource occupation is big, the design cost height; If realize PHASE-LOCKED LOOP PLL TECHNIQUE, increased the complexity and the debugging difficulty of circuit again, and design cost is higher by circuit design.
5, realize frequency multiplication with the multistage delay unit time-delay of forming by basic logic unit.
This method is to be combined to form delay unit by basic logic unit, will treat the frequency doubling clock required phase place of delaying time by multistage delay unit then, and the clock after will delaying time is again realized frequency multiplication with the method for the treatment of the frequency doubling clock XOR.The shortcoming of this method is: because the time-delay of the basic logic unit of logical device is uncertain, generally between the maximin that its databook provides, change, also along with environment (as temperature, humidity etc.) change and change, so the clock that this frequency-doubling method provides is very unstable, duty ratio also is difficult to accurately control, and therefore this method can not be used in many instances; Especially, when treating the frequency doubling clock frequency when 100KHz is following, this method also will consume ample resources, and frequency is low more when realizing that duty ratio is about 50% frequency multiplication, and it is big more to consume resource.
The utility model content
The technical problem that the utility model solves provides a kind of synchronised clock frequency multiplier circuit, it can overcome in the design of clock multiplier in the prior art shortcoming separately, solves that the clock multiplier that exists in the prior art is can't simultaneous adaptation stable, phase relation is constant, highly compatible and problem cheaply.
In order to solve the problems of the technologies described above, the utility model provides a kind of clock synchronization frequency multiplier circuit, comprise that clock is along circuit base module and frequency multiplier circuit basic module take place, high frequency sampled clock signal and treat that the frequency doubling clock signal imports described clock along the circuit base module takes place, this module generates rising edge and the trailing edge signal for the treatment of frequency doubling clock, the signal of this generation and described high frequency sampled clock signal are input to described frequency multiplier circuit basic module again, generate required and the described frequency doubling clock signal for the treatment of that frequency doubling clock is synchronous by this frequency multiplier circuit basic module.
Further, described clock comprises delay unit and an XOR gate along the circuit base module takes place, described frequency doubling clock signal and the high frequency sampled clock signal treated imported described delay unit, treat the frequency doubling clock signal after time-delay of this delay unit output, import XOR gate together with the former frequency doubling clock for the treatment of again, generate described rising edge, the trailing edge signal for the treatment of frequency doubling clock.
Further, above-mentioned clock synchronization frequency multiplier circuit also can have following characteristics: described delay unit comprises first trigger and second trigger, described frequency doubling clock signal and the high frequency sampled clock signal treated imported the data input pin and the input end of clock of described first trigger respectively, the output signal of described first trigger and described high frequency sampled clock signal are imported described second flip-flop data input and the input end of clock more respectively, treat the frequency doubling clock signal after the described time-delay of the output of described second trigger.
Further, above-mentioned clock synchronization frequency multiplier circuit also can have following characteristics: described delay unit is a gate delay circuit.
Further, above-mentioned clock synchronization frequency multiplier circuit also can have following characteristics: described delay unit is that the described frequency doubling clock for the treatment of is postponed 1 to 2 high frequency sampling clock week after date output.
Further, above-mentioned clock synchronization frequency multiplier circuit also can have following characteristics: described frequency multiplier circuit basic module comprises counter, comparing unit and the 3rd trigger, the described rising edge of frequency doubling clock for the treatment of links to each other with the synchronous clear terminal of described counter with the trailing edge signal, by described high frequency sampled clock signal described counter triggers is counted, the output signal of described counter and constant signal connect the input of described comparing unit, described comparing unit compares computing to two signals, its output signal one tunnel connects the counting Enable Pin of described counter, another road is input to described the 3rd flip-flop data input, the described rising edge of frequency doubling clock for the treatment of links to each other with the set end of described the 3rd trigger with the trailing edge signal, described high frequency sampled clock signal links to each other with the input end of clock of described the 3rd trigger, and the output signal of described the 3rd trigger is and the described frequency doubling clock signal for the treatment of that frequency doubling clock is synchronous.
Further, above-mentioned clock synchronization frequency multiplier circuit also can have following characteristics: described comparing unit is a comparator or one and or door combinational logic circuit.
Further, above-mentioned clock synchronization frequency multiplier circuit also can have following characteristics: described frequency multiplier circuit basic module also comprises a selector, another road of described comparing unit output signal connects described selector earlier as selecting control signal, two inputs of described selector connect high level and low level respectively, the output signal of described selector connects described the 3rd flip-flop data input, and this selector output signal level is consistent with the output signal of described comparing unit.
Further, above-mentioned clock synchronization frequency multiplier circuit also can have following characteristics: the described rising edge of frequency doubling clock, the set end that the trailing edge signal connects described the 3rd trigger treated carries out set to the 3rd trigger.
Further, above-mentioned clock synchronization frequency multiplier circuit also can have following characteristics: described trigger is a d type flip flop
Adopt method described in the utility model, compared with prior art, reached and at low cost, highly compatible and need not under the condition of phase-locked loop, can obtain to stablize, the effect of EDM Generator of Adjustable Duty Ratio, frequency doubling clock that phase relation is constant, provide cost savings with circuit design in the veneer area, remedied not with the logical device of phase-locked loop and band phase-locked loop but treated the not deficiency of the logical device in the frequency multiplication of phase locked loop scope of frequency doubling clock frequency, solved the shortcoming that prior art can't be taken into account these several conditions simultaneously.
Description of drawings
Fig. 1 is the utility model general structure block diagram;
Fig. 2 be in the clock synchronization frequency multiplier circuit shown in Figure 1 clock along the circuit theory diagrams that circuit base module most preferred embodiment takes place;
Fig. 3 is the circuit theory diagrams of frequency multiplier circuit basic module most preferred embodiment in the clock synchronization frequency multiplier circuit shown in Figure 1.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is described in further detail.
The described clock synchronization frequency multiplier circuit of Fig. 1 comprises that the clock that links to each other in turn is along circuit base module and frequency multiplier circuit basic module take place.Treat that frequency doubling clock signal 101 and high frequency sampling clock 102 are the input signal of clock along generation circuit base module, the rising edge and the trailing edge signal 104 of frequency doubling clock treated in its output, enter the frequency multiplier circuit basic module with high frequency sampling clock 102, output frequency doubling clock 108.
High frequency sampling clock 102 can be determined according to the design needs, if veneer itself does not provide suitable clock to enter logical device, can realize by add a suitable crystal oscillator in the logical device periphery.
The operation principle of this clock synchronization frequency multiplier circuit is: treat that frequency doubling clock signal 101 and high frequency sampling clock 102 enter clock after generation circuit base module, extract rising edge and the trailing edge signal 104 for the treatment of frequency doubling clock, this signal and high frequency sampled clock signal 102 enter the frequency multiplier circuit basic module, the frequency doubling clock 108 that output duty cycle is adjustable, phase relation is constant.
Fig. 2 is that clock is along the circuit theory diagrams that circuit base module most preferred embodiment takes place in this clock synchronization frequency multiplier circuit, and it comprises two cascaded flip-flops DFF1, DFF2 and an XOR gate XOR1.Treat frequency doubling clock 101 and high frequency clock signal 102 data input pin D and the input end of clock CLK of input trigger DFF1 respectively, the output signal of trigger DFF1 and high frequency clock signal 102 be data input pin D and the input end of clock CLK of input trigger DFF2 respectively, the output signal 103 of trigger DFF2 and treat frequency doubling clock 101 input XOR gate XOR1, the rising edge and the trailing edge signal 104 of frequency doubling clock treated in XOR gate XOR1 output.
In preferred forms of the present utility model, trigger DFF1, DFF2 are d type flip flop.
This clock along the operation principle that the circuit base module takes place is: treat two the cascade d type flip flop DFF1s of frequency doubling clock 101 through being triggered by high frequency sampling clock 102, behind the DFF2, this moment, the output signal 103 of DFF2 was synchronous with high frequency clock signal 102, two metastable state problems that the clock zone transfer of data may exist have been eliminated, and the output signal 103 of DFF2 has been a signal for the treatment of that frequency doubling clock 101 postpones 1 to 2 high frequency sampling clock cycle, to treat that again the output signal 103 of frequency doubling clock 101 and DFF2 carries out XOR, just can produce the rising edge for the treatment of frequency doubling clock 101, trailing edge signal 104, the frequency multiplier circuit basic module of level after outputing to.
But, the utility model clock is not limited to this implementation method along circuit takes place, in another embodiment, the d type flip flop that can replace two cascades with the gate delay circuit, to treat that frequency doubling clock and high frequency sampling clock import this gate delay circuit, after will treating frequency doubling clock time-delay by the gate delay circuit, generate rising edge and the trailing edge signal for the treatment of frequency doubling clock by XOR with treating frequency doubling clock again.The progression of gate delay circuit is controlled according to device property and applied environment parameter.
Fig. 3 is the circuit theory diagrams of frequency multiplier circuit basic module most preferred embodiment in this clock synchronization frequency multiplier circuit, and it comprises a counter COUNT1, comparator C OMP1, a selector MUX1 and a d type flip flop DFF3.The prime clock is along the synchronous clear terminal Sclr that the rising edge for the treatment of frequency doubling clock that circuit produces and trailing edge signal 104 meet counter COUNT1 takes place, by 102 pairs of COUNT1 flip-flop numbers of high frequency sampling clock, the output signal 105 of counter COUNT1 inserts comparator C OMP1 with constant signal 106, the output signal 107 one tunnel of comparator C OMP1 connects the counting Enable Pin of counter COUNT1, another road meets selector MUX1 as selecting control signal, " 0 " of selector MUX1, " 1 " end connects low level and high level respectively, the output signal of selector MUX1 meets the data input pin D of trigger DFF3, the rising edge for the treatment of frequency doubling clock links to each other with the set end of trigger DFF3 with trailing edge signal 104, the input end of clock CLK of trigger DFF3 provides signal by high frequency sampling clock 102, and the output signal 108 of trigger DFF3 is the synchronised clock frequency-doubled signal.
The operation principle of this frequency multiplier circuit basic module is:
Carry out synchronous zero clearing by the prime clock along treat frequency doubling clock rising edge, 104 couples of counter COUNT1 of trailing edge signal that the circuit generation takes place, by 102 couples of counter COUNT1 of high frequency sampling clock flip-flop number, output signal 105 and the constant signal 106 of counter COUNT1 compare computing, the output signal 107 of comparator C OMP1 feeds back to the counting Enable Pin of counter COUNT1, have only when the output signal 107 of comparator C OMP1 is high level, counter COUNT1 just begins counting.Another road of the output signal 107 of comparator C OMP1 enters selector MUX1 as selecting control signal, when the output signal 107 of comparator C OMP1 is high level, selector MUX1 exports high level, otherwise output low level, between the rising edge for the treatment of frequency doubling clock and trailing edge, produced the frequency doubling clock of one-period.Treat that the set end that frequency doubling clock rising edge, trailing edge signal 104 meet trigger DFF3 carries out set to trigger DFF3, the frequency doubling clock 108 that guarantees output with treat that the frequency doubling clock phase relation is constant.
In the present embodiment, the value of constant signal 106 is to be determined by the duty ratio of high frequency sampling clock and the frequency ratio for the treatment of frequency doubling clock and frequency doubling clock.For specific design, constant signal generally all determined, therefore in another embodiment, also can by with or the door combinational logic circuit replace comparator C OMP1, with or the expression formula of door combinational logic can obtain by methods such as Karnaugh maps.
Selector MUX1 among Fig. 3 is provided with for clear description, can omit when reality realizes, as long as the output signal 107 of COMP1 is directly connected to the data input pin D of trigger DFF3.
In sum, the utility model produces frequency doubling clock in the method for the treatment of to count after frequency doubling clock rising edge and the trailing edge zero clearing respectively by counter, can adjust the duty ratio of frequency doubling clock by count value, the frequency doubling clock that the output signal 108 of trigger DFF3 is exactly stable, EDM Generator of Adjustable Duty Ratio, phase relation is constant.
Claims (10)
1, a kind of clock synchronization frequency multiplier circuit, it is characterized in that, comprise that clock is along circuit base module and frequency multiplier circuit basic module take place, high frequency sampled clock signal and treat that the frequency doubling clock signal imports described clock along the circuit base module takes place, this module generates rising edge and the trailing edge signal for the treatment of frequency doubling clock, the signal of this generation and described high frequency sampled clock signal are input to described frequency multiplier circuit basic module again, generate required and the described frequency doubling clock signal for the treatment of that frequency doubling clock is synchronous by this frequency multiplier circuit basic module.
2, clock synchronization frequency multiplier circuit according to claim 1, it is characterized in that, described clock comprises delay unit and an XOR gate along the circuit base module takes place, described frequency doubling clock signal and the high frequency sampled clock signal treated imported described delay unit, treat the frequency doubling clock signal after time-delay of this delay unit output, import XOR gate together with the former frequency doubling clock for the treatment of again, generate described rising edge, the trailing edge signal for the treatment of frequency doubling clock.
3, clock synchronization frequency multiplier circuit according to claim 2, it is characterized in that, described delay unit comprises first trigger and second trigger, described frequency doubling clock signal and the high frequency sampled clock signal treated imported the data input pin and the input end of clock of described first trigger respectively, the output signal of described first trigger and described high frequency sampled clock signal are imported described second flip-flop data input and the input end of clock more respectively, treat the frequency doubling clock signal after the described time-delay of the output of described second trigger.
4, clock synchronization frequency multiplier circuit according to claim 2 is characterized in that, described delay unit is a gate delay circuit.
5, clock synchronization frequency multiplier circuit according to claim 2 is characterized in that, described delay unit is that the described frequency doubling clock for the treatment of is postponed 1 to 2 high frequency sampling clock week after date output.
6, clock synchronization frequency multiplier circuit according to claim 1, it is characterized in that, described frequency multiplier circuit basic module comprises counter, comparing unit and the 3rd trigger, the described rising edge of frequency doubling clock for the treatment of links to each other with the synchronous clear terminal of described counter with the trailing edge signal, by described high frequency sampled clock signal described counter triggers is counted, the output signal of described counter and constant signal connect the input of described comparing unit, described comparing unit compares computing to two signals, its output signal one tunnel connects the counting Enable Pin of described counter, another road is input to described the 3rd flip-flop data input, the described rising edge of frequency doubling clock for the treatment of links to each other with the set end of described the 3rd trigger with the trailing edge signal, described high frequency sampled clock signal links to each other with the input end of clock of described the 3rd trigger, and the output signal of described the 3rd trigger is and the described frequency doubling clock signal for the treatment of that frequency doubling clock is synchronous.
7, clock synchronization frequency multiplier circuit according to claim 6 is characterized in that, described comparing unit is a comparator or one and or door combinational logic circuit.
8, clock synchronization frequency multiplier circuit according to claim 6, it is characterized in that, described frequency multiplier circuit basic module also comprises a selector, another road of described comparing unit output signal connects described selector earlier as selecting control signal, two inputs of described selector connect high level and low level respectively, the output signal of described selector connects described the 3rd flip-flop data input, and this selector output signal level is consistent with the output signal of described comparing unit.
9, clock synchronization frequency multiplier circuit according to claim 6 is characterized in that, the described rising edge of frequency doubling clock, the set end that the trailing edge signal connects described the 3rd trigger treated carries out set to the 3rd trigger.
10, according to claim 3 or 6 described clock synchronization frequency multiplier circuits, it is characterized in that described trigger is a d type flip flop.
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CN 200520132730 CN2884690Y (en) | 2005-11-11 | 2005-11-11 | Clock synchronous doulbing circuit |
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CN 200520132730 CN2884690Y (en) | 2005-11-11 | 2005-11-11 | Clock synchronous doulbing circuit |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101236776B (en) * | 2008-02-26 | 2011-06-29 | 北京芯技佳易微电子科技有限公司 | A serial interface flash memory and its design method |
CN102664608A (en) * | 2010-12-28 | 2012-09-12 | 博通集成电路(上海)有限公司 | Frequency multiplier and frequency multiplication method |
CN104052406A (en) * | 2014-07-08 | 2014-09-17 | 福州大学 | Frequency multiplication circuit and frequency multiplication method |
CN108259006A (en) * | 2018-01-31 | 2018-07-06 | 深圳骏通微集成电路设计有限公司 | A kind of two frequency multiplication realization devices and method |
-
2005
- 2005-11-11 CN CN 200520132730 patent/CN2884690Y/en not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101236776B (en) * | 2008-02-26 | 2011-06-29 | 北京芯技佳易微电子科技有限公司 | A serial interface flash memory and its design method |
CN102664608A (en) * | 2010-12-28 | 2012-09-12 | 博通集成电路(上海)有限公司 | Frequency multiplier and frequency multiplication method |
CN102664608B (en) * | 2010-12-28 | 2015-03-11 | 博通集成电路(上海)有限公司 | Frequency multiplier and frequency multiplication method |
CN104052406A (en) * | 2014-07-08 | 2014-09-17 | 福州大学 | Frequency multiplication circuit and frequency multiplication method |
CN104052406B (en) * | 2014-07-08 | 2016-10-05 | 福州大学 | A kind of frequency multiplier circuit and frequency-doubling method |
CN108259006A (en) * | 2018-01-31 | 2018-07-06 | 深圳骏通微集成电路设计有限公司 | A kind of two frequency multiplication realization devices and method |
CN108259006B (en) * | 2018-01-31 | 2021-04-02 | 深圳骏通微集成电路设计有限公司 | Double-frequency realization device and method |
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