CN2831617Y

CN2831617Y - Digital phase-locked loop

Info

Publication number: CN2831617Y
Application number: CN 200520074906
Authority: CN
Inventors: 李争齐
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2005-08-22
Filing date: 2005-08-22
Publication date: 2006-10-25
Anticipated expiration: 2015-08-22

Abstract

The utility model discloses a device for a digital phase locked loop, which comprises the digital phase locked loop, an input signal processing circuit, a clock conversion treating circuit and an other function processing circuit, wherein the digital phase locked loop receives an input clock signal, and generates an output clock signal and a phase locked signal; the input signal processing circuit receives the input clock signal and input data, and generates standard input data; the clock conversion treating circuit receives the standard input data, the input clock signal and the output clock signal, and generates standard output data; the other function processing circuit receives the standard output data and the output clock signal, and generates output data. The utility model can completely work normally without detecting the operating condition of PLL and resetting the digital PLL.

Description

A kind of digital phase-locked loop device

Technical field

The utility model relates to communication technique field, particularly relates to the digital phase-locked loop device that uses in programmable logic device.

Background technology

On various communication apparatus, all a large amount of use programmable logic devices.For the needs of signal processing, need various clocks, but in general; system only provides a master clock signal; in order to obtain the clock with other frequency of system master clock homology, often can use PLL (PhaseLock (ed) Loop, phase-locked loop).Digital P LL because easy to use, integrated level is high, low cost and other advantages, is directly slipped in the programmable logic device, obtains a large amount of uses.

But there is a problem in digital P LL, and a period of time after input clock is lost, it can't follow the tracks of the phase place of new clock, and same, for the sudden change of clock phase, it also can't be followed the tracks of.When this situation occurs, system may be just can't operate as normal, the most reliable method is carried out manual reset to PLL exactly.Manual reset in general the time long, bigger to the influence of signal; Most importantly may be because of various reasons, we can't know which variation has taken place input clock.

A kind of possible method is the lock flag of checking PLL, but the reliability of this sign can't guarantee, need ask input clock to lose the long time and just can provide alarm, and the situation that can't adapt to the input clock SPA sudden phase anomalies, secondly the designer must could detect this alarm at clock of introduction in addition, and system may not have such clock.

Fig. 1 is the schematic diagram of current PLL using method.

The defective of current method:

1: after input clock (input clock) loses a period of time, again recover, the phase place that outputclock_1 (output clock 1) just can't follow the tracks of input clock, make that the sampling of data may go wrong in interfaceprocess (current process), need reset this moment to PLL could operate as normal;

Resetting of 2:PLL is feasible bigger to the influence of signal;

3: PLL resetted needs manual intervention, and reaction speed is slow;

4: PLL is resetted and need detect lock (phase-locked) signal or input clock, detect ten fens difficulties of input clock, detect lock signal demand another one clock;

5: when a sudden change took place for the phase place of input clock, PLL can't continue to follow the tracks of the phase place of inputclock, and on this moment lock signal without any reaction.

The utility model content

Technical problem to be solved in the utility model provides a kind of digital phase-locked loop device, and solving prior art must detect the operating state of PLL, the digital PLL that need reset, the just technical problem of operate as normal fully.

For achieving the above object, the utility model provides a kind of digital phase-locked loop device, and its characteristics are, comprising: digital phase-locked loop, input signal treatment circuit, clock conversion processing circuit and all the other function treatment circuit; Described digital phase-locked loop receives an input clock signal, produces a clock signal and a lockin signal; Described input signal treatment circuit receives described input clock signal and input data, produces standard input data; Described clock conversion processing circuit receives described standard input data, described input clock signal and described clock signal, produces a standard dateout; Described all the other function treatment circuit receive described standard dateout and described clock signal, produce a dateout.

Above-mentioned digital phase-locked loop device, its characteristics are that described clock conversion processing circuit comprises an asynchronous first in first out device, import described standard input data, described input clock signal and described clock signal, export described standard dateout.

Above-mentioned digital phase-locked loop device, its characteristics are that described clock conversion processing circuit also comprises write control circuit, imports described input clock signal, export a writing address signal to described asynchronous first in first out device.

Above-mentioned digital phase-locked loop device, its characteristics are that described clock conversion processing circuit also comprises reads control circuit, read address signal to described asynchronous first in first out device output one.

Above-mentioned digital phase-locked loop device, its characteristics are that described clock conversion processing circuit also comprises phase detecting circuit, import described writing address signal and the described address signal of reading, and export an adjustment indication to the described control circuit of reading.

Technique effect of the present utility model is:

1: do not re-use one of PLL output and input clock with clock frequently,

2: use asynchronous FIFO (first in first out) to realize the function of clock domain change process (clock conversion processing circuit), asynchronous FIFO substitutes the Synchronous Processing mode of the original shift register that uses, owing to can be avoided the clock phase problem between the input and output fully.Therefore can accomplish the not damaged of data is passed through.

3: do not need the clock signal input clock of input is detected, avoided the reset operation of PLL, the various abnormal conditions that can adapt to the output clock are handled.

Therefore the utility model can be not detect the operating state of PLL, does not need the digital PLL that resets, just operate as normal fully.

Further describe specific embodiment of the utility model below in conjunction with accompanying drawing.

Description of drawings

Fig. 1 is the schematic diagram of prior art phase-locked loop using method;

Fig. 2 is a circuit structure diagram of the present utility model;

Fig. 3 is the circuit structure diagram of clock domain change process in the utility model.

Embodiment

The utility model is the improvement of carrying out on the basis of existing technology,

The utility model comprises following a few this part (as shown in Figure 2):

1): digital P LL 201;

This digital PLL uses input clock (input clock) as input, and output clock_0 (output clock 0) is as output.Wherein the frequency of output clock_0 and phase place can be determined by the parameter that PLL is set, and output clock_0 is as the input clock of clock conversion processing circuit and other treatment circuit.

Embedded PLL among the FPGA of the Stratix series that an application example of 201 circuit is altera corps

2): input signal treatment circuit 202 (input process);

Input Data (input data) during the input data of this circuit, the clock of input is input clock, the effect of this circuit is the requirement according to other treatment circuit output format, convert inputData to reference format Din (standard input data), send to clock conversion processing circuit 203.Bus multiplex circuit in the SDH product that an application example of 202 circuit is ZTE

3): clock conversion processing circuit 203 (clock domain change process);

This circuit has two output clocks, and one is input clock, and another is outputclock_0, and input data Data in (it is the output signal of input signal treatment circuit) are arranged.It will be imported data Data in and use input clock to write an asynchronous FIFO, using outputclock_0 that data are read from FIFO, send to other treatment circuit by Dout (standard dateout).

4): other treatment circuit (all the other function treatment circuit) 204 (other process):

Handle as required;

Pointer interpreter circuit in the SDH product that an application example of 204 circuit is ZTE companies

As shown in Figure 3, clock conversion processing circuit 203 is made up of following several sections:

3.1): asynchronous FIFO 301

This FIFO is used for store data, and its data that write are exactly Data in, and its sense data is exactly Dout.

Embedded dual port RAM in the Stratix series that the application example of this asynchronous FIFO 301 is an altera corp

3.2): write control circuit 302 (write control);

Under the effect of input clock, to the data Data in of each input with current write address pointer as

The position of current data Data in FIFO is written among the FIFO and goes, and write address pointer adds 1 simultaneously.

The application example of 302 circuit is accumulators

3.3): read control circuit 303 (read control);

If input signal adjust is invalid, according to the frequency of output clock_0, each cycle will be read address pointer and be added one; Otherwise, to reading address pointer adjustment, can make except adding any way 1, for example zero clearing, constant, adding one is not fixed value of 1 etc.

The application example of 303 circuit is accumulators that have set function

3.4): phase detecting circuit 304 (phase detection):

Check the phase relation between the read/write address pointer,, taking place to adjust indication adjust, otherwise removing adjust if both differ the threshold value less than a regulation

The application example of 304 circuit is comparators

As from the foregoing, the utlity model has following characteristics:

1: do not re-use one of PLL output and input clock with clock frequently,

2: use asynchronous FIFO to realize the function of clock domain change process, substitute the Synchronous Processing mode of the original shift register that uses, because asynchronous FIFO can be avoided the clock phase problem between the input and output fully.Therefore can accomplish the not damaged of data is passed through.

The utility model can be not detect the operating state of PLL, does not need the digital PLL that resets, just operate as normal fully

The above is preferred embodiment of the present utility model only, is not to be used for limiting practical range of the present utility model; Every equivalence of doing according to the utility model changes and revises, and is all contained by utility model scope of the present utility model.

Claims

1, a kind of digital phase-locked loop device is characterized in that, comprising: digital phase-locked loop, input signal treatment circuit, clock conversion processing circuit and all the other function treatment circuit;

Described digital phase-locked loop receives an input clock signal, produces a clock signal and a lockin signal;

Described input signal treatment circuit receives described input clock signal and input data, produces standard input data;

Described clock conversion processing circuit receives described standard input data, described input clock signal and described clock signal, produces a standard dateout;

Described all the other function treatment circuit receive described standard dateout and described clock signal, produce a dateout.

2, digital phase-locked loop device according to claim 1, it is characterized in that, described clock conversion processing circuit comprises an asynchronous first in first out device, imports described standard input data, described input clock signal and described clock signal, exports described standard dateout.

3, digital phase-locked loop device according to claim 2 is characterized in that, described clock conversion processing circuit also comprises write control circuit, imports described input clock signal, exports a writing address signal to described asynchronous first in first out device.

4, digital phase-locked loop device according to claim 3 is characterized in that, described clock conversion processing circuit also comprises reads control circuit, reads address signal to described asynchronous first in first out device output one.

5, digital phase-locked loop device according to claim 4 is characterized in that, described clock conversion processing circuit also comprises phase detecting circuit, imports described writing address signal and the described address signal of reading, and exports an adjustment indication to the described control circuit of reading.