CN106301748A - Clock output intent and device - Google Patents

Abstract

The invention provides a kind of clock output intent and device, wherein, the method includes: digital phase-locked loop DPLL receives the recovered clock of output, and wherein, this DPLL is the logical resource configuration using chip；Above-mentioned DPLL exports clock according to DPLL state in which.By the present invention, solve equipment cost height, the problem of PCB design complexity present in correlation technique, and then reached to reduce equipment cost and the effect of PCB design complexity.

Description

Clock output intent and device

Technical field

The present invention relates to the communications field, in particular to a kind of clock output intent and device.

Background technology

In communication equipment is applied, a lot of interface requirements realize transmitting terminal can follow the frequency of receiving terminal, referred to as timing Loop fuction (Loop Timing).The most traditional Synchronous Optical Network (Synchronous Optiical Network, letter It is referred to as SONET)/SDH (Synchronous Digital Hierarchy, referred to as SDH) transmission network, Optical transport network (Optical Transport Network, referred to as OTN) in backbone network and Metropolitan Area Network (MAN), in packet network All ports havings such as synchronous ethernet (Synchronous Ethernet networks) between the demand of Frequency Synchronization.In communication In the system design of device port Frequency Synchronization, when the port frequency synchronization implementation in correlation technique typically uses outside Clock pattern and line clock pattern two kinds.

Fig. 1 is that the port frequency under the external clocking mode in correlation technique synchronizes schematic diagram.As shown in Figure 1, employing is worked as During the port frequency method of synchronization of external clocking mode, the network equipment needs from outside Building Integrated Timing Supply (Building Integrated Timing System, referred to as BITS) clock source obtains clock information, the distribution of this synchronised clock It is most reliable mode, but needs to increase expensive BITS equipment at central machine room.

Fig. 2 is that the port frequency under the line clock pattern in correlation technique synchronizes schematic diagram, as shown in Figure 2, uses line During the clock module of road, the first order network equipment uses outside bits timing source, by synchronised clock information from emission port Tx It is delivered to the receiving port Rx of the second level network equipment.Second level network equipment Rx recovers synchronised clock letter from receiving side Breath, synchronised clock information is recovered by clock and data recovery (Clock Data Recovery, referred to as CDR) Outside narrow band phase lock loop (Phase-Locked Loop, referred to as PLL) delivered to by clock, provides height after PLL processes Quality references clock is to Tx direction PHY (Physical Layer Protocol, referred to as PHY) module.Adopt The phaselocked loop being required for an outside with each port of scheme of outside phaselocked loop processes recovered clock, when design high density During multi-channel interface plate, this interface board may require that a lot of outside phaselocked loop of increase.This can bring extra cost, bigger Power consumption, the problems such as printed circuit board (PCB) (Printed Circuit Board, referred to as PCB) design complexities is high.

Therefore, when needs realize port frequency synchronize time, use the scheme in correlation technique can also exist equipment cost high, The problem that PCB design is complicated.

The problem high for equipment cost present in correlation technique, PCB design is complicated, the most not yet proposes effective solution Certainly scheme.

Summary of the invention

The invention provides a kind of clock output intent and device, with at least solve equipment cost present in correlation technique high, The problem that PCB design is complicated.

According to an aspect of the invention, it is provided a kind of clock output intent, including: digital phase-locked loop DPLL receives The recovered clock of output, wherein, described DPLL is the logical resource configuration using chip；Described DPLL is according to institute State DPLL state in which output clock.

Alternatively, the described recovered clock of described DPLL reception output includes: described DPLL receives serializer Serdes The recovered clock of sending side output；Described DPLL includes according to described DPLL state in which output clock: described DPLL receives side output clock according to the state serially device Serdes that described DPLL is in.

Alternatively, described DPLL, before according to described DPLL state in which output clock, also includes: described DPLL is according to the parameter of the requirement described DPLL intraware of configuration of the reference clock of described Serdes sending side, wherein, Described DPLL intraware includes at least one of: phase discriminator, wave filter, frequency plot controller.

Alternatively, described DPLL includes according to described DPLL state in which output clock: described DPLL determines institute Stating DPLL state in which, wherein, described state includes one below: freely shake state, hold mode, locking State；Described DPLL is according to the State-output clock determined.

Alternatively, described DPLL includes according to the State-output clock determined: when described DPLL state in which is for certainly During by concussion state, described DPLL according to the parameter of described DPLL intraware of configuration to described Serdes sending side Sending a free clock, wherein, the frequency of described free clock is uncorrelated with the frequency of described recovered clock；When described When DPLL state in which is hold mode, described DPLL according to configuration described DPLL intraware parameter to Described Serdes transmitting terminal sends the clock of a fixed frequency, and wherein, described fixed frequency is to lock before described DPLL The frequency of the clock determined；When described DPLL state in which is lock-out state, described DPLL is according to the institute of configuration Described recovered clock is processed by the parameter stating DPLL intraware；Recovered clock after described DPLL will process is sent out Give described Serdes sending side.

According to a further aspect in the invention, it is provided that a kind of clock output device, described device is applied to digital phase-locked loop In DPLL, including: receiver module, for receiving the recovered clock of output, wherein, described DPLL is to use chip Logical resource configuration；Output module, for exporting clock according to described DPLL state in which.

Alternatively, described receiver module includes: receive the recovered clock of serializer Serdes sending side output；Described output Module includes: the state serially device Serdes being according to described DPLL receives side output clock.

Alternatively, described device also includes: configuration module, wanting for the reference clock according to described Serdes sending side Seeking the parameter configuring described DPLL intraware, wherein, described DPLL intraware includes at least one of: mirror Phase device, wave filter, frequency plot controller.

Alternatively, described output module comprises determining that unit, is used for determining described DPLL state in which, wherein, Described state includes one below: freely shake state, hold mode, lock-out state；Output unit, for according to really Fixed State-output clock.

Alternatively, described output unit includes: when described DPLL state in which is for freely shaking state, described DPLL according to configuration described DPLL intraware parameter to described Serdes sending side send a free clock, Wherein, the frequency of described free clock is uncorrelated with the frequency of described recovered clock；When described DPLL state in which is During hold mode, described DPLL sends out to described Serdes transmitting terminal according to the parameter of the described DPLL intraware of configuration Sending the clock of a fixed frequency, wherein, described fixed frequency is the frequency of the clock that described DPLL front-locking is crossed； When described DPLL state in which is lock-out state, described DPLL is according to the described DPLL intraware configured Described recovered clock is processed by parameter；Recovered clock after described DPLL will process is sent to described Serdes transmission Side.

By the present invention, using digital phase-locked loop DPLL to receive the recovered clock of output, wherein, described DPLL is to make With the logical resource configuration of chip；Described DPLL exports clock according to described DPLL state in which, solves phase The problem that present in the technology of pass, equipment cost is high, PCB design is complicated, and then reached reduction equipment cost and PCB The effect of design complexities.

Accompanying drawing explanation

Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, the present invention Schematic description and description be used for explaining the present invention, be not intended that inappropriate limitation of the present invention.In the accompanying drawings:

Fig. 1 is that the port frequency under the external clocking mode in correlation technique synchronizes schematic diagram；

Fig. 2 is that the port frequency under the line clock pattern in correlation technique synchronizes schematic diagram；

Fig. 3 is the flow chart of clock output intent according to embodiments of the present invention；

Fig. 4 is the structured flowchart of clock output device according to embodiments of the present invention；

Fig. 5 is the preferred structure block diagram of clock output device according to embodiments of the present invention；

Fig. 6 is the structured flowchart of output module 44 in clock output device according to embodiments of the present invention；

Fig. 7 be single-chip according to embodiments of the present invention realize communication equipment port frequency synchronize realize device schematic diagram；

Fig. 8 is the method flow diagram that single-chip according to embodiments of the present invention realizes that communication equipment port frequency synchronizes.

Detailed description of the invention

Below with reference to accompanying drawing and describe the present invention in detail in conjunction with the embodiments.It should be noted that in the feelings do not conflicted Under condition, the embodiment in the application and the feature in embodiment can be mutually combined.

It should be noted that term " first " in description and claims of this specification and above-mentioned accompanying drawing, " second " Etc. being for distinguishing similar object, without being used for describing specific order or precedence.

Providing a kind of clock output intent in the present embodiment, Fig. 3 is clock output intent according to embodiments of the present invention Flow chart, as it is shown on figure 3, this flow process comprises the steps:

Step S302, digital phase-locked loop DPLL receives the recovered clock of output, and wherein, this DPLL is to use chip Logical resource configuration；

Step S304, above-mentioned DPLL exports clock according to DPLL state in which.

By above-mentioned steps, digital phase-locked loop (Digital Phase Locked Loop, referred to as DPLL) is utilized to receive Recovered clock and output clock, and, this DPLL is the digital phase-locked loop utilizing the logical resource of chip to configure, nothing Chip internal and external dedicated phaselocked loop resource need to be taken, therefore, in high-density multi-port communication device interface plate designs, Fully according to physical port quantity full configuration DPLL, and the design of equipment cost and PCB can be greatly reduced again Miscellaneous degree, thus solve equipment cost height, the problem of PCB design complexity present in correlation technique, and then reached fall Low equipment cost and the effect of PCB design complexity.

In an optional embodiment, above-mentioned DPLL receives the recovered clock of output and includes: this DPLL receives serial The recovered clock of device Serdes sending side output；Above-mentioned DPLL includes according to DPLL state in which output clock: should DPLL receives side output clock according to the state serially device Serdes that DPLL is in.Wherein, DPLL is receiving Serdes Before the recovered clock of sending side output, first Serdes sending side can obtain recovered clock, and its acquisition mode can be Multiple, illustrate with a kind of example below: Serdes receives the serializer clock and data recovery Serdes CDR in side Recovered clock signal from high speed serialization code stream, i.e. obtains recovered clock.

In an optional embodiment, above-mentioned DPLL, before according to DPLL state in which output clock, also wraps Include: this DPLL is according to the parameter of the requirement configuration DPLL intraware of the reference clock of Serdes sending side, wherein, This DPLL intraware includes at least one of: phase discriminator, wave filter, frequency plot controller.Need explanation Be, DPLL according to the reference clock of Serdes sending side requirement configure DPLL intraware parameter operation and on The sequencing of the operation that digital phase-locked loop DPLL stated receives the recovered clock of output can be multiple, and DPLL is permissible First configure the parameter of DPLL intraware, receive recovered clock the most again；Can also first receive recovered clock, be reconfigured at The parameter of DPLL intraware；It is of course also possible to receive recovered clock and the parameter of configuration DPLL intraware simultaneously. Wherein, the purpose of this DPLL configuration above-mentioned parameter is the clock of outputting high quality.

In an optional embodiment, above-mentioned DPLL includes according to DPLL state in which output clock: this DPLL Determining DPLL state in which, wherein, this DPLL state in which includes one below: freely shake state, guarantor Hold state, lock-out state；This DPLL is according to the State-output clock determined.So that it is guaranteed that output meets transmission network association The view high-quality clock frequency to port clock jitter index request.

In an optional embodiment, above-mentioned DPLL includes according to the State-output clock determined: when this DPLL institute The state at place is when be freely to shake state, DPLL according to the parameter of the DPLL intraware configured to Serdes sending side Sending a free clock, wherein, the frequency of this free clock is uncorrelated with the frequency of recovered clock；When this DPLL institute When the state at place is hold mode, DPLL sends to Serdes transmitting terminal according to the parameter of the DPLL intraware of configuration The clock of one fixed frequency, wherein, this fixed frequency is the frequency of the clock that DPLL front-locking is crossed；As this DPLL When state in which is lock-out state, DPLL according to the parameter of DPLL intraware of configuration to recovered clock at Reason；Recovered clock after this DPLL will process is sent to Serdes sending side.

Through the above description of the embodiments, those skilled in the art is it can be understood that arrive according to above-described embodiment Method can add the mode of required general hardware platform by software and realize, naturally it is also possible to by hardware, but a lot In the case of the former is more preferably embodiment.Based on such understanding, technical scheme is the most in other words to existing The part having technology to contribute can embody with the form of software product, and this computer software product is stored in one In storage medium (such as ROM/RAM, magnetic disc, CD), including some instructions with so that a station terminal equipment (can To be mobile phone, computer, server, or the network equipment etc.) perform the method described in each embodiment of the present invention.

Additionally providing a kind of clock output device in the present embodiment, this device is used for realizing above-described embodiment and being preferable to carry out Mode, had carried out repeating no more of explanation.As used below, term " module " can realize predetermined function Software and/or the combination of hardware.Although the device described by following example preferably realizes with software, but firmly Part, or the realization of the combination of software and hardware also may and be contemplated.

Fig. 4 is the structured flowchart of clock output device according to embodiments of the present invention, and this device can apply to digital servo-control In ring DPLL, as shown in Figure 4, this device includes receiver module 42 and output module 44, carries out this device below Explanation.

Receiver module 42, for receiving the recovered clock of output, wherein, this DPLL is that the logical resource using chip is joined Put；Output module 44, is connected to above-mentioned receiver module 42, for exporting clock according to DPLL state in which.

In an optional embodiment, above-mentioned receiver module 42 includes: receive the output of serializer Serdes sending side Recovered clock；Above-mentioned output module 44 includes: the state serially device Serdes being according to DPLL receives side output Clock.

Fig. 5 is the preferred structure block diagram of clock output device according to embodiments of the present invention, as it is shown in figure 5, this device removes Outside including all modules shown in Fig. 4, also include configuring module 52, below this device is illustrated.

Configuration module 52, is connected to above-mentioned output module 44, for the requirement of the reference clock according to Serdes sending side The parameter of configuration DPLL intraware, wherein, this DPLL intraware includes at least one of: phase discriminator, filter Ripple device, frequency plot controller.

Fig. 6 is the structured flowchart of output module 44 in clock output device according to embodiments of the present invention, as shown in Figure 6, This output module 44 includes determining unit 62 and output unit 64, illustrates this output module 44 below.

Determining unit 62, be used for determining DPLL state in which, wherein, this state includes one below: freely shake State, hold mode, lock-out state；Output unit 64, be connected to above-mentioned determine unit 62, for according to determining State-output clock.

In an optional embodiment, above-mentioned output unit 64 includes: when DPLL state in which is for freely to shake During state, this DPLL according to configuration DPLL intraware parameter to Serdes sending side send a free clock, Wherein, the frequency of this free clock and the frequency of recovered clock are uncorrelated；When DPLL state in which is hold mode, This DPLL according to configuration DPLL intraware parameter to Serdes transmitting terminal send a fixed frequency clock, Wherein, this fixed frequency is the frequency of the clock that DPLL front-locking is crossed；When DPLL state in which is lock-out state Time, recovered clock is processed by this DPLL according to the parameter of the DPLL intraware of configuration；After DPLL will process Recovered clock be sent to Serdes sending side.

For solving the problem that the port frequency synchronization scenario in above two correlation technique exists, the embodiment of the present invention also carries Go out a kind of apparatus and method utilizing single-chip to realize the synchronization of communication equipment port frequency, utilize chip internal logic realization DPLL carry out process circuit recovered clock, and, after being configured with the relevant parameter of DPLL, it is possible to outputting high quality Reference clock to transmitting terminal, thus realize the Frequency Synchronization of each port on communication equipment.Below this device and method is entered Row explanation.

Fig. 7 be single-chip according to embodiments of the present invention realize communication equipment port frequency synchronize realize device schematic diagram, As it is shown in fig. 7, this device includes with lower module:

Serdes receiver module 72, Serdes sending module 74 and DPLL module 76 (with above-mentioned receiver module 42, Output module 44 and configuration module 52), below this device is illustrated.

Serdes receiver module 72 and Serdes sending module 74 is the reception of HSSI High-Speed Serial Interface and sends processing module. DPLL module 76 is used for realizing port frequency and synchronizes.Wherein, Serdes receiver module 72, Serdes sending module 74 With relation between DPLL module 76 is as follows.

Serdes receiver module 72 receives side interconnection with optical module, except realizing basic Serial data receiving, going here and there and turn Beyond changing and decoding, mainly utilize Serdes CDR module output recovered clock to give DPLL module 76 and process.

DPLL module 76 mainly realizes the locking to CDR recovered clock, and according to configuration parameter, generates the most high-quality Amount clock is to Serdes sending module 74.DPLL control module in DPLL module 76 needs to lock according to DPLL State realizes free oscillation, keeps and lock the switching of three kinds of states, it is ensured that when output meets transport network protocols to port The high-quality clock frequency of clock shake index request.

In system designs, each physical port should be furnished with independent DPLL.Owing to DPLL is entirely by logic list Unit realizes, and is not take up chip internal and external dedicated phaselocked loop resource, therefore at high-density multi-port communication device interface plate In design, DPLL can be put fully according to physical port quantity full configuration, it is achieved the other clock rate synchronization of port level.Press According to the solution provided in this embodiment, can promote while communicating equipment product performance, save hardware cost, Power consumption and the design difficulty of reduction veneer.

Fig. 8 is the method flow diagram that single-chip according to embodiments of the present invention realizes that communication equipment port frequency synchronizes, such as figure Shown in 8, the method comprises the steps:

Step S802: chip Serdes receives side and judges whether to receive effective high-speed serial signals, as received, holds Row S804, otherwise, continues waiting for；

Step S804:Serdes CDR lock operation, when Serdes receives recovery the high speed serialization code stream of side output Clock information, when CDR state machine enters lock-out state, shows that the recovered clock of now CDR output has been stablized, permissible Being supplied to subordinate's module use, CDR locking signal triggers S806 operation；

After step S806:Serdes receiver module 72 judges that CDR locking and Serdes reception state etc. are normal, output Stable recovered clock gives the DPLL module 76 that this port is corresponding；

Step S808:DPLL module 76 configures relevant parameter, configures the requirement of sending side reference clock according to system DPLL intraware, the such as parameter such as phase discriminator, wave filter and frequency plot control, wait S810 after parameter configuration is good The result of step；

Step S810: after judging DPLL lock-out state, performs tri-steps of S812, S814 and S816, initially Changing powers in locking process, performs step S812；In the locked state, step S816 is performed；In an out-of-lock condition, Perform step S814；

Step S812:DPLL free-running operation, now DPLL module 76 exports a free clock, time free Clock frequency rate is uncorrelated with input clock (recovered clock with above-mentioned)；

Step S814:DPLL hold mode, now DPLL is during relocking, and DPLL module 76 keeps The clock of the rate-adaptive pacemaker fixed frequency of front-locking；

Step S816:DPLL lock-out state, now DPLL is in locking process, DPLL module 76 output time The frequency of the recovered clock of the frequency following input of clock；

Step S818:DPLL module 76 exports clock and gives Serdes sending side phaselocked loop, by frequency multiplication of phase locked loop to being The required clock frequency of system.

In summary, in the method realizing the synchronization of communication equipment port frequency in correlation technique, external clocking mode scheme Need expensive BITS equipment；Line clock pattern uses outside phaselocked loop to realize clock recovery can bring cost, merit The problems such as consumption and design complexities.The problems such as the complexity due to design, use outside phaselocked loop to realize the side of clock recovery Case often cannot accomplish the other Frequency Synchronization of port level, can only reduce performance and realize the clock recovery of board level.Use this Method and apparatus in inventive embodiments, compared with correlation technique, the DPLL using chip internal logical resource to build comes Realize port clock frequency retrieval, hardware cost can be saved and reduce single while promoting communicating equipment product performance The design difficulty of plate.Along with, under the trend that communication products physical port density improves and cost optimization pressure increases, using this The port frequency synchronous method that patent provides carrys out design interface veneer, advantageously reduces cost and reduces power consumption, improving veneer Design flexibility.

It should be noted that above-mentioned modules can be by software or hardware realizes, for the latter, Ke Yitong Cross in the following manner to realize, but be not limited to this: above-mentioned module is respectively positioned in same processor；Or, above-mentioned module position respectively In multiple processors.

Embodiments of the invention additionally provide a kind of storage medium.Alternatively, in the present embodiment, above-mentioned storage medium can To be arranged to storage for the program code performing following steps:

S1, digital phase-locked loop DPLL receives the recovered clock of output, and wherein, this DPLL is the logic money using chip Source configuration；

S2, above-mentioned DPLL export clock according to DPLL state in which.

Alternatively, in the present embodiment, above-mentioned storage medium can include but not limited to: USB flash disk, read only memory (Random Access Memory is called for short for (Read-Only Memory, referred to as ROM), random access memory For RAM), portable hard drive, the various media that can store program code such as magnetic disc or CD.

Alternatively, the concrete example in the present embodiment is referred to showing described in above-described embodiment and optional embodiment Example, the present embodiment does not repeats them here.

Obviously, those skilled in the art should be understood that each module of the above-mentioned present invention or each step can be with general Calculating device to realize, they can concentrate on single calculating device, or be distributed in multiple calculating device and formed Network on, alternatively, they can realize, it is thus possible to by them with calculating the executable program code of device Storage is performed by calculating device in the storage device, and in some cases, can hold with the order being different from herein Step shown or described by row, or they are fabricated to respectively each integrated circuit modules, or by many in them Individual module or step are fabricated to single integrated circuit module and realize.So, the present invention is not restricted to any specific hardware Combine with software.

The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for the technology of this area For personnel, the present invention can have various modifications and variations.All within the spirit and principles in the present invention, that is made is any Amendment, equivalent, improvement etc., should be included within the scope of the present invention.

Claims (10)

1. a clock output intent, it is characterised in that including:

Digital phase-locked loop DPLL receives the recovered clock of output, and wherein, described DPLL is the logic money using chip Source configuration；

Described DPLL exports clock according to described DPLL state in which.

Method the most according to claim 1, it is characterised in that

Described DPLL receives the described recovered clock of output and includes: described DPLL receives serializer Serdes sending side The recovered clock of output；

Described DPLL includes according to described DPLL state in which output clock: described DPLL is according to described DPLL The state being in serially device Serdes receives side output clock.

Method the most according to claim 2, it is characterised in that described DPLL is according to described DPLL state in which Before output clock, also include:

Described DPLL configures described DPLL intraware according to the requirement of the reference clock of described Serdes sending side Parameter, wherein, described DPLL intraware includes at least one of: phase discriminator, wave filter, frequency plot Controller.

Method the most according to claim 3, it is characterised in that described DPLL is defeated according to described DPLL state in which Go out clock to include:

Described DPLL determines described DPLL state in which, and wherein, described state includes one below: freely shake Swing state, hold mode, lock-out state；

Described DPLL is according to the State-output clock determined.

Method the most according to claim 4, it is characterised in that described DPLL is according to the State-output clock bag determined Include:

When described DPLL state in which is freely to shake state, described DPLL is according to the described DPLL of configuration The parameter of intraware sends a free clock, wherein, described free clock to described Serdes sending side Frequency is uncorrelated with the frequency of described recovered clock；

When described DPLL state in which is hold mode, inside the described DPLL described DPLL according to configuration The parameter of assembly sends the clock of a fixed frequency, wherein, described fixed frequency to described Serdes transmitting terminal Frequency for the clock that described DPLL front-locking is crossed；

When described DPLL state in which is lock-out state, inside the described DPLL described DPLL according to configuration Described recovered clock is processed by the parameter of assembly；Recovered clock after described DPLL will process is sent to described Serdes sending side.

6. a clock output device, it is characterised in that be applied in digital phase-locked loop DPLL, including:

Receiver module, for receiving the recovered clock of output, wherein, described DPLL is the logic money using chip Source configuration；

Output module, for exporting clock according to described DPLL state in which.

Device the most according to claim 6, it is characterised in that

Described receiver module includes: receive the recovered clock of serializer Serdes sending side output；

Described output module includes: when the state serially device Serdes being according to described DPLL receives side output Clock.

Device the most according to claim 7, it is characterised in that also include:

Configuration module, the requirement for the reference clock according to described Serdes sending side configures inside described DPLL The parameter of assembly, wherein, described DPLL intraware includes at least one of: phase discriminator, wave filter, frequently Rate phase controller.

Device the most according to claim 8, it is characterised in that described output module includes:

Determining unit, be used for determining described DPLL state in which, wherein, described state includes one below: Freely shake state, hold mode, lock-out state；

Output unit, for according to the State-output clock determined.

Device the most according to claim 9, it is characterised in that described output unit includes:

When described DPLL state in which is freely to shake state, described DPLL is according to the described DPLL of configuration The parameter of intraware sends a free clock, wherein, described free clock to described Serdes sending side Frequency is uncorrelated with the frequency of described recovered clock；

When described DPLL state in which is hold mode, inside the described DPLL described DPLL according to configuration The parameter of assembly sends the clock of a fixed frequency, wherein, described fixed frequency to described Serdes transmitting terminal Frequency for the clock that described DPLL front-locking is crossed；

When described DPLL state in which is lock-out state, inside the described DPLL described DPLL according to configuration Described recovered clock is processed by the parameter of assembly；Recovered clock after described DPLL will process is sent to described Serdes sending side.