CN2689399Y

CN2689399Y - Synchronous single-interface SRAM for realizing synchronous double-interface SRAM function

Info

Publication number: CN2689399Y
Application number: CN 200320129405
Authority: CN
Inventors: 朱哲; 金传恩
Original assignee: Vimicro Corp
Current assignee: Vimicro Corp
Priority date: 2003-12-19
Filing date: 2003-12-19
Publication date: 2005-03-30
Anticipated expiration: 2013-12-19

Abstract

The utility model relates to the field of integrated circuit, and particularly discloses a synchronous single-interface SRAM which can obtain synchronous double interface SRAM function and its obtaining method. The synchronous single-interface SRAM comprises a common synchronous single-interface static random access memory body (1), and a mapping logic circuit module (2) with multiple-input and multiple-output terminals. The mapping logic circuit module (2) comprises terminal ports for connecting to each signal terminal of the synchronous single-interface static random access memory body (1), and the mapping logic circuit module (2) also comprises terminal ports for connecting to the suitable signal terminal of the synchronous double interface static random access memory. The mapping logic circuit module (2) is mapped to be connected between the synchronous single-interface static random access memory body (1) and each signal terminal ports which are corresponding to the synchronous double interface static random access memory.

Description

A kind of synchronous single port SRAM that realizes synchronous dual-port SRAM function

Technical field

The utility model relates to integrated circuit fields, specifically, relates to a kind of synchronous single port SRAM that realizes synchronous dual-port SRAM (static RAM) function.

Background technology

Along with the development of integrated circuit fields, people are more and more higher to the requirement of chip functions.Particularly in multimedia and communication IC design, understand a large amount of integrated SRAM; and often can use dual-port SRAM; the difference of the SRAM of it and single port is; it has two cover clock/data/address ports; and can write simultaneously independently and read operation; but it is for single port SRAM, and volume almost is the twice of single port SRAM.It is a lot of when a large amount of the use chip cost to be increased.

The utility model content

The purpose of this utility model is for a kind of synchronous single port SRAM that realizes synchronous dual-port SRAM function is provided, and it can be employed under the dual-port SRAM applied environment, can reach the purpose that reduces volume again simultaneously.

To achieve these goals, the utility model provides scheme as follows:

A kind of synchronous single port static RAM that realizes synchronous twoport static random memory function, comprise a common synchronous single port static RAM body, synchronous single port static RAM of the present utility model also comprises the mapping logic circuit module of a multiple-input and multiple-output end, described mapping logic circuit module includes the port that is used to connect above-mentioned synchronous each signal end of single port static RAM body, this mapping logic circuit module also includes the port that is used to connect the signal end that synchronous twoport static RAM is suitable for simultaneously, this mapping logic circuit module shines upon connection between above-mentioned synchronous single port static RAM body and each signal port corresponding to synchronous twoport static RAM, make the two cover signal ends that connect synchronous twoport static RAM port originally be mapped on the corresponding function port of described synchronous single port static RAM body.

In the mapping logic circuit unit described in the utility model, corresponding to the piece Enable Pin CENA of synchronous twoport static RAM, mapping between the piece Enable Pin CEN on CENB and the synchronous single port static RAM, write Enable Pin WENA corresponding to synchronous twoport static RAM, WENB and synchronously write mapping between the Enable Pin WEN on the single port static RAM, read Enable Pin OENA corresponding to synchronous twoport static RAM, the mapping of reading between the Enable Pin OEN on OENB and the synchronous single port static RAM all realizes with door by one.

In the mapping logic circuit unit described in the utility model, corresponding to can being direct-connected between the clock end CLK on clock end CLKA, the CLKB of synchronous twoport static RAM and the synchronous single port static RAM; Corresponding to also can being direct-connected between the output terminal Q on output terminal QA, the QB of synchronous twoport static RAM and the synchronous single port static RAM.

In the mapping logic circuit unit described in the utility model, can be (/CENA) * DA+ (/CENB) * DB corresponding to the mapping relations expression formula between the data terminal D on data terminal DA, the DB of synchronous twoport static RAM and the synchronous single port static RAM; Corresponding to the mapping relations expression formula between the address end D on address end AA, the AB of synchronous twoport static RAM and the synchronous single port static RAM can be (/CENA) * AA+ (/CENB) * AB.

The clock frequency of synchronous single port static RAM described in the utility model can satisfy following formula: f _CLK=2x max{f _Clka, f _Clkb, f wherein _CLKBe the frequency of synchronous single port SRAM, f _Clka, f _ClkbFrequency of operation for synchronous dual-port SRAM.

Compared with prior art, advantage of the present utility model is:

The utility model can be employed under the dual-port SRAM applied environment, can reduce the volume of chip simultaneously again.

The purpose of this utility model, characteristics and advantage will be in conjunction with the embodiments, are further described with reference to accompanying drawing.

Description of drawings

Accompanying drawing 1 is that synchronous single port SRAM writes sequential chart.

Accompanying drawing 2 is that synchronous single port SRAM reads sequential chart.

Accompanying drawing 3 is synchronous dual-port SRAM read-write sequence figure.

Accompanying drawing 4 is structural drawing of device described in the utility model.

Accompanying drawing 5 is structural drawing of the specific embodiment of device described in the utility model.

Embodiment

With reference to accompanying drawing 1,2, be that synchronous single port SRAM writes, reads sequential chart.

The port signal of single port SRAM generally has data input pin D synchronously, data output end Q, and address AD DR, clock CLK, piece Enable Pin CEN writes Enable Pin WEN, reads Enable Pin OEN; The port signal of dual-port SRAM has the such signal of two covers synchronously: DA, DB, QA, QB, AA, AB, CLKA, CLKB, CENA, CENB, WENA, WENB, OENA, OENB.Sometimes write and enable and read to enable to use single line WEN/OE, wherein, tcyc is the clock period, tckl is that clock is a low level time, tckh is that clock is a high level time, and tas is address Time Created, and tah is low address hold time, tds is the input data setup time, tdh is an address input data hold time, and tws is write signal Time Created, and twh is the write signal retention time, tcs is piece enable signal Time Created, tch is the piece enable signal retention time, when writing synchronous single port SRAM, enables the CEN signal at piece, under write signal WEN (effectively low) and the effective condition of address signal ADDR1, input data DATA1 deposits in the storer corresponding address at rising edge clock; When reading synchronous single port SRAM, enable the CEN signal at piece, under read signal (when WEN is high) and the effective condition of address signal ADDR1, output data Q1 reads in the appropriate address from storer through after the access time.

With reference to accompanying drawing 3, be synchronous dual-port SRAM read-write sequence figure.

When reading synchronous dual-port SRAM, piece enables EN_B, reads to enable WE_B, when address AD DR_B signal is effective, behind clock CLK_B rising edge, through appearing on the output data line DO_B of the data stabilization of ADDR_B address after the access time; When writing synchronous dual-port SRAM, piece enables EN_A, write enable WE_A, when address signal ADDR_A is effective, behind clock CLK_A rising edge, through access time ta (greater than tcc, tcc represents the clock collision shortest time can take place) stable the existing among the SRAM of back input data DI_A.Can not rewrite the same address contents of storer by port A port B simultaneously, but can read the same address of storer by port A port B simultaneously.

With reference to accompanying drawing 4, be the structural drawing of device described in the utility model.

A kind of synchronous single port static RAM that realizes synchronous twoport static random memory function, comprise a common synchronous single port static RAM body 1, synchronous single port static RAM of the present utility model also comprises the mapping logic circuit module 2 of a multiple-input and multiple-output end, described mapping logic circuit module 2 includes the port that is used to connect above-mentioned synchronous each signal end of single port static RAM body, this mapping logic circuit module 2 also includes the port that is used to connect the signal end that synchronous twoport static RAM is suitable for simultaneously, this mapping logic circuit module 2 shines upon connection between above-mentioned synchronous single port static RAM body 1 and each signal port corresponding to synchronous twoport static RAM, make the two cover signal ends that connect synchronous twoport static RAM port originally be mapped on the corresponding function port of described synchronous single port static RAM body 1.

With reference to accompanying drawing 5, be the structural drawing of the specific embodiment of device described in the utility model.

So when realizing so synchronous dual-port SRAM, the port signal of single port SRAM is done some logical process, with DA, DB connects together through a logical circuit becomes the D of inner single port SRAM synchronously end, and the mapping relations of logical circuit described here can be (/CENA) * DA+ (/CENB) * DB; QA, QB connect together becomes the Q of inner single port SRAM synchronously end; AA, AB connects together through a logical circuit becomes the ADDR of inner single port SRAM synchronously end, the mapping relations of logical circuit described here can be (/CENA) * AA+ (/CENB) * AB, CLKA, CLKB connects together becomes the CLK of inner single port SRAM synchronously end, CENA, CENB can become the CEN of inner single port SRAM synchronously end with connecting together with door, WENA, WENB can become the WEN of inner single port SRAM synchronously end with connecting together with door, OENA, OENB can become the OEN of inner single port SRAM synchronously end with connecting together with door.

The clock frequency of synchronous single port static RAM described in the utility model can satisfy following formula: f _CLK=2x max{f _Clka, f _Clkb, f wherein _CLKBe the frequency of synchronous single port SRAM, f _Clka, f _ClkbFrequency of operation for synchronous dual-port SRAM.Because the synchronous single port SRAM of Clock Doubled carries out read or write respectively in the different cycles, can not produce the clock collision, just the data of writing into CLK_A can not be read away by thing followed CLK_B, but the data that a last CLK rising edge is write into can reading away by next CLK rising edge safety.

According to the utility model, the method for designing of single port SRAM simulation dual-port SRAM can reduce the shared chip area of SRAM really, give an example, and the synchronous dual-port SRAM of 512 words, 16 bit wides, the wide 523um of long 435.17um, area is 227594um ², the synchronous single port SRAM of 512 words, 16 bit wides, the wide 276um of long 334um, area is 92184um ², the former is 2.46 times of the latter.And the logic that increases is few, and cost is lower.The key of this method is to improve synchronous single port SRAM frequency of operation, and its port signal is added some conversion logics, carries out time-sharing operation, realizes synchronous dual-port SRAM function.

A kind of synchronous single port SRAM that realizes synchronous dual-port SRAM function described in the utility model, be not restricted to listed utilization in instructions and the embodiment, it can be applied to the field of various suitable the utility model fully, for those skilled in the art, can easily realize additional advantage and make amendment, therefore under the situation of the spirit and scope of the universal that does not deviate from claim and equivalency range and limited, the examples shown that the utility model is not limited to specific details, representational equipment and illustrates here and describe.

Claims

1, a kind of synchronous single port static RAM that realizes synchronous twoport static random memory function, comprise a common synchronous single port static RAM body (1), it is characterized in that: the mapping logic circuit module (2) that also comprises a multiple-input and multiple-output end, described mapping logic circuit module (2) includes the port that is used to connect each signal end of above-mentioned synchronous single port static RAM body (1), this mapping logic circuit module (2) also includes the port that is used to connect the signal end that synchronous twoport static RAM is suitable for simultaneously, this mapping logic circuit module (2) shines upon connection between above-mentioned synchronous single port static RAM body (1) and each signal port corresponding to synchronous twoport static RAM, make the two cover signal ends that connect synchronous twoport static RAM port originally be mapped on the corresponding function port of described synchronous single port static RAM body (1).

2, synchronous single port static RAM according to claim 1, it is characterized in that, in the described mapping logic circuit unit, corresponding to the piece Enable Pin CENA of synchronous twoport static RAM, mapping between the piece Enable Pin CEN on CENB and the synchronous single port static RAM, write Enable Pin WENA corresponding to synchronous twoport static RAM, WENB and synchronously write mapping between the Enable Pin WEN on the single port static RAM, read Enable Pin OENA corresponding to synchronous twoport static RAM, the mapping of reading between the Enable Pin OEN on OENB and the synchronous single port static RAM all realizes with door by one.

3, synchronous single port static RAM according to claim 1, it is characterized in that: in the described mapping logic circuit unit, corresponding to can being direct-connected between the clock end CLK on clock end CLKA, the CLKB of synchronous twoport static RAM and the synchronous single port static RAM; Corresponding to also can being direct-connected between the output terminal Q on output terminal QA, the QB of synchronous twoport static RAM and the synchronous single port static RAM.

4, synchronous single port static RAM according to claim 1, it is characterized in that: in the described mapping logic circuit unit, can be (/CENA) * DA+ (/CENB) * DB corresponding to the mapping relations expression formula between the data terminal D on data terminal DA, the DB of synchronous twoport static RAM and the synchronous single port static RAM; Corresponding to the mapping relations expression formula between the address end D on address end AA, the AB of synchronous twoport static RAM and the synchronous single port static RAM can be (/CENA) * AA+ (/CENB) * AB.

5, synchronous twoport static RAM according to claim 1, it is characterized in that: the clock frequency of described synchronous twoport static RAM can satisfy following formula: f _CLK=2x max{f _Clka, f _Clkb, f wherein _CLKBe the frequency of synchronous single port SRAM, f _Clka, f _ClkbFrequency of operation for synchronous dual-port SRAM.