CN2562370Y - One electron memory at ambient temperature - Google Patents

Abstract

The utility model relates to a single electron memory which comprises a silicon substrate, a silicon dioxide insulating layer on the surface of the silicon substrate, a field-effect transistor and an electrode formed on the insulating layer and having split grate structure. The utility model further comprises a single-wall carbon nanotube with quantum dot structure. The split grate of the field-effect transistor is formed by a central grate, two outer grates arranged on the two sides of the central grate and arranged in parallel, and a conducting layer positioned on the silicon dioxide insulating layer. A P-type conducting groove is doped inside the silicon substrate just below the outer grates and the central grate. An n-type source electrode and a drain electrode are formed respectively on the two sides of the conducting groove by heavily doping process. The electrode is vertical to the split grate. The two ends of the nanotube are contacted with the central grate and the electrode respectively. The utility model has split grate structure to reduce the consumption of electronic number required in the running. The single electron memory of the utility model can realize the information storage with low power consumption and super-high density at room temperature.

Description

The single-electron memory that can at room temperature work

Technical field

The utility model belongs to memory, particularly relates to a kind of novel single-electron memory and preparation method that can at room temperature work who utilizes quantum dot coulomb blockade effect design preparation.

Background technology

Electronic device has experienced from the electron tube to the transistor, from the discrete device to the development of integrated circuits.For the satisfied information that develops rapidly and the needs of computer technology, the live width of integrated circuit constantly reduces, and integrated level improves constantly.High density, high-speed, low-power consumption are several leading indicators that integrated circuit technique is pursued.The integrated circuit live width of large-scale industrialization production has at present reduced to 0.13 micron, and the laboratory can produce 10 nanometers with interior live width.Reduce the closeness that live width can proportional raising integrated circuit, but when device one or more dimensions size is reduced to nanometer scale, to such an extent as to characteristic size is less than by inelastic scattering free path that ambient temperature determined the time, quantum effect is obvious with ten minutes, caused the inefficacy of macroscopic concept, based on the device of traditional macro notion with cisco unity malfunction.Memory has occupied 40% share in whole world semi-conductor market, per 2 years of other semiconductor product beyond the memory is more of new generation, memory then is per 18 months generation, and the development of memory device is faced with device equally and further reduces the difficulty brought.With the example that develops into of dynamic memory (DRAM), the electric capacity in the memory cell can not be too little, and so whole memory will be flooded by noise to not providing abundant electronics to amplifier if this electric capacity is little, reliability that can not the guarantee information storage; Simultaneously, the number of electrons of each memory cell will be along with the further raising of memory device integrated level will become more and more littler, and it is unstable that the MOS field-effect transistor in the memory will become gradually.Therefore, seek that size is little, cost is low, speed is fast, the memory device of good stability, and the Highgrade integration of realization device, the critical problem that has become semi-conductor industry and faced.

At present, people have begun the memory device of nanometer scale is studied, and hope can be found the way of dealing with problems.In the past few years, research work mainly concentrates on the Monoelectron memory device.A kind of single electron dynamic random access memory (" nanometer technology ", Nanotechnology, 2001,12,155) with the nano wire of many tunnel junctions (MTJ) and traditional metal-oxide semiconductor fieldeffect transistor (being called for short MOSFET) structure has appearred.This Monoelectron memory device based on the MTJ/MOSFET structure mainly contains following 2 shortcomings: the size restrictions of (1) nano wire and control gate the further raising of device integrated level; (2) working temperature is very low, is generally tens K.These drawbacks limit the memory property of memory.

Summary of the invention

The purpose of this utility model be solve legacy memory and single-electron memory since the size restrictions of nano wire and control gate the shortcoming of further raising of device integrated level; Very low with this device working temperature, be generally tens K, limited the defective of the memory property of memory widely; Thereby the utility model provides a kind of coulomb blockade effect of utilizing quantum dot in the carbon nano-tube, and the single-electron memory of preparing makes the storage density of device higher, and speed is faster, finally reaches the purpose of the ultrahigh density storage of realization information.

The purpose of this utility model is achieved in that

The single-electron memory that can at room temperature work that the utility model provides comprises: as substrate, its surface is the layer of silicon dioxide insulating barrier that oxidation forms, and prepares field-effect transistor and electrode with splitting bar structure thereon with silicon; It is characterized in that: also comprise Single Walled Carbon Nanotube with quantum-dot structure; The splitting bar of described field-effect transistor is by center grid and be positioned at grid both sides, center, and two outer grid that are arranged in parallel are formed, and are formed by the conductive material layer that is positioned on the silicon dioxide insulating layer; In the corresponding silicon substrate in grid and center grid below, form p type conducting channel by mixing outside, the conducting channel both sides are source electrode and drain electrodes of a n type forming respectively through heavy doping; Described electrode is provided with the splitting bar direction is vertical, with splitting bar distance be 10 nanometers to 100 micron; Two ends with Single Walled Carbon Nanotube of quantum-dot structure contact with center grid and electrode respectively.

Also be included in center grid end one catalyst zone is set, the area of this catalyst zone is between 10 square nanometers to 500 square microns; It is Fe, Co, and Ni and alloy thereof are made.

Described silicon dioxide insulating layer thickness is the 5-500 nanometer.

Described conductive material layer can be the n type polysilicon layer that forms by mixing, and also can be metal materials such as Al or Au; Thickness of electrically conductive layer is the 5-500 nanometer.

Described electrode area is between 10 square nanometers to 1 square millimeter.

The tunnel junctions of two spacing distances less than 50 nanometers arranged on the described Single Walled Carbon Nanotube, between two tunnel junctions, form a quantum dot.

The area of described center grid is between 100 square nanometers to 100 square microns, and the distance between its China and foreign countries' grid and the center grid is between 5 nanometer to 200 nanometers;

The described tunnel junctions for preparing on Single Walled Carbon Nanotube is to utilize probe to make the local generation of Single Walled Carbon Nanotube deformation, and the carbon nanotube properties of deformation place changes and forms a tunnel junctions.

The utility model memory operate as normal has two primary conditions: (1) enough big coulomb blockade zone occurs by being applied to the bias voltage on the electrode 8, can making the Single Walled Carbon Nanotube with quantum-dot structure; (2) conducting channel in the field-effect transistor 5 will keep enough continuitys.

The utility model single-electron memory has the following advantages:

The single-electron memory that can at room temperature work of the present utility model, use Single Walled Carbon Nanotube to replace traditional MTJ, saved large-area control gate, can make full use of unique electrical, mechanics and the chemical property of carbon nano-tube, therefore the memory construction of designing has higher storage density than the single-electron memory that designs based on MTJ/MOSFET in the past, and can at room temperature realize the storage of information, so sort memory has not only solved the difficulty that legacy memory faces, also improved the performance of Monoelectron memory device; Simultaneously, the chemical inertness of Single Walled Carbon Nanotube and good toughness have determined device to have very long useful life, these advantages make the predicament that the utility model is faced in can the evolution of fine solution memory, compare with the memory of other type, have following aspect 1 in a word) can at room temperature work, 2) advantage that low in energy consumption, 3) heat dissipation capacity is little, 4) operating frequency is high.

Description of drawings

The perspective view of Fig. 1 single-electron memory of the present utility model.

The structural representation of Single Walled Carbon Nanotube in Fig. 2 single-electron memory of the present utility model.

The planar structure schematic diagram of Fig. 3 single-electron memory of the present utility model.

Fig. 4 memory does not apply the static chemical potential of the quantum dot in the Single Walled Carbon Nanotube under the situation of bias voltage and the relation of center grid and electrode Fermi level at electrode.

Fig. 5 memory applies the static chemical potential of the quantum dot in the Single Walled Carbon Nanotube under the situation of back bias voltage and the relation of center grid and electrode Fermi level at electrode, and the electron tunneling tunnel junctions enters memory cell, and memory cell (center grid 6) finally is in-Vc.

Fig. 6 memory applies the static chemical potential of the quantum dot in the Single Walled Carbon Nanotube under the situation of positive bias and the relation of center grid and electrode Fermi level at electrode, and electronics is fled from memory cell, and memory cell finally is in+Vc.

Fig. 7 single-electron memory of the present utility model utilizes the structural representation of carbon nano-tube in-situ growth technology preparation.

Indicate among the figure:

1. substrate 2. insulating barriers 3. source electrodes 4. drain electrodes

5. conducting channel 6. center grid 7. outer grid 8. electrodes

9. Single Walled Carbon Nanotube 10. tunnel junctions 11. quantum dots

12. read control line 13. catalyst zones

Embodiment

Embodiment 1:

Make the single-electron memory that can at room temperature work with reference to Fig. 1-3, its structure be elaborated below in conjunction with present embodiment and preparation method:

Select for use the p type silicon of (001) orientation to make substrate 1, utilize the dry-oxygen oxidation method, oxidizing temperature is 900 ℃, and oxidation goes out the silicon dioxide insulating layer of one 25 nanometer thickness.

Preparing the polysilicon layer of one deck 20 nanometer thickness with the method for molecular beam epitaxy (MBE), then, carry out three times and mix, is that polysilicon layer heavy doping arsenic is become the n type semiconductor layer for the first time, and doping content is 8 * 10 ¹³Cm ^-2For the second time be to inject p type boron impurities to channel region, concentration is 2 * 10 ¹²Cm ^-2, at Si/SiO ₂The following p type raceway groove 5 that forms in interface; Be to form two heavily doped n type zones by implanted dopant phosphorus on silicon substrate for the third time, doping content is 1 * 10 ¹⁵Cm ^-2, preparing the source electrode 3 of device and the distance in 4, two zones of drain electrode is 2 microns.

Utilize electronic beam photetching process and dry etching technology in polysilicon layer, prepare electrode 8, center grid 6 and outside grid 7.Center grid 6 are that 50 nanometers are wide, and 500 nanometers are long; Each outer grid 7 is that 500 nanometers are long, and 400 nanometers are wide, with the spacing of center grid 6 be 50 nanometers; Electrode 8 is that 200 nanometers are long, and 200 nanometers are wide.Electrode 8 is 300 nanometers to the distance of center grid 6.

Utilize the accurately Single Walled Carbon Nanotube 9 of diameter 7 nanometers in location, long 400 nanometers of atomic force microscope AFM, the two ends of pipe are placed on center grid 6 and the electrode 8, utilize the atomic force microscope probe technology, promptly adopt probe to contact and make it to take place local deformation with Single Walled Carbon Nanotube 9, deformation place has just formed a tunnel junctions, the spacing of preparing very near 10, two tunnel junctions of tunnel junctions of two distances like this is 9 nanometers, forms quantum dot 11 this moment in the middle of Single Walled Carbon Nanotube.At last, device is encapsulated.

Embodiment 2:

Select for use the silicon of (001) orientation to make substrate 1, utilize the dry-oxygen oxidation method, oxidizing temperature is 900 ℃, and oxidation goes out the silicon dioxide insulating layer of one 40 nanometer thickness.

Preparing the polysilicon layer of one deck 20 nanometer thickness with the method for molecular beam epitaxy (MBE), then, carry out three times and mix, is that polysilicon layer heavy doping arsenic is become the n type semiconductor layer for the first time, and doping content is 5 * 10 ¹³Cm ^-2For the second time be to inject p type boron impurities to channel region, concentration is 1 * 10 ¹²Cm ^-2, at Si/SiO ₂The following p type raceway groove 5 that forms in interface; Be to form two heavily doped n type zones by implanted dopant phosphorus on silicon substrate for the third time, doping content is 2 * 10 ¹⁵Cm ^-2, preparing the source electrode 3 of device and the distance in 4, two zones of drain electrode is 2 microns.

The catalyst zone 13 that the probe manipulation technology that utilizes atomic force microscope is made of Fe in the arranged outside of center grid 6, towards direction growth in situ Single Walled Carbon Nanotube 9 away from center grid 6, as shown in Figure 7, wherein the diameter of Single Walled Carbon Nanotube is 4 nanometers, and length is 400 nanometers.Utilizing focused ion beam is the FIB technology is prepared 30 nanometer thickness away from an end of center grid 6 in Single Walled Carbon Nanotube platinum electrode 8.

Utilizing the spacing of probe 10, two tunnel junctions of two tunnel junctions of formation in the middle of Single Walled Carbon Nanotube 9 of atomic force microscope is 5 nanometers, so just forms quantum dot 11 in the middle of Single Walled Carbon Nanotube.At last, device is encapsulated.

Embodiment 3:

Select for use the silicon of (001) orientation to make substrate 1, be used in the oxygen method for oxidation, oxidizing temperature is 1000 ℃, and oxidation goes out the silicon dioxide insulating layer of one 50 nanometer thickness.Then, carrying out twice doping, is for the first time to inject p type boron impurities to channel region, and concentration is 5 * 10 ¹²Cm ^-2, at Si/SiO ₂The following p type raceway groove 5 that forms in interface; Be to form two heavily doped n type zones by implanted dopant phosphorus on silicon substrate for the second time, doping content is 3 * 10 ¹⁵Cm ^-2, preparing the source electrode 3 of device and the distance in 4, two zones of drain electrode is 4 microns.

Utilize photoetching and dry etching, in silicon dioxide insulating layer 2, prepare the silicon dioxide table top of grid 7 outside being used for supporting, center grid 6 and electrode 8.And on table top, deposit the polysilicon of 50 nanometer thickness, and then polysilicon layer being mixed arsenic becomes the n type semiconductor layer, and doping content is 6 * 10 ¹³Cm ^-2, utilize the method for alignment photoetching and the technology of dry etching, finally prepare outer grid 7, center grid 6 and electrode 8.Center grid 6 are that 70 nanometers are wide, and 300 nanometers are long; Each outer grid 7 is that 300 nanometers are long, and 300 nanometers are wide; Electrode 9 is that 100 nanometers are long, and 100 nanometers are wide.Electrode 8 is 200 nanometers to the distance of center grid 6.

Utilize the accurately Single Walled Carbon Nanotube 9 of diameter 5 nanometers in location, long 300 nanometers of atomic force microscope AFM, the two ends of pipe are placed on center grid 6 and the electrode 8, utilize probe in the middle of Single Walled Carbon Nanotube 9, to form two tunnel junctions 10, the spacing of two tunnel junctions is 9 nanometers, so just forms quantum dot 11 in the middle of Single Walled Carbon Nanotube.At last, device is encapsulated.

Embodiment 4:

Substrate 1, outer grid 7, center grid 6, source electrode 3 and drain 4 preparation method and embodiment 3 with, adopt this moment the in-situ growth technology of Single Walled Carbon Nanotube to prepare and locate Single Walled Carbon Nanotube 9.The catalyst zone 13 that the probe manipulation technology that utilizes atomic force microscope is made of Ni in the arranged outside of center grid 6, towards direction growth in situ Single Walled Carbon Nanotube 9 away from center grid 6, as shown in Figure 7, wherein the diameter of Single Walled Carbon Nanotube is 7 nanometers, and length is 400 nanometers.Utilize focused ion beam to prepare the platinum electrode 8 of 40 nanometer thickness away from an end of center grid 6 in Single Walled Carbon Nanotube.

Utilizing the spacing of probe 10, two tunnel junctions of two tunnel junctions of formation in the middle of Single Walled Carbon Nanotube 9 of atomic force microscope is 15 nanometers, so just forms quantum dot 11 in the middle of Single Walled Carbon Nanotube.At last, device is encapsulated.

Embodiment 5:

Select for use the silicon of (001) orientation to make substrate 1, utilize the dry-oxygen oxidation method, oxidizing temperature is 900 ℃, and oxidation goes out the silicon dioxide insulating layer of one 50 nanometer thickness.Then, carrying out twice doping, is for the first time to inject p type boron impurities to channel region, and concentration is 4 * 10 ¹²Cm ^-2, at Si/SiO ₂The following p type raceway groove 5 that forms in interface; Be to form two heavily doped n type zones by implanted dopant phosphorus on silicon substrate for the second time, doping content is 2 * 10 ¹⁵Cm ^-2, preparing the source electrode 3 of device and the distance in 4, two zones of drain electrode is 4 microns.

On silicon dioxide insulating layer, deposit the aluminium of 60 nanometer thickness, utilize the method for alignment photoetching and the technology of dry etching, prepare outer grid 7 and center grid 6.Center grid 6 are that 90 nanometers are wide, and 400 nanometers are long; Each outer grid 7 is that 400 nanometers are long, and 400 nanometers are wide.

The probe manipulation technology that utilizes atomic force microscope in the arranged outside of center grid 6 by Fe, Co, the catalyst zone 13 that Ni and alloy thereof are made, towards direction growth in situ Single Walled Carbon Nanotube 9 away from center grid 6, as shown in Figure 7, wherein the diameter of Single Walled Carbon Nanotube is 6 nanometers, and length is 150 nanometers.Utilizing focused ion beam is the FIB technology is prepared 70 nanometer thickness away from an end of center grid 6 in Single Walled Carbon Nanotube platinum electrode 8.

Utilizing the spacing of probe 10, two tunnel junctions of two tunnel junctions of formation in the middle of Single Walled Carbon Nanotube 9 of atomic force microscope is 10 nanometers, so just forms quantum dot 11 in the middle of Single Walled Carbon Nanotube.At last, device is encapsulated.

Embodiment 6:

Structure and preparation method are with embodiment 5, difference is: utilize the accurately Single Walled Carbon Nanotube 9 of diameter 5 nanometers in location, long 500 nanometers of atomic force microscope AFM, the two ends of pipe are placed on center grid 6 and the electrode 8, utilize probe in the middle of Single Walled Carbon Nanotube 9, to form two tunnel junctions 10, the spacing of two tunnel junctions is 9 nanometers, so just forms quantum dot 11 in the middle of Single Walled Carbon Nanotube.At last, device is encapsulated.

Single-electron memory of the present utility model is with the theoretical foundation of coulomb blockade principle as designs.The utlity model has the storage organization (as shown in Figure 1) of quantum dot/split gate field effect transistor, and realize the storage of information by the coulomb blockade effect of the quantum dot in the Single Walled Carbon Nanotube (as shown in Figure 2).Therefore the size in coulomb blockade zone must be able to make memory cell have two tangible store statuss, and the size of tunnel junctions can be controlled the size in this nano wire coulomb blockade zone during preparation.The planar structure of this memory as shown in Figure 3, memory cell is center grid 6, suppose that electronics can only arrive the memory cell of memory outside after the match by the quantum dot in the Single Walled Carbon Nanotube, influence for fear of quantum fluctuation, the tunnelling resistance of quantum dot should be bigger than quantum resistance in the Single Walled Carbon Nanotube, quantum resistance $R_q=h/e^2\≈26\mathrm{k\Ω}$ (h is a planck constant).Quantum dot coulomb blockade peak width in the Single Walled Carbon Nanotube of supposing to prepare is 2V _cApply bias voltage to data wire, exceed the coulomb blockade zone, electronics is with the quantum dot in the tunnelling Single Walled Carbon Nanotube, till coulomb blockade takes place in system once more, according to the height difference that is applied to bias voltage on the data wire, center grid 7 (memory cell of device) form two different voltage :+V of height _c,-V _c, as Fig. 4, Fig. 5 and shown in Figure 6.Apply bias voltage for outer grid 7 by reading control line 12 this moment, makes that the raceway groove 5 of conduction is continuous, just can leak the current value that obtains different sizes between the level in the source, so just realized the storage of information.

Two kinds of stable store statuss the have reflected cell stores electronics of different numbers, therefore the voltage of center grid has two stable status, the voltage of center grid has caused the variation of channel carrier concentration, under the situation that the source drain bias remains unchanged, produced the drain current of different sizes, detected drain current and just realized reading of data.The number of electrons of center grid is few more good more, but must guarantee that two stable states have the difference that obviously can distinguish, make its storage that can realize data accurately, such memory device is as long as control electronics seldom just can be realized two phase co-conversions between the stable storage state.The voltage of memory cell is represented with following formula: $V=\frac{Q}{C_{\mathrm{\Σ}}}$

Wherein Q is the charge number in the memory cell, C _ΣTotal capacitance for memory cell.Mainly comprise two parts for this system's storage capacitance: the capacitor C of memory cell and substrate _sStray capacitance C _ElseWith C _sBe main, so C _Σ≌ C _sThe electric capacity of memory cell, the i.e. electric capacity of center grid 6: $C_s=\frac{\mathrm{\ω}}{d}.$ Wherein ε is a dielectric constant, and S is the area of center grid 7, and d is the thickness of oxidation insulating layer 2 between center grid 6 and the substrate 1.The voltage of center grid 7 when supposing electric neutrality (memory cell of memory) is 0, for cell stores the state of electric charge-ne (the extra electron number when n represents with respect to electric neutrality, can be for just, also can be for negative, the difference of symbol has been represented entering of electronics and has been flowed out), therefore can obtain: $V=\stackrel{\‾}{C_{..}}$

The voltage of center grid 6 (memory cell) is subjected to the influence of the village, often used in village names logical sequence congested areas size of quantum dot in the Single Walled Carbon Nanotube, can obtain two stable states at the edge in coulomb blockade zone, promptly | and V|=V _cSo: $\underset{\mathrm{\ϵ}}{\‾}\·\underset{{\mathrm{SV}}_c}{\‾}=1$

For a memory, e and ε can think constant, d and V in all the other four variablees _cVariable range very little, in order to reduce the electric charge of need of work, must reduce the area S of memory cell as much as possible.The utility model memory device has used the field-effect transistor of splitting bar structure, the memory cell of center grid 6 as information, can effectively reduce the area of memory cell, and the number of electrons that needs when making device work still less.

The further raising of the utility model memory stores performance need be in preparation and use the strict value of controlling several basic parameters.At first, the coulomb blockade zone of quantum dot is the bigger the better in the Single Walled Carbon Nanotube, can make two store statuss have tangible difference like this, is easy to reading of data.In order to realize such target, should reduce the spacing of two tunnel junctions 10 on the nano wire to greatest extent, because the minimizing of two tunnel junctions spacings, the electric capacity of quantum dot reduces, and the electric capacity of the size in coulomb blockade zone and quantum dot is inversely proportional to.Secondly, memory cell is the smaller the better, and promptly the area of center grid 6 is the smaller the better.It is exactly to reduce the area of memory cell that device of the present utility model uses the splitting bar purpose, and along with its physical dimension is more little, memory cell is at the edge-V in coulomb blockade zone _cWith+V _cBetween to change the charge number of required control also few more.The benefit of making is the operating frequency that has improved device like this, has reduced the power consumption of device, has also reduced the heat dissipation capacity of memory.

Claims (6)

1. the single-electron memory that can at room temperature work comprises: as substrate, its surface is the layer of silicon dioxide insulating barrier that oxidation forms, and prepares field-effect transistor and electrode with splitting bar structure thereon with silicon; It is characterized in that: also comprise Single Walled Carbon Nanotube with quantum-dot structure; The splitting bar of described field-effect transistor is by center grid and be positioned at grid both sides, center, and two outer grid that are arranged in parallel are formed, and are formed by the conductive material layer that is positioned on the silicon dioxide insulating layer; In the corresponding silicon substrate in grid and center grid below, form p type conducting channel by mixing outside, the conducting channel both sides are source electrode and drain electrodes of a n type forming respectively through heavy doping; Described electrode is provided with the splitting bar direction is vertical, with splitting bar distance be 10 nanometers to 100 micron; Two ends with Single Walled Carbon Nanotube of quantum-dot structure contact with center grid and electrode respectively.

2. according to the described single-electron memory that can at room temperature work of claim 1, it is characterized in that: described silicon dioxide insulating layer thickness is the 5-500 nanometer.

3. according to the described single-electron memory that can at room temperature work of claim 1, it is characterized in that: described conductive material layer comprises to be made by the metals such as n type polysilicon layer, Al or Au that are doping to; Thickness of electrically conductive layer is the 5-500 nanometer.

4. according to the described single-electron memory that can at room temperature work of claim 1, it is characterized in that: described electrode area is between 10 square nanometers to 1 square millimeter.

5. according to the described single-electron memory that can at room temperature work of claim 1, it is characterized in that: two tunnel junctions spacing distances on the Single Walled Carbon Nanotube are less than 50 nanometers.

6. according to the described single-electron memory that can at room temperature work of claim 1, it is characterized in that: described catalyst zone is Fe, Co, and Ni and alloy thereof are made.

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