CN1228855C - Single-electron storage designed based on coulomb damping principle and its preparing method - Google Patents
Single-electron storage designed based on coulomb damping principle and its preparing method Download PDFInfo
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- CN1228855C CN1228855C CN 02125967 CN02125967A CN1228855C CN 1228855 C CN1228855 C CN 1228855C CN 02125967 CN02125967 CN 02125967 CN 02125967 A CN02125967 A CN 02125967A CN 1228855 C CN1228855 C CN 1228855C
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Abstract
The present invention relates to a single electron storage designed based on a coulomb damping principle and a preparing method thereof. The single electron storage comprises a monocrystal silicon layer as a surface with SOI as a substrate. The structure of a carbon nanotube transistor is etched in the doped surface silicon layer. The carbon nanotube transistor comprises an electrode as a source electrode, an electrode as a drain electrode and a grid electrode. One single wall carbon nanotube is arranged on the two electrodes to form ohmic contact, wherein the grid electrode is arranged between the source electrode and the drain electrode and one side of the single wall carbon nanotube; the other carbon nanotube with the structures of more than two tunnel through joints is arranged on the grid electrode and the source electrode or the drain electrode of the carbon nanotube transistor to form the ohmic contact. The preparing method of the single electron storage is easy to operate. By controlling a plurality of dozens or even a plurality of electrons, the normal work of the single electron storage can be realized without the influence of the random background charges. Simultaneously, each storage unit of the single electron storage only has two electrode lead wires. The high integration of the single electron storage is easily realized and super-high density information storage is realized under a low power consumption condition.
Description
Technical field
The invention belongs to Monoelectron memory device, particularly relate to a kind of utilization have the sub-dot structure of volume nano wire the design preparation of coulomb blockade effect can at room temperature work have single-electron memory of low-power consumption and preparation method thereof.
Background technology
Memory has occupied 40% share in whole world semi-conductor market, per 2 years of other semiconductor product beyond the memory is more of new generation, memory then is per 18 months generation, the example that develops into dynamic memory (DRAM), Japan's live width of groove on silicon chip had reached 0.8 micron in 1988, the dynamic random access memory DRAM of 4Mb comes out, thereby has entered the integrated ULSI epoch of imperial scale; The 16Mb chip that live width in 1992 is 0.5 micron is gone into operation; The 64Mb chip that live width in 1994 is 0.35 micron is gone into operation; Soon just will realize the DRAM of 0.13 micron 4Gb.But keep the ever-reduced trend surface of yardstick facing to extremely serious challenge, be that electric capacity in the memory cell can not be too little, so whole memory will be flooded by noise to not providing abundant electronics to amplifier if this electric capacity is little, reliability that can not the guarantee information storage; Simultaneously, the number of electrons of each memory cell will become more and more hour along with the further raising of memory device integrated level, and it is unstable that the MOS field-effect transistor in the memory will become gradually.Therefore, seek that size is little, cost is low, speed is fast, the memory device of good stability, and the Highgrade integration of realization device, the critical problem that has become semi-conductor industry and faced.
At present, people have begun the memory device of nanometer scale is studied, and hope can be found the way of dealing with problems.In the past few years, research work mainly concentrates on the Monoelectron memory device, single-electron memory (" Applied Physics wall bulletin " Appl.Phys.Lett.1999 that a kind of nano wire with many tunnel junctions (MTJ) and traditional metal-oxide semiconductor fieldeffect transistor (MOSFET) structure have occurred, 74,1293), although this device has solved some problems such as power consumption of puzzlement legacy memory, but this device also exists a lot of deficiencies, mainly contain following two aspects: (1) has utilized the MTJ/MOSFET structure, limited the further raising of integrated level, this is because the size of MOSFET can not be too little, otherwise the number of electrons of work very little, to influence the stability of device, will consider also that simultaneously the MOSFET size reduces to make that preparation technology faces very big difficulty.In addition, nano wire also has two very large-area control gates, exhausts the sub-dot structure of nano wire formation volume by apply bias voltage to control gate.This shows that the storage density of memory is restricted.(2) in the device nano wire temperature of coulomb blockade effect to occur very low, cause the memory device working temperature very low, have only tens K usually.(3) memory can only be used as dynamic memory, need constantly refresh when therefore working, and has increased the power consumption of device.(4) device architecture complexity in integrated memory circuitry, need a lot of lead and lead-in wire, so device is unfavorable for integrated.This shows, the memory limitations of traditional MTJ/MOSFET structure the performance of device, if want to promote the performance of such single-electron memory, must find to have more that the storage system of high integration substitutes the MTJ/MOSFET system.
Summary of the invention
The objective of the invention is to solve the difficulty that the development of legacy memory and single-electron memory is faced, overcome existing MTJ/MOSFET structure memory, limited the defective of the further raising of integrated level; The temperature that occurs the coulomb blockade effect with nano wire in the device is very low, causes the very low defective of memory device working temperature; And the big defective of the power consumption of device; Thereby the coulomb blockade effect and the carbon nanometer transistor that provide a kind of structure letter, integrated level height, speed to utilize quantum dot in the carbon nano-tube faster, preparation has single-electron memory of low-power consumption and preparation method thereof.
The object of the present invention is achieved like this:
Single-electron memory with the coulomb blockade principle design provided by the invention comprises: with SOI is substrate, utilizes the method attenuate surface single crystal silicon of oxidation attenuate, and its thickness is 5 to 500 nanometers, and highly doped be the silicon conducting layer of n type or p type; Etch a carbon nanometer transistor structure in the silicon layer of attenuate rear surface, it comprises an electrode as source electrode, an electrode and a gate electrode as drain electrode; First carbon nano-tube is arranged on ohmic contact on source electrode and the drain electrode, and wherein gate electrode is in the centre of source electrode, drain electrode, a side of first carbon nano-tube; It is characterized in that: comprise that also another root has second carbon nano-tube of 2 above tunnel junctions structures, the second carbon carbon nano-tube is arranged on ohmic contact on gate electrode and the source electrode, or is arranged on ohmic contact on gate electrode and the drain electrode.
Described gate area in 1 square nanometers between 1 square micron.
Also be included on the outside of the inboard of drain electrode and gate electrode and place one by Fe, Co, Ni or and the catalyst zone done of alloy, again towards the direction in-situ growing carbon nano tube of source electrode, the other end of the carbon nano-tube that this grows out contacts with source electrode, or to utilize focused ion beam be the FIB technology at this end of carbon nano-tube and source electrode place deposition platinum, makes it have good electrical contact.
Distance between described source electrode and the drain electrode is 5 nanometers to 1 micron.
Described tunnel junctions distance is less than 20 nanometers.
Also comprise a described memory cell,, the memory cell two ends of respective number are linked to each other with bit line with word line respectively, form storage matrix, the storage of realization multidigit binary data according to the requirement of storage number of bits and memory capacity with two ends.
The preparation method of the single-electron memory with the coulomb blockade principle design of the present invention comprises the steps:
(1) with SOI is substrate, at first adopt steam oxidation technology, float the method attenuate monocrystalline silicon layer of the oxide layer of growing again with HF buffered etch liquid, the thickness that makes surface silicon layer is between 5 to 500 nanometers, and monocrystalline silicon layer carried out the doping of conventional method, form highly doped p type or n type silicon conducting layer;
(2) prepare the source, leak two electrodes and gate electrode by conventional semiconductor technology in the monocrystalline silicon layer after doping, gate electrode in the source, the centre of leaking two electrodes; Then with the carbon nano-tube in atomic force microscope location on two electrodes and gate electrode, make the electrode of itself and source and leakage have good Ohmic contact;
(3) locate another root carbon nano-tube with atomic force microscope and be arranged on source electrode or drain electrode and the gate electrode, source electrode or drain electrode and gate electrode are linked together; Perhaps also be included in and place catalyst zone (Fe, Co, Ni or and alloy make) on the outside of the inboard of drain electrode and gate electrode, towards the direction of source electrode, in-situ growing carbon nano tube; The other end and the source electrode of the carbon nano-tube that grows out come in contact, if there is not excellent contact, need utilize focused ion beam is that the FIB technology deposits platinum at this end of carbon nano-tube and source electrode place, makes it have good electrical contact; Utilize the scan-probe technology to form 2 above tunnel junctions by local deformation then on this root carbon nano-tube, the spacing of facing tunnel junctions mutually is less than 20 nanometers; Constituted a single-electron memory unit with two ends;
(5) device is encapsulated the preparation of just having finished memory of the present invention.
Also comprise and the two ends of a plurality of memory cell can be linked to each other with bit line with word line respectively, can form the storage matrix of multidigit, realize the storage of multidigit binary data.
The invention belongs to single-electron memory, with the theoretical foundation of coulomb blockade principle as designs.The present invention has the storage organization of carbon nano-tube single-electronic transistor/carbon nanotube field-effect transistor, and realizes the storage of information by the coulomb blockade effect of quantum dot.Therefore the size in coulomb blockade zone must be able to make memory cell have two tangible store statuss, and the electric capacity of each quantum dot has determined the size in coulomb blockade zone.Suppose that electronics can only arrive the memory cell of memory outside after the match by the quantum dot in the carbon nano-tube, for fear of the influence of quantum fluctuation, the tunnelling resistance of quantum dot should be bigger than quantum resistance, the quantum resistance R
q=h/e
2≈ 26k Ω (h is a planck constant).Suppose that the coulomb blockade peak width is 2V
c, apply bias voltage to source electrode, exceed the coulomb blockade zone, electronics is with quantum dot in the tunnelling carbon nano-tube, till system once more coulomb blockade takes place,, just form two different voltage :+V of height on the carbon nanometer transistor grid according to the height difference that is applied to bias voltage on the source electrode
c,-V
cTwo kinds of stable store statuss have reflected that grid has stored the electronics of different numbers, for operating frequency and the reduction power consumption that improves device, wish that this number of electrons is few more good more, but must guarantee that two stable states have the difference that obviously can distinguish, promptly can realize reading of data, such memory device is as long as control electronics seldom just can be realized two phase co-conversions between the stable storage state.The voltage of grid is represented with following formula:
Wherein Q is a charge stored number in the gate electrode, C
∑Total capacitance for grid.Mainly comprise two parts for this system capacitance: the capacitor C of memory cell and substrate
sStray capacitance C
tThe voltage of grid is 0 when supposing electric neutrality, has stored the state (the extra electron number when n represents with respect to electric neutrality can be for just, also can be for negative, the difference of symbol has been represented entering of electronics and flowed out) of electric charge-ne for grid, therefore can obtain:
Thickness of oxide layer is very thin, C in the system
s〉=C
1,
ε is a dielectric constant, and S is the area of memory cell, and d is a thickness of oxide layer between memory cell and the substrate.The voltage of grid is subjected to the influence of coulomb blockade area size, and its two stable states are in the edge in coulomb blockade zone, promptly | and V|=V
cSo:
For a memory, e and ε can think constant, d and V in all the other four variablees
cVariable range very little, in order to reduce the electric charge of need of work, must reduce the area S of gate electrode as much as possible.The memory cell of this device is the grid of carbon nano-tube, and it is very little that area can be done, so electric charge seldom just can cause change in voltage very big on the gate electrode.
The further raising of memory stores performance of the present invention need be in preparation and use the strict value of controlling several basic parameters.At first, the coulomb blockade zone of the sub-dot structure of volume is the bigger the better in the carbon nano-tube, can make two store statuss have tangible difference like this, is easy to reading of data.In order to realize such target, should reduce the spacing of tunnel junctions on the nano wire to greatest extent, because the minimizing of two tunnel junctions spacings, the electric capacity of quantum dot reduces, and the electric capacity of the size in coulomb blockade zone and quantum dot is inversely proportional to.Secondly, memory cell is the smaller the better.Promptly use little capacitive charge storage, needed charge number when the benefit of this spline structure is to have reduced memory operation, promptly gate electrode is at the edge-V of coulomb blockade
cWith+V
cBetween change required control charge number seldom.Therefore the size that reduces gate electrode has improved the operating frequency of device, has reduced the power consumption of device, has also reduced the heat dissipation capacity of memory.At last, increase electric capacity between first carbon nano-tube and the gate electrode as far as possible.For given quantum dot coulomb blockade zone 2V
cSize be invariable.Capacitor C between first carbon nano-tube and the grid
tFor: C
t=2 π ε L/log (2h/r)
Wherein ε is a dielectric constant, and L is the width of gate electrode, and r is the diameter of Single Walled Carbon Nanotube, and h is the distance between first carbon nano-tube and the gate electrode.Voltage changes 2V
cThe relative increment that causes electric charge in the carbon nano-tube is:
ΔQ/Q∝2V
cC
t/L＝4πεV
c/log/(2h/r)
Wherein Q is the charge carrier total electrical charge number in the carbon nano-tube.Δ Q/Q is big more, and promptly the change in concentration of charge carrier is big more in the carbon nano-tube, and grid voltage changes the electric current that causes and changes also more greatly.In order to improve the accuracy of memory read process, the raising Δ Q/Q of necessary maximum possible.For given quantum dot, V
cBe constant,, need reduce h, increase r in order to promote Δ Q/Q.This shows, need to reduce the distance of the gate electrode and first carbon nano-tube in the preparation process, use the bigger Single Walled Carbon Nanotube of diameter.In order to make the memory property optimization of device, have to take all factors into consideration the various factors that influences memory, because the lifting of a memory property index is a cost to sacrifice other performance often.
Memory operate as normal of the present invention has two primary conditions: the coulomb blockade zone can appear in quantum dot in (1) carbon nano-tube, and it is enough big that want in this zone; (2) memory cell has two stable store statuss as the grid of carbon nanometer transistor, and it is enough big that the difference of the drain current of these two stable status correspondences is wanted, with the assurance memory data and the information that deposit in of read-out system exactly.
The invention has the advantages that: because this device has been abandoned traditional MOSFET structure, adopted the carbon nanometer transistor structure, can make full use of unique electrical, mechanics and the chemical property of carbon nano-tube, therefore the memory construction of designing has higher storage density than the single-electron memory that designs based on MTJ/MOSFET in the past, neither be subjected to the influence of random background charge, can under higher temperature, work again.Simultaneously, the chemical inertness of carbon nano-tube and good toughness have determined device to have very long useful life.In addition, this single-electron memory has saved the large-area grid (being used for forming the sub-dot structure of volume in the nano wire) that exhaust than the more simple structure that has of the single-electron memory that designed in the past, and each memory cell has only two pins, so device is easy to control, is easy to integrated.These advantages make the predicament that the present invention is faced in can the evolution of fine solution memory, compare with the memory of other type, have many-sided advantage.
Bit of traditional dynamic random access memory (DRAM) storage needs a transistor and an electric capacity, and its storage density is subject to the size of storage capacitance, and this is that operation principle by DRAM causes.And bit of static random access memory SRAM storage needs 4 to 6 transistors.This shows that single electron of the present invention is stored at random and can be had higher storage density, this is because do not have traditional transistor in the device, has just avoided yardstick further to reduce the difficulty of being brought, as electric leakage of the grid etc.This dynamic random access memory based on carbon nano-tube has very low power consumption simultaneously, it does not need to control a large amount of electronics and realizes variation between the on off state of memory as traditional DRAM, single-electron memory of the present invention only need be controlled several even tens electronics just can be realized the conversion of device between two states, so the heat dissipation capacity of sort memory is low-down, this has just guaranteed that the raising of device integrated level can not be subjected to the restriction of heat dissipation problem, compares with traditional memory to have remarkable advantages.Use the Monoelectron memory device of such low-power consumption can solve the energy crisis that the development of conventional dynamic random asccess memory is faced.
Traditional metal-oxide semiconductor fieldeffect transistor (MOSFET) need mix at source and drain areas and form source electrode and drain electrode, so that MOSFET can not be done is very little, therefore exist MOSFET to limit the raising of device integrated level to a great extent in the single-electron memory, can not show the advantage of single-electron memory to greatest extent.Single-electron memory of the present invention utilizes very little that carbon nanometer transistor then can make size.Because memory provided by the invention can utilize carbon nano-tube as the lead-in wire on each electrode, so line capacitance can be very little, and the RC time is also very little, and the device operating frequency after integrated is very high, can reach more than the 100GHz.
In a word, single-electron memory of the present invention has the following advantages than legacy memory: 1) simple in structure, 2) be easy to integrated, 3) operating frequency height, 4) storage density is big, and 5) low in energy consumption, 6) heat dissipation capacity is little, 7) being subjected to the influence of random background charge hardly, 8) working temperature is room temperature.
Description of drawings
The structural representation of Fig. 1 memory device of the present invention.
The carbon nano tube structure schematic diagram that has many quantum dots in Fig. 2 memory device of the present invention.
Fig. 3 is with the memory circuit schematic diagram of Monoelectron memory device of the present invention.
Fig. 4 memory of the present invention does not apply under the situation of bias voltage the static chemical potential of quantum dot and the relation between gate electrode and the source electrode Fermi level in second carbon nano-tube at source electrode.
Fig. 5 memory of the present invention applies under the situation of back bias voltage the static chemical potential of quantum dot and the relation between gate electrode and the source electrode Fermi level in second carbon nano-tube at source electrode, electronics enters gate electrode by source electrode, and gate electrode finally is in-V
c
Fig. 6 memory of the present invention applies under the situation of positive bias the static chemical potential of quantum dot and the relation between gate electrode and the source electrode Fermi level in second carbon nano-tube at source electrode, and electronics is fled from gate electrode, and gate electrode finally is in+V
c
Fig. 7 carbon nanometer transistor drain current ideally is with the change curve of grid voltage.
Fig. 8 memory of the present invention write with readout in the relation of each associated voltage.
Fig. 9 the present invention utilizes the schematic diagram of the memory construction of carbon nano-tube in-situ growth technology preparation.
Indicate among the figure:
1.SOI substrate 2. buried oxide 3. source electrodes 4. drain electrodes
5. gate electrode 6. first carbon nano-tube 7. second carbon nano-tube 8. tunnel junctions
9. memory cell 11. word lines in quantum dot 10. memory circuits
12. bit line 13. catalyst zones
Embodiment
Embodiment 1:
Make a single-electron memory with the coulomb blockade principle design by Fig. 1 and Fig. 3, and structure of the present invention be described in detail in conjunction with manufacture method:
Choose commercially available SOI as backing material 1, it utilizes oxygen to inject the isolation technology preparation, utilizes dry-oxygen oxidation attenuate surface single crystal silicon, and its parameter is as follows: material crystal orientation＜100 〉, P type, resistivity are 3 Ω cm; Silicon layer thickness is 40 nanometers, and the silicon dioxide layer thickness is 200 nanometers.Form n type conductive layer by implanted dopant arsenic in the monocrystalline silicon layer behind attenuate, doping content is 5 * 10
13Cm
-2, form the monocrystalline silicon layer that conducts electricity; Utilize electronic beam photetching process and dry etching technology to prepare source electrode 3, drain electrode 4 and gate electrode 5.Source electrode 3 and drain electrode 4 all are 40 nanometer thickness, and 50 nanometers are wide, and 50 nanometers are long, and two parts spacing is 300 nanometers; Gate electrode 5 is 40 nanometer thickness, and 30 nanometers are wide, and 200 nanometers are long, and gate electrode 5 all is 50 nanometers with the spacing of source electrode 3 and drain electrode 4, and etching depth is 50 nanometers, promptly will etch into buried oxide 2 places.
Utilize the accurately Single Walled Carbon Nanotube 6 of diameter 3 nanometers in location, long 500 nanometers of atomic force microscope AFM, its two ends are contacted with drain electrode 4 with source electrode 3.Locating diameter then is that 3 nanometers, length are another root Single Walled Carbon Nanotube 7 of 80 nanometers, one end of Single Walled Carbon Nanotube 7 is on the gate electrode 5, on the other end place source electrode 3, or an end of Single Walled Carbon Nanotube 7 is on the gate electrode 5, on the other end place drain electrode 4.In addition, utilize the probe technique of atomic force microscope to make the part of carbon nano-tube 7 that deformation take place again, form 3 tunnel junctions 8 of distance 20 nanometers, between two tunnel junctions of facing mutually, just formed quantum dot 9 like this; At last device is carried out the routine encapsulation.
Embodiment 2:
The preparation method of source electrode 3, drain electrode 4 and gate electrode 5 and embodiment 1 with, the surface silicon bed thickness behind the attenuate of different is described SOI is 5 or 500 nanometers; Distance between described source electrode and the drain electrode is 5 nanometers or 1 micron; Described gate area in 1 square nanometers between 1 square micron.And on the outside of the inboard of drain electrode 4 and gate electrode 5, place catalyst zone 13, this catalyst zone 13 usefulness Fe, Co, Ni or and alloy make, as shown in Figure 9, towards the direction in-situ growing carbon nano tube of source electrode 3, the other end of the carbon nano-tube that grows out and source electrode 3 come in contact.In addition, utilize the probe technique of atomic force microscope to make the part of carbon nano-tube 7 that deformation take place again, form the tunnel junctions 8 of distance 10 nanometers, between two tunnel junctions, just formed quantum dot 9 like this.At last device is encapsulated.
When not having excellent contact, need utilize focused ion beam is that the FIB technology deposits platinum at this end of carbon nano-tube and source electrode contact position, makes it have good electrical contact.
The operation principle of the single-electron memory with the coulomb blockade principle design of the present invention is described as follows:
According to prepared its stereochemical structure of device of above embodiment as shown in Figure 1, mainly contain two elements: have the Single Walled Carbon Nanotube of the sub-dot structure of volume, as shown in Figure 2; Carbon nanometer transistor.Fig. 3 has provided the memory circuit of this Monoelectron memory device, just can realize the read and write of data by word line 11 and bit line 12.The present invention realizes the storage of information by the coulomb blockade effect of the sub-dot structure of volume in the carbon nano-tube 7.Quantum dot coulomb blockade peak width in the carbon nano-tube of supposing to prepare is 2V
c, apply bias voltage for source electrode 3, exceed the coulomb blockade zone, electronics is with the quantum dot in the tunnelling carbon nano-tube, till system once more coulomb blockade took place, according to the height difference that is applied to bias voltage on the source electrode, gate electrode 5 formed two different voltage :+V of height
c,-V
c, Fig. 4 is the situation of no extra electron storage in the device grids electrode 5, can suppose that the gate electrode 5 of this moment and the voltage of source electrode 3 are 0.Fig. 5 exceeds the state in the coulomb blockade zone of quantum dot 9 in second carbon nano-tube 7 for the bias voltage on the source electrode 3, this moment, electronics entered gate electrode 5 by source electrode, nano wire can be approximated to one section resistance, final result makes N electronics arrive gate electrode, makes system reach the edge of coulomb blockade.If the voltage of source electrode 3 is removed, because the existence of coulomb blockade makes gate electrode 5 be stabilized in-V
cState.In like manner, on source electrode, apply+V
cVoltage (as Fig. 6) shown in, electronics will flow to source electrode 3 by gate electrode 5, final gate electrode 5 reaches+V
cStable state.Can obtain the current values of different sizes this moment between the source electrode 3 of carbon nanometer transistor and drain electrode 4, so just realized the storage of information.
Another essential part of this memory is a carbon nanometer transistor.Its grid can be used for changing the carrier concentration in first carbon nano-tube 6, so under the constant situation of source-drain voltage, grid can be used for controlling the electric current in first carbon nano-tube 6.Fig. 7 has provided the relation between a transistorized source-drain current of typical Single Walled Carbon Nanotube and the grid voltage, because the existence in nano wire coulomb blockade zone, makes gate electrode 5 at+V
cWith-V
cThe place obtains two stable store statuss, and the charge carrier in the carbon nano-tube is the hole, so-V
cThe drain current of place's correspondence is bigger.Traditional metal-oxide semiconductor fieldeffect transistor (MOSFET) need mix at source and drain areas and form source electrode and drain electrode, so that MOSFET can not be done is very little, therefore exist MOSFET to limit the raising of device integrated level to a great extent in the single-electron memory, can not show the advantage of single-electron memory to greatest extent.Memory of the present invention utilizes very little that carbon nanometer transistor then can make size, and the reducing of each memory cell size can further be improved storage density.
Single-electron memory of the present invention control is very simple with respect to other memory, gets final product because of this device only need apply bias voltage at source electrode and drain electrode, so that this device is beneficial to very much is integrated.The current potential of supposing drain electrode is 0, and then there is a coulomb zone in the source electrode voltage V of memory device, can control the exchange of electronics between source electrode 3 and the gate electrode 5.Data are being write fashionablely, write voltage | ± V
W|＞V
C, exceeded the coulomb blockade zone of second carbon nano-tube this moment, can realize the control to gate electrode 5 number of electrons, ± V
WCorresponding two kinds of different stable states; During sense data, source electrode is read voltage | V
R|＜V
CThis moment, this voltage can not exert an influence to the number of electrons on the gate electrode, added a bias voltage between just leaking to the source of carbon nanometer transistor, the electric current between leak in the measurement source just can be determined the store status of grid, and the state of read-write voltage as shown in Figure 8.
Claims (11)
1. single-electron memory with the coulomb blockade principle design, comprising: be substrate with SOI, the surface is a monocrystalline silicon layer; Etch a carbon nanometer transistor structure in the surface silicon layer after doping, it comprises an electrode as source electrode, an electrode and a gate electrode as drain electrode, first carbon nano-tube is arranged on ohmic contact on source electrode and the drain electrode, wherein gate electrode is in the centre of source electrode, drain electrode, a side of first carbon nano-tube; It is characterized in that: comprise that also another root has second carbon nano-tube of 2 above tunnel junctions structures, the second carbon carbon nano-tube is arranged on ohmic contact on gate electrode and the source electrode, or is arranged on ohmic contact on gate electrode and the drain electrode.
2. by the described single-electron memory of claim 1 with the coulomb blockade principle design, it is characterized in that: also be included on the outside of the inboard of drain electrode and gate electrode and place a catalyst zone, again towards the direction of source electrode, growth in situ first and second carbon nano-tube, the other end of the carbon nano-tube that this grows out contacts with source electrode.
3. by the described single-electron memory of claim 2, it is characterized in that: also be included in first and second carbon nano-tube and source electrode contact position deposition platinum with the coulomb blockade principle design.
4. by the described single-electron memory with the coulomb blockade principle design of claim 3, it is characterized in that: described catalyst zone is by Fe, Co, and Ni and alloy thereof are done.
5. by claim 1 or 2 described single-electron memories, it is characterized in that: surface silicon bed thickness 5 to 500 nanometers behind the attenuate of described SOI with the coulomb blockade principle design.
6. by claim 1 or 2 described single-electron memories with the coulomb blockade principle design, it is characterized in that: the distance between described source electrode and the drain electrode is 5 nanometers to 1 micron.
7. by claim 1 or 2 described single-electron memories, it is characterized in that with the coulomb blockade principle design: described gate area in 1 square nanometers between 1 square micron.
8. by the single-electron memory of claim 1 or 2 described low-power consumption, it is characterized in that: described tunnel junctions distance is less than 20 nanometers; Have 2 tunnel junctions at least on the carbon nano-tube.
9. method for preparing the described single-electron memory with the coulomb blockade principle design of claim 1 is characterized in that: may further comprise the steps:
(1) with SOI is substrate, at first adopt steam oxidation technology, float the method attenuate monocrystalline silicon layer of the oxide layer of growing again with HF buffered etch liquid, the thickness that makes surface silicon layer is between 5 to 500 nanometers, and monocrystalline silicon layer carried out the doping of conventional method, form highly doped p type or n type silicon conducting layer;
(2) in the SOI surface single crystal silicon that step 1 obtains mixing, prepare the source, leak two electrodes and gate electrode by conventional semiconductor technology, gate electrode in the source, the centre of leaking two electrodes; Locate first carbon nano-tube on drain electrode and source electrode with atomic force microscope then, make itself and source electrode and drain electrode have good Ohmic contact;
(3) locating second carbon nano-tube with atomic force microscope is arranged on gate electrode and the source electrode, source electrode or gate electrode are linked together, utilize the scan-probe technology to form 2 above tunnel junctions by local deformation then on this root carbon nano-tube, tunnel junctions knot spacing is less than 20 nanometers;
(4) conventional method encapsulates device.
10. by the method for the described preparation of claim 9 with the single-electron memory of coulomb blockade principle design, it is characterized in that: also be included on the outside of the inboard of drain electrode and gate electrode and place catalyst zone, towards the direction of source electrode, growth in situ first and second carbon nano-tube; The other end and the source electrode of the carbon nano-tube that grows out come in contact.
11., it is characterized in that: also comprise and utilize focused ion beam at first and second carbon nano-tube and source electrode junction deposition platinum by the method for the described preparation of claim 10 with the single-electron memory of coulomb blockade principle design.
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| CN100420033C (en) * | 2004-10-28 | 2008-09-17 | 鸿富锦精密工业（深圳）有限公司 | Field effect transistor |
| CN100466204C (en) * | 2006-06-07 | 2009-03-04 | 中国科学院微电子研究所 | A making method for nano coulomb structure |
| CN111880764B (en) * | 2020-08-05 | 2024-04-16 | 中国航天科工集团第二研究院 | Quantum random number generation method, device and generator based on coulomb blockade effect |
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2002
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