CN2558011Y - Asychronous collection and superposition device for multiplex high speed analog signal - Google Patents
Asychronous collection and superposition device for multiplex high speed analog signal Download PDFInfo
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- CN2558011Y CN2558011Y CN02265505U CN02265505U CN2558011Y CN 2558011 Y CN2558011 Y CN 2558011Y CN 02265505 U CN02265505 U CN 02265505U CN 02265505 U CN02265505 U CN 02265505U CN 2558011 Y CN2558011 Y CN 2558011Y
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Abstract
The utility model discloses a multi-way high-speed analog signal asynchronous collection and superimposition device. The utility model is composed of a signal coupled circuit; an analog-digital sampling converter; a first level asynchronous FIFO memory which is connected with the analog-digital sampling converter; a front end programmable control chip which is respectively connected with the first asynchronous FIFO memory and the analog-digital sampling converter; a back end programmable control chip which is connected with the front end programmable control chip; a programmable interface control chip which is respectively connected with the front end and the back end programmable control chips and forms a digital filter of the superimposed data and a local bus interface; and a second level asynchronous FIFO memory which is connected with the back end programmable control chip and the programmable interface control chip. The utility model can meet the asynchronous data acquisition and superimposition of more than tens of signal channels and has the advantages of flexible assembly and high precision.
Description
Technical field
The utility model belongs to a kind of data collector, the especially a kind of asynchronous collecting of multipath high-speed simulating signal and device of superposition of being used for.
Technical background
The asynchronous collecting and the superposition device of existing multipath high-speed simulating signal, generally by signal coupling circuit, analog to digital conversion circuit, data superposition pipeline, read-write sequential, interface circuit and input signal analog delay line taking place forms, it generally is the method that adopts analog delay line, finish by the phase place that postpones between the varying input signal, to realize the collection of related data.
But owing to be subjected to the restriction of delay line tap and switch selection, the input way of signal can be subjected to very big restriction, also can bring the input signal distortion in various degree and the distortion of waveform simultaneously, thereby influence measuring accuracy; In some use occasion, as adopt in the equipment of phased-array technique, system need extract tens road signals for system acquisition from the input signal of as many as roads up to a hundred, if adopt conventional apparatus, because lag line is selected the increase of tap and selector switch, the loaded down with trivial details and system and device in the time of can bringing realization to multiplexed signal sampling huge can't be realized sometimes, but the quantity that reduces input signal will influence measuring accuracy, and the distortion of inhibit signal and distortion also can reduce the measuring accuracy of system.
Summary of the invention
The utility model technical issues that need to address provide a kind of multipath high-speed simulating signal asynchronous collecting and superposition device, and it can satisfy the asynchronous collecting of the signalling channel more than tens of roads and superposition, and combination is flexible, precision is high.
For solving the problems of the technologies described above, the technical solution adopted in the utility model is:
A kind of multipath high-speed simulating signal asynchronous collecting and superposition device, it includes signal coupling circuit and modulus sample conversion device, and this device also includes
The first order asynchronous FIFO memory that is connected with modulus sample conversion device;
Be connected with first order asynchronous FIFO memory and modulus sample conversion device respectively and sampling time sequence controlled and formed the front end programmable control chip of first order data superposition pipeline;
That be connected with the front end programmable control chip and form the rear end programmable control chip of second level data superposition pipeline, sequential control circuit and read-write sequence circuit;
That be connected with the front and back ends programmable control chip respectively and form the digital filtering of data behind the superposition and the programmable interface control chip of local bus interface;
The second level asynchronous FIFO memory that is connected with the programmable interface control chip with above-mentioned rear end programmable control chip.
Described front and back ends programmable control chip is the XC2S100-5PQ208C field programmable gate array chip of company of match SEL; Described first and second grade asynchronous FIFO memory is made up of the products C Y7C466A-10JC of company of Cypress Semiconductor Co., Ltd; Described programmable interface control chip is the QL5232 chip of the U.S. quick logic company; Described modulus sample conversion device adopts the AD9057-80 chip of Analog Devices Inc; The unity gain amplifier that described signal coupling circuit is made of the AD8041 operational amplifier of Analog Devices Inc; Front end programmable control chip, rear end programmable control chip are connected with the formula storer, and this formula storer is the XC18V01 chip of company of match SEL.
The utility model is for fear of the defective of conventional art, having proposed a kind ofly has high degree of flexibility, high-speed data acquisition treatment technology capable of being combined to solve multiple signals asynchronous collecting and superposition, promptly by controlling, adjust the phase differential between each road sampling pulse in the sampling period, distinguish the store sampled data in first and second grade asynchronous FIFO memory, unify to read related data again and carry out computing.
Owing to taked above-mentioned scheme, the advantage that the utility model is compared with prior art had is:
Because the programmable control chip that has adopted first and second grade asynchronous FIFO memory and sampling time sequence is controlled, realization is to the asynchronous data collection of multipath high-speed signal, and can dispose modulus sample conversion device, asynchronous FIFO memory and the programmable control chip of respective numbers easily according to the number of required acquired signal passage, improved the number of active lanes that needs the simulating signal of collection greatly, and apparatus structure is compact simple, combination is flexible, the precision height.
Description of drawings
Below in conjunction with the drawings and specific embodiments the utility model is described in further detail:
Fig. 1 is the structured flowchart of the utility model multipath high-speed simulating signal asynchronous collecting and superposition device;
Fig. 2 is the system schematic that the utility model expands to 32 road signal input channels;
Fig. 3 is the circuit catenation principle figure that the utility model expands to 32 road signal input channels;
Fig. 4 is that the utility model carries out image data superposition synoptic diagram.
Embodiment
As shown in Figure 1, the utility model multipath high-speed simulating signal asynchronous collecting and superposition device include signal coupling circuit 1 and modulus sample conversion device 2, and this device also includes
The first order asynchronous FIFO memory 3 that is connected with modulus sample conversion device 2;
Be connected with first order asynchronous FIFO memory 3 and modulus sample conversion device 2 respectively and sampling time sequence controlled and formed the front end programmable control chip 4 of first order data superposition pipeline;
That be connected with front end programmable control chip 4 and form the rear end programmable control chip 5 of second level data superposition pipeline, sequential control circuit and read-write sequence circuit;
That be connected with the front and back ends programmable control chip respectively and form the digital filtering of data behind the superposition and the programmable interface control chip 7 of local bus interface;
The second level asynchronous FIFO memory 6 that is connected with programmable interface control chip 7 with above-mentioned rear end programmable control chip 5.
Asynchronous collecting herein be meant to correlativity is arranged, the multiple signals on are not at one time gathered, are handled.When specific implementation, consider the size of printed board and the convenience of connection, be an elementary cell generally with 8 road input signals, following description is based on this promptly.
As shown in Figures 2 and 3, the utility model expanded to 32 road high speed analog signals are carried out asynchronous collecting and superposition, in Fig. 2, four passages (or claiming elementary cell) A/D
0～A/D
7Adopt 32 modulus sample conversion devices 2 altogether; Four passage F
0～F
7, be 32 first order asynchronous FIFO memories 3 altogether; Each passage a slice front end programmable control chip 4 is front end programmable control chip X
00, X
01, X
02, X
03, they are except that address decoding part difference, and other internal circuit principle of work is identical; Rear end programmable control chip 5 is finished the distribution of data superposition and sequential; F
10, F
11Be 2 second level asynchronous FIFO memories 6, F
10, F
11Read signal provide by programmable control chip 7; Programmable interface control chip 7 is at a high speed extensive programmed logical module, be provided with pci interface (Peripheral Component Interconnect interface) controller in it, form read command, the weighted mean filtration module of second level asynchronous FIFO memory data by programmed logical module, realize the exchanges data of this device and computing machine by pci interface.
In Fig. 3, signal coupling circuit 1 of the present utility model is by the AD8041 operational amplifier component unit gain amplifier of AD company (Analog Devices Inc), as the driving of back level modulus sample conversion device 2, its output pin Ao is connected with the input end Ain of rear end corresponding modulus sample conversion device 2.
Modulus sample conversion device 2 adopts the AD9057 chip of AD company, (i can be 0,1,2 and 3 for ENCODE pin and front end programmable control chip 4 corresponding WR_Fi, the front end programmable chip of representative on different passages) signal pins is connected, the FPDP Do[0 of AD9057,7] connect the FPDP Di[0 of the first order asynchronous FIFO memory of rear end with sequence number, 7].
First order asynchronous FIFO memory 3 is made of the CY7C466A-10JC chip of CYPRESS company (semiconductor company of Sai Pulasi company), and as the impact damper of data; Also (i can be 0,1,2 and 3 to WR write signal pin separately with front end programmable control chip 4 corresponding WR_Fi, the front end programmable control chip of representative on different passages) signal pins is connected, control signal is provided by front end programmable control chip 4, hence one can see that, and the write signal that the sampling of modulus sample conversion device AD9057 starts sequential and first order asynchronous FIFO memory 3 is the same signal that is produced by front end programmable control chip 4; The read signal of the RD separately pin of the first order asynchronous FIFO memory 3 in a certain passage is connected to front end programmable control chip 4 corresponding RD_Fi jointly, and (i can be 0,1,2 and 3, representative is at the front end programmable control chip on the different passages) on, its public read signal is produced by rear end programmable control chip 5, is sent to first order asynchronous FIFO memory 3 through front end programmable control chip 4; All herein CY7C466A-10JC chip write signals are independently, and read signal is identical; 8 CY7C466A-10JC chip data output port Q[0,7] meet the data-in port IN_A[0 of corresponding front end programmable control chip 4 respectively with sequence number, 7] to IN_H[0,7].
Define in the first order asynchronous FIFO memory of each elementary cell 3 F
4The data input pin of sheet is data D8 position, the D8_OUT pin that connects front end programmable control chip 4, utilizing this is D8_IN pin that data Q8 position send into front end programmable control chip 4 again as raw data by the data output pin with the zone bit that front end programmable control chip 4 produces, as the diagnostic criterium of system.
The quantity of front end programmable control chip 4 can decide according to the way of system simulation input signal, is an elementary cell with 8 road input signals generally, and then the front end programmable control chip is a slice; Input signal is 32 the tunnel, then is four elementary cells, and the front end programmable control chip needs four.
Front end programmable control chip 4, rear end programmable control chip 5 adopt the XC2S100-5PQ208C field programmable gate array chip of XILINX company (Sai Lingsi company), and the mode of operation of front end programmable control chip, rear end programmable control chip is chosen as the serial holotype.
Front end programmable control chip 4 is used for first order data superposition pipeline is controlled and formed to sampling time sequence, and rear end programmable control chip 5 then forms second level data superposition pipeline, sequential control circuit, read-write sequence circuit; And the data superposition adopts pipeline work.
The digital filtering and the pci interface circuit of data behind the programmable interface control chip 7 realization superpositions, this chip is the QL5232 chip of QUICKLOGIC company (U.S. quick logic company), it is at a high speed extensive programmed logical module, its built-in pci interface controller is realized the exchanges data of this device and computing machine by pci interface.
Between programmable control chip 7 and rear end programmable control chip 5, also be provided with two second level asynchronous FIFO memories 6, these two storage chips walk abreast and connect into 14 storer, its data port D[0,13], Q[0,13] respectively the corresponding data mouth with rear end programmable control chip and QL5232 chip be connected; And the write signal pin WR of this storer is connected on the write signal pin WR_F of rear end programmable control chip jointly, and read signal pin RD is connected on the read signal pin RD_F of QL5232 chip jointly.
The Dai[0 of front end programmable control chip, 11], CNT[0,7] signal pins is connected CNT[0,7 with the corresponding signal pin of rear end programmable control chip] signal pins sends the time sequence information that pre-sets to X
00, X
01, X
02, X
03Chip; And the COMB[0 of front end programmable control chip, 7] and RD/AB[0,15] be connected with the corresponding signal pin of programmable interface control chip 7, COMB[0,7] be the control command interface, RD/AB[0,15] be the data address interface, be used for being provided with various initial values, command register, sampling plan and inner decoding.
The DB[0 of rear end programmable control chip, 7] be connected DB[0,7 with the corresponding pin of QL5232 chip] for transmitting the time sequence information data-interface.
The formula storer of front end programmable control chip, rear end programmable control chip is the XC18V01 chip XC0 and the XC1 of XILINX company, start back is got in touch by itself and computing machine, can series arrangement front end programmable control chip, the rear end programmable control chip.
Transmit the scheme data of computing machine to this device from pci interface, the information such as difference sampling starting point that comprise each road analog input signal, these signals are handled by programmable interface control chip 7, through COMB[0,7] control command interface, RD/AB[0,15] data-interface is sent to the various initial values and the command register of front end programmable control chip 4 inside then; According to the difference of sampling plan, change front end programmable control chip 4 inner various initial registers and command registers, can be so that have different sampling starting points between each road analog input signal.
Rear end programmable control chip 5 is finished read-write sequence control and is produced circuit, condition discrimination auxiliary circuit and data superposition, read-write sequence control produces circuit and mainly is made up of the pulse beat generator, the pulse beat generator is an one-period with eight beats, moves in circles, wherein T
0Beat is carried out sky/full mode bit and data superposition computing command bit of differentiating asynchronous FIFO memory, produces one and waits for or carry out signal (NOP/RUN), T
2-T
4Beat is the read pulse width of first order asynchronous FIFO memory 3, T
1Be the clock signal of first order data superposition pipeline, T
3Be the clock signal of second level data superposition pipeline, T
6-T
7Beat is the write pulse width of second level asynchronous FIFO memory 6.
First order asynchronous FIFO memory 3 is directly controlled by front end programmable control chip 4, the length (being frame length) that rear end programmable control chip 5 only will will receive data at every turn is transferred to front end programmable control chip 4, sends reading by 4 controls of front end programmable control chip.
The condition discrimination auxiliary circuit detects the state of asynchronous FIFO memory, when being illegal as state, then stops all command signals in the next beat cycle.
Entire circuit is under the commander of pulse beat generator, according to the numerical value of front end programmable control chip 4 inner various initial registers and command register, with decision from which sampling channel begin to sample, sampling length what are and and sampling time of other passage poor; Data superposition pipeline adds computing entirely to the multichannel data of importing under clock signal cooperates, it is carried out with multistage duct type, till computing to frame data finish.
Programmable interface control chip 7 is realized the weighted mean filtering and the pci interface of data, and the data behind the output superposition are accepted sampling plan and initial value order that computing machine sends simultaneously, thereby controlled the sampling of each road analog input signal to back-end computer.
The sample frequency of modulus sample conversion device 2 is 50Mhz in native system, and the clock rate of writing of first order asynchronous FIFO memory 3 is 50Mhz to the maximum, and these two signals integrate.Being the parallel work-flow of the dummy status of avoiding asynchronous FIFO memory and the system of realization, guaranteeing that first order asynchronous FIFO memory writes sooner than reading, is 12.5Mhz so get the clock of reading of first order asynchronous FIFO memory 3; Here first order asynchronous FIFO memory has played the buffer action of high-speed data to the low speed conversion; The clock rate of writing of second level asynchronous FIFO memory is 12.5Mhz, is 33Mhz and read clock, and second level asynchronous FIFO memory has played the buffer action of low speed data to high-speed transitions; Here the conversion key of data rate is that the meaning of data rate transition is to read and write the difference on the speed to the differentiation of the read-write sequence and the state of asynchronous FIFO memory.
The utility model principle of work and use are, after some acquisition scheme generate in background computer, import this device by pci interface, deliver to four data register and command registers in the front end programmable control chip 4 through programmable interface control chip 7, these orders, data include the signalling channel that this acquisition scheme need start, interchannel sampling interval, the length of sampling etc., after setting is finished, the various programmable modules that rear end programmable control chip 5 unbalanced pulse beat generators, pulse beat instruction order about in 4 in the front end control core able to programme are carried out according to programmed order; The isometric sampled data of each signalling channel is deposited in the corresponding asynchronous FIFO memory, deposit original 8 sampled datas at first order asynchronous FIFO memory 3, second level asynchronous FIFO memory 6 is deposited 13 bit data (including a bit flag position) behind the superposition first time, after the sampling of one frame data finishes, read in and carry out exporting rear end programmable control chip 5 to after the computing by front end programmable control chip 4, carry out computing again, export programmable interface control chip 7 then to, in this programmable interface control chip 7, finish the filtering of multiple spot weighted mean; Final data is by pci interface input backstage computer, and test procedure is according to result of calculation, and whether decision needs to generate other scheme is continued data acquisition again.
Fig. 4 is a data superposition synoptic diagram, N road input signal C0-CN (N≤32) among the figure, to each curve do not go up at one time C00, C10 ..., the CN0 point samples, thereby the stacking value that forms N road sample that input signal is gathered is ∑ f0=C00+C10+ ... + CN0.
Claims (7)
1, a kind of multipath high-speed simulating signal asynchronous collecting and superposition device, it includes signal coupling circuit (1) and modulus sample conversion device (2), and it is characterized in that: this device also includes
The first order asynchronous FIFO memory (3) that is connected with modulus sample conversion device;
Be connected with first order asynchronous FIFO memory and modulus sample conversion device respectively and sampling time sequence controlled and formed the front end programmable control chip (4) of first order data superposition pipeline;
That be connected with the front end programmable control chip and form the rear end programmable control chip (5) of second level data superposition pipeline, sequential control circuit and read-write sequence circuit;
That be connected with the front and back ends programmable control chip respectively and form the digital filtering of data behind the superposition and the programmable interface control chip (7) of local bus interface;
The second level asynchronous FIFO memory (6) that is connected with programmable interface control chip (7) with above-mentioned rear end programmable control chip (5).
2, multipath high-speed simulating signal asynchronous collecting according to claim 1 and superposition device is characterized in that: described front and back ends programmable control chip is the XC2S100-5PQ208C field programmable gate array chip of company of match SEL.
3, multipath high-speed simulating signal asynchronous collecting according to claim 1 and superposition device is characterized in that: described programmable interface control chip is the QL5232 chip of the U.S. quick logic company.
4, according to claim 2 or 3 described multipath high-speed simulating signal asynchronous collecting and superposition devices, it is characterized in that: described first and second grade asynchronous FIFO memory is made up of the products C Y7C466A-10JC of company of Cypress Semiconductor Co., Ltd.
5, multipath high-speed simulating signal asynchronous collecting according to claim 4 and superposition device is characterized in that: described modulus sample conversion device adopts the AD9057-80 chip of Analog Devices Inc.
6, multipath high-speed simulating signal asynchronous collecting according to claim 5 and superposition device is characterized in that: the unity gain amplifier that described signal coupling circuit is made of the AD8041 operational amplifier of Analog Devices Inc.
7, multipath high-speed simulating signal asynchronous collecting according to claim 6 and superposition device, it is characterized in that: described front end programmable control chip, rear end programmable control chip are connected with the formula storer, and this formula storer is the XC18V01 chip of company of match SEL.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02265505U CN2558011Y (en) | 2002-07-15 | 2002-07-15 | Asychronous collection and superposition device for multiplex high speed analog signal |
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| Application Number | Priority Date | Filing Date | Title |
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| CN02265505U CN2558011Y (en) | 2002-07-15 | 2002-07-15 | Asychronous collection and superposition device for multiplex high speed analog signal |
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| CN2558011Y true CN2558011Y (en) | 2003-06-25 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105208275A (en) * | 2015-09-25 | 2015-12-30 | 北京航空航天大学 | System supporting real-time processing inside streaming data piece and design method |
| CN109003352A (en) * | 2018-07-02 | 2018-12-14 | 南京兴鼎升电气设备有限公司 | A kind of storage recording method of train event recorder |
-
2002
- 2002-07-15 CN CN02265505U patent/CN2558011Y/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105208275A (en) * | 2015-09-25 | 2015-12-30 | 北京航空航天大学 | System supporting real-time processing inside streaming data piece and design method |
| CN109003352A (en) * | 2018-07-02 | 2018-12-14 | 南京兴鼎升电气设备有限公司 | A kind of storage recording method of train event recorder |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20120715 Granted publication date: 20030625 |