CN201294493Y - Hierarchical amplifying circuit and multifunctional data acquisition card - Google Patents
Hierarchical amplifying circuit and multifunctional data acquisition card Download PDFInfo
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- CN201294493Y CN201294493Y CNU2008202225461U CN200820222546U CN201294493Y CN 201294493 Y CN201294493 Y CN 201294493Y CN U2008202225461 U CNU2008202225461 U CN U2008202225461U CN 200820222546 U CN200820222546 U CN 200820222546U CN 201294493 Y CN201294493 Y CN 201294493Y
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Abstract
The utility model relates to a grading amplifying circuit and a multifunctional data collecting card which adopts the grading amplifying circuit, wherein an analogue input unit of the multifunctional data collecting card adopts the grading amplifying circuit, the first grade adopts three operational amplifiers to realize the performances of high impedance and high common mode rejection, the second grade adopts the operational amplifier and a multiplexer to realize the functions of amplifying or reducing switching signals in multiple gears. The multifunctional data collecting card solves the technical problems that an existing amplifying circuit used for an instrument only can amplify signals and can not realize reducing the signals, and an existing data card can not simultaneously realize wide range and high scanning speed, and the multifunctional data card has the advantages of multiple functions and wide application range, and can simultaneously realize the requirements of high precision and high scanning rate with 1 MHz, and can realize the big capacitance data caching function.
Description
Technical field
The utility model relates to a kind of amplifying circuit, relates in particular to the amplifying circuit that a kind of classification is handled; The utility model also relates to a kind of data acquisition circuit, relates in particular to a kind of data acquisition circuit based on PXI or pci bus.
Background technology
Domestic at present based on the data collecting card function singleness of scan pattern, the scanning frequency of the multifunction card of existing 16 precision all is lower than 1MSa/s, and less at the plate buffer memory.Along with quick development of modern science and technology,, also more and more higher for the sampling precision and the rate request of multi-functional scanning collection especially in Aero-Space, military field.In this case, the multifunctional data acquisition card of exploitation high-speed, high precision has good application prospects.
Existing data collecting card adopts scan mode to realize the acquisition time of multi-channel analog signal, generally comprises Port Multiplier signal selecting circuit, amplifying circuit, ADC change-over circuit.Existing data collecting card adopts instrument to finish the signal amplification with amplification chip able to programme usually, but existing chip can't realize wide range (maximum input range ± 10V) and up to the sweep speed of 1MHz simultaneously, if will be operated in 1MHz scanning down, can have a strong impact on acquisition precision.Simultaneously, common instrument only carries out signal with amplifying circuit and amplifies, and can not realize the signal reduction capability.
Summary of the invention
One of the utility model purpose is to propose a kind of graded amplifying circuit that adopts bi-level treatment, and it has solved existing instrument and has only carried out the signal amplification with amplifying circuit, can not realize that signal dwindles technical problem.
Two of the utility model purpose is to propose a kind of high-velocity scanning of graded amplifying circuit, big buffer memory, high-precision multifunctional data acquisition card of adopting, and it has solved the technical problem that the available data capture card can't be realized wide range and high sweep speed simultaneously.
Concrete technology contents of the present utility model is:
A kind of graded amplifying circuit, its special character are that it comprises three discharge circuits, multi-way switch circuit and the level shifting circuit U5 that connects successively; Described three discharge circuits are used to realize importing the high impedance and the high cmrr of analog signal, and it comprises positive input discharge circuit U1B, negative input discharge circuit U1A and differential amplifier circuit U2; Described multi-way switch circuit is used to realize that the switching of many gear signal and signal amplify or dwindle, and it comprises the different convert resistance of preposition follower U3, the Port Multiplier U6, a plurality of parallel connection and the resistance that connect successively (R8～R14) and rearmounted amplifying circuit U4; Described preposition follower U3 is used to avoid the influence of the conducting resistance of Port Multiplier U6 to gain, and described Port Multiplier U6 and convert resistance (R8～R14) realize gear switch, described rearmounted amplifying circuit U4 is used for signal is adjusted to the voltage range of regulation; Described level shifting circuit U5 is used for the multi-way switch circuit amplification or the positive/negative voltage signal after dwindling converts positive voltage signal to.
Above-mentioned positive input discharge circuit U1B adopts amplifier AD8620; Described negative input discharge circuit U1A adopts amplifier AD8620; Described differential amplifier circuit U2 adopts amplifier THS4031; Described preposition follower U3 adopts amplifier AD8610; Described Port Multiplier U6 adopts Port Multiplier ADG1207; Described rearmounted amplifying circuit adopts amplifier AB8056, and described level shifting circuit U5 adopts amplifier LM6171.
A kind of multifunctional data acquisition card that adopts above-mentioned graded amplifying circuit, it comprises FPGA unit 1, pci interface 2, memory 3 and input-output unit; Described input-output unit comprises analog input unit 41; Described FPGA unit 1 is connected with memory 3, and described FPGA unit is connected with pci bus 5 by pci interface 2, and described FPGA unit is connected with IO interface 6 by input-output unit; Its special character is that described analog input unit 41 is a graded amplifying circuit; Described graded amplifying circuit comprises three discharge circuits, multi-way switch circuit and the level shifting circuit U5 that connects successively; Described three discharge circuits are used to realize importing the high impedance and the high common mode inhibition of analog signal, and it comprises positive input discharge circuit U1B, negative input discharge circuit U1A and differential amplifier circuit U2; Described multi-way switch circuit is used to realize that the switching of many gear signal and signal amplify or dwindle, and it comprises the different convert resistance of preposition follower U3, the Port Multiplier U6, a plurality of parallel connection and the resistance that connect successively (R8～R14) and rearmounted amplifying circuit U4; Described preposition follower U3 is used to avoid the influence of the conducting resistance of Port Multiplier U6 to gain, and described Port Multiplier U6 and convert resistance (R8～R14) realize gear switch, described rearmounted amplifying circuit U4 is used for signal is adjusted to the voltage range of regulation; Described level shifting circuit U5 is used for the multi-way switch circuit amplification or the positive/negative voltage signal after dwindling converts positive voltage signal to.
Above-mentioned positive input discharge circuit U1B adopts high speed and precision amplifier AD8620; Described negative input discharge circuit U1A adopts high speed and precision amplifier AD8620; Described differential amplifier circuit U2 adopts high speed and precision amplifier THS4031; Described preposition follower U3 adopts amplifier AD8610; Described Port Multiplier U6 adopts Port Multiplier ADG1207; Described rearmounted amplifying circuit adopts AB8056, and described level shifting circuit U5 adopts amplifier LM6171.
Above-mentioned input-output unit also can comprise simulation output unit 42 and/or digital I unit 43.
One end of above-mentioned digital I unit 43 is connected with FPGA unit 1, and its other end is connected with IO interface 6; It comprises the current-limiting resistance 20 that is arranged on the IO interface end and diode voltage-limiting protection circuit 10 and the bus switch 9 that is arranged on the FPGA interface end; Described bus switch 9 is used to realize the level conversion function.
Above-mentioned FPGA unit 1 comprises logical routing module 11, internal clocking 14, other control modules 18, memory control module 13, local bus control module 12 and input/output control module; Described logical routing module 11 is connected with internal clocking 14, other control modules 18, memory control module and input/output control module respectively; Described input/output control module comprises analog input control module 15; Described analog input control module 15 is connected with analog input unit 41, and described memory control module 13 is connected with memory 3; Described logical routing module 11 is connected with pci bus 5 by pci interface 2.
Above-mentioned input/output control module also can comprise simulation output control module 16 and/or digital I 17; Described simulation output control module 16 is connected with simulation output unit 42, and described digital I 17 is connected with digital I unit 43.
Above-mentioned memory 3 can be selected the SDRAM memory.
The utlity model has following advantage:
1, function is many, applied range.The utility model is based on the multifunctional data acquisition card of PXI or pci bus, and this capture card has analog acquisition, analog quantity output, digital quantity IO, timer conter and programmable functions interface function.Have 16 resolution, the analog acquisition of multichannel 1M scanning, functions such as 4 passages, 16 parallel-by-bit analog quantity outputs.
2, can realize high scan rate and high-precision requirement simultaneously.The utility model has adopted multistage amplifier circuit in order to realize the high-accuracy data acquisition requirement at front end, and especially the first order has adopted three amplifiers to realize the performance of high impedance, high cmrr; At first, the input high impedance can reduce the decay of input signal, improves acquisition precision; Secondly, the high cmrr of differential amplifier circuit can well suppress common-mode signal (interference), realizes high precision collecting.In addition, the utility model is at the characteristics of multi-channel data scanning collection, front end three amplifiers in the analog input unit, have been adopted, the mode of rear end Port Multiplier gain controlling is carried out signal condition, especially select the operational amplifier of high-speed, high precision, avoided the general programmable instrument with the scan rate defective that amplifier brought, can realize scan rate requirement up to 1MHz.
3, realize the large-capacity data caching function.Adopt the mode of FPGA control SDRAM memory stores, realized that plate carries big buffer memory, have the mass data storage function of analog acquisition, simulation output, digital I.Simultaneously can improve the IO buffer capacity greatly, reduce the requirement of PC response speed, applicable to high-speed, high precision multi-channel measurement occasion.
4, the utility model data collecting card adopts the analogue data output function of four path parallel, but every passage independent design output waveform, output area.
5, the utility model digital I unit directly utilizes FPGA to realize, adopts protection diode and bus switch to carry out the IO protection simultaneously.
Description of drawings
Fig. 1 is the utility model multifunctional data acquisition card circuit theory diagrams, wherein: 1-FPGA unit, 2-PCI interface, 3-memory, 41-analog input unit, 42-simulates output unit, 43-digital I unit, 5-PCI bus, the 6-IO interface, other circuit of 7-, 8-calibration circuit;
Fig. 2 is the utility model digital I element circuit schematic diagram, wherein: 9-bus switch, 10-diode voltage-limiting protection circuit, 20-current-limiting resistance;
Fig. 3 is the utility model digital I element circuit structural representation;
Fig. 4 is the utility model FPGA element circuit schematic diagram; Wherein: 11-logical routing module, 12-local bus control module, the 13-memory control module, the 14-internal clocking, 15-analog input control module, 16-simulates output control module, the 17-digital I, other control modules of 18-,
Fig. 5 is the utility model graded amplifying circuit schematic diagram; Wherein: U1B-positive input discharge circuit, the negative input of U1A-discharge circuit, U2-differential amplifier circuit, the preposition follower of U3-, U6-Port Multiplier, the rearmounted amplifying circuit of U4-, U5-level shifting circuit.
Embodiment
Referring to Fig. 1, the utility model multifunctional data acquisition card mainly is made up of analog input unit, simulation output unit, digital I unit, FPGA unit, memory, pci interface and power supply, be a kind of multifunctional data acquisition card, adopt the overall architecture of FPGA unit (Programmable Logic Controller)+PCI bridge+memory+ancillary equipment based on PXI or pci bus.Wherein: the FPGA unit adopts chip XC3S1500, realizes the functions such as Communication Control of the ancillary equipment control of (comprising analog input unit, simulation output unit, digital I unit), timer conter, memory control, pci interface chip; The FPGA unit adopts PCI 9054 chips to realize the PXI/PCI interface function, converts pci bus to local bus; The FPGA unit is connected with IO interface 6 by input-output unit; Pci interface FPGA unit is connected with memory, and the jumbo SDRAM chip MT48LC8M32 that memory adopts monolithic realizes the interim storage of jumbo analog-and digital-data; FPGA internal build sdram controller carries out the metadata cache of each several part; Because the maximum operation frequency of SDRAM is 100MHz, so adopt the multi-layer sheet wiring.
Referring to Fig. 2 and Fig. 3, the utility model digital I unit is in order to realize the independent control of single IO direction, the mode that adopts FPGA directly to realize.The port voltage height of common user IO level ratio FPGA is so the present invention adopts current-limiting resistance 20, diode voltage-limiting protection circuit 10 and bus switch 9 to carry out dual IO defencive function.Current-limiting resistance and diode carry out overvoltage protection, in voltage clamp to 0～5V, and the 3.3V signal that becomes FPGA normally to receive the IO conversion of signals of 5V through bus switch then.
Referring to Fig. 4, the FPGA unit comprises that control, timer conter, the memory of ancillary equipment such as analog input unit, simulation output unit, digital I unit are controlled, the functions such as Communication Control of pci interface chip.FPGA adopts modularized design, be divided into the funtion part of relative opposition, comprise analog input control module, simulation output control module, digital I, memory control module etc., also realize metadata cache function in a small amount simultaneously in inside, FPGA unit.
Referring to Fig. 5, (maximum input range ± 10V), gear is many, speed is fast, signal amplification and the function of dwindling, and the present invention adopts scan mode to realize the acquisition time of multi-channel analog signal for the input impedance height that reaches analog signal, common-mode rejection ratio height, input range are big.Specifically, analog input unit 41 adopts classification to handle, and promptly adopts graded amplifying circuit; The first order adopts three amplifiers to realize the performance of high impedance, high common mode inhibition, and the second level is adopted amplifier to add Port Multiplier and realized that many gear switches signal amplifies or reduction capability.Graded amplifying circuit comprises three discharge circuits, multi-way switch circuit and the level shifting circuit U5 that connects successively; Three discharge circuits are used to realize importing the high impedance and the high common mode inhibition of analog signal, and it comprises positive input discharge circuit U1B, negative input discharge circuit U1A and differential amplifier circuit U2; Multi-way switch circuit is used to realize that the switching of many gear signal and signal amplify or dwindle, and it comprises the different convert resistance of preposition follower U3, the Port Multiplier U6, a plurality of parallel connection and the resistance that connect successively (R8～R14) and rearmounted amplifying circuit U4; Preposition follower U3 is used to avoid the influence of the conducting resistance of Port Multiplier U6 to gain, and Port Multiplier U6 and convert resistance (R8～R14) realize gear switch, rearmounted amplifying circuit U4 is used for signal is adjusted to the voltage range of regulation; Level shifting circuit U5 is used for the multi-way switch circuit amplification or the positive/negative voltage signal after dwindling converts positive input discharge circuit and the negative high speed and precision amplifier AD8620 that imports discharge circuit selection AD company that positive voltage is believed three discharge circuits to, and differential amplifier circuit is selected the high speed and precision amplifier THS4031 of TI company for use.In order to realize programmable multrirange control, the utility model adopts Port Multiplier ADG1207 to carry out gear switch.For fear of the influence of the parameters such as conducting resistance of Port Multiplier, adopt amplifier AD8610 to control to gain etc.Adopt amplifier LM6171 through bias treatment at last, signal is adjusted in the input range of ADC.AD chip of the present invention, adopt 16 the single-ended input of 2MSPS ADC of TI, the translation data of ADC is under the control of FPGA, at first carry out a small amount of buffer memory in FPGA inside, after arrival is a certain amount of, move into and carry out buffer memory in the SDRAM memory, after the analog input in the SDRAM memory is cached to a certain degree, import data into PC, offer the user and use.
The simulation output unit adopts multi-disc high accuracy DAC chip LT1597, realizes multichannel Parallel Simulation output function.The data of simulation output also adopt the SDRAM memory to carry out buffer memory.
Claims (9)
1, a kind of graded amplifying circuit is characterized in that: it comprises three discharge circuits, multi-way switch circuit and the level shifting circuit (U5) that connects successively; Described three discharge circuits are used to realize importing the high impedance and the high cmrr of analog signal, and it comprises positive input discharge circuit (U1B), negative input discharge circuit (U1A) and differential amplifier circuit (U2); Described multi-way switch circuit is used to realize that the switching of many gear signal and signal amplify or dwindle, and it comprises the different convert resistance of the preposition follower (U3), Port Multiplier (U6), a plurality of parallel connection and the resistance that connect successively (R8～R14) and rearmounted amplifying circuit (U4); Described preposition follower (U3) is used to avoid the influence of the conducting resistance of Port Multiplier (U6) to gain, described Port Multiplier (U6) and convert resistance (R8～R14) realize gear switch, described rearmounted amplifying circuit (U4) is used for signal is adjusted to the voltage range of regulation; Described level shifting circuit (U5) is used for the multi-way switch circuit amplification or the positive/negative voltage signal after dwindling converts positive voltage signal to.
2, graded amplifying circuit according to claim 1 is characterized in that: described positive input discharge circuit (U1B) adopts amplifier AD8620; Described negative input discharge circuit (U1A) adopts amplifier AD8620; Described differential amplifier circuit (U2) adopts amplifier THS4031; Described preposition follower (U3) adopts amplifier AD8610; Described Port Multiplier (U6) adopts Port Multiplier ADG1207; Described rearmounted amplifying circuit adopts amplifier AB8056, and described level shifting circuit (U5) adopts amplifier LM6171.
3, a kind of multifunctional data acquisition card, it comprises FPGA unit (1), pci interface (2), memory (3) and input-output unit; Described input-output unit comprises analog input unit (41); Described FPGA unit (1) is connected with memory (3), and described FPGA unit is connected with pci bus (5) by pci interface (2), and described FPGA unit is connected with IO interface (6) by input-output unit; It is characterized in that: described analog input unit (41) is a graded amplifying circuit; Described graded amplifying circuit comprises three discharge circuits, multi-way switch circuit and the level shifting circuit (U5) that connects successively; Described three discharge circuits are used to realize importing the high impedance and the high common mode inhibition of analog signal, and it comprises positive input discharge circuit (U1B), negative input discharge circuit (U1A) and differential amplifier circuit (U2); Described multi-way switch circuit is used to realize that the switching of many gear signal and signal amplify or dwindle, and it comprises the different convert resistance of the preposition follower (U3), Port Multiplier (U6), a plurality of parallel connection and the resistance that connect successively (R8～R14) and rearmounted amplifying circuit (U4); Described preposition follower (U3) is used to avoid the influence of the conducting resistance of Port Multiplier (U6) to gain, described Port Multiplier (U6) and convert resistance (R8～R14) realize gear switch, described rearmounted amplifying circuit (U4) is used for signal is adjusted to the voltage range of regulation; Described level shifting circuit (U5) is used for the multi-way switch circuit amplification or the positive/negative voltage signal after dwindling converts positive voltage signal to.
4, graded amplifying circuit according to claim 3 is characterized in that: described positive input discharge circuit (U1B) adopts high speed and precision amplifier AD8620; Described negative input discharge circuit (U1A) adopts high speed and precision amplifier AD8620; Described differential amplifier circuit (U2) adopts high speed and precision amplifier THS4031; Described preposition follower (U3) adopts amplifier AD8610; Described Port Multiplier (U6) adopts Port Multiplier ADG1207; Described rearmounted amplifying circuit adopts AB8056, and described level shifting circuit (U5) adopts amplifier LM6171.
5, multifunctional data acquisition card according to claim 3 is characterized in that: described input-output unit also comprises simulation output unit (42) and/or digital I unit (43).
6, multifunctional data acquisition card according to claim 3 is characterized in that: an end of described digital I unit (43) is connected with FPGA unit (1), and its other end is connected with IO interface (6); It comprises current-limiting resistance (20) and diode voltage-limiting protection circuit (10) that is arranged on the IO interface end and the bus switch (9) that is arranged on the FPGA interface end; Described bus switch (9) is used to realize the level conversion function.
7, according to claim 3 or 4 or 5 or 6 described multifunctional data acquisition cards, it is characterized in that: described FPGA unit (1) comprises logical routing module (11), internal clocking (14), other control modules (18), memory control module (13), local bus control module (12) and input/output control module; Described logical routing module (11) is connected with internal clocking (14), other control modules (18), memory control module and input/output control module respectively; Described input/output control module comprises analog input control module (15); Described analog input control module (15) is connected with analog input unit (41), and described memory control module (13) is connected with memory (3); Described logical routing module (11) is connected with pci bus (5) by pci interface (2).
8, multifunctional data acquisition card according to claim 7 is characterized in that: described input/output control module also comprises simulation output control module (16) and/or digital I (17); Described simulation output control module (16) is connected with simulation output unit (42), and described digital I (17) is connected with digital I unit (43).
9, multifunctional data acquisition card according to claim 8 is characterized in that: described memory (3) is the SDRAM memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008202225461U CN201294493Y (en) | 2008-11-21 | 2008-11-21 | Hierarchical amplifying circuit and multifunctional data acquisition card |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNU2008202225461U CN201294493Y (en) | 2008-11-21 | 2008-11-21 | Hierarchical amplifying circuit and multifunctional data acquisition card |
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| CN201294493Y true CN201294493Y (en) | 2009-08-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNU2008202225461U Expired - Lifetime CN201294493Y (en) | 2008-11-21 | 2008-11-21 | Hierarchical amplifying circuit and multifunctional data acquisition card |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431315B (en) * | 2008-11-21 | 2011-12-14 | 陕西海泰电子有限责任公司 | Graded amplifying circuit and multifunctional data acquisition card |
| CN102323498A (en) * | 2011-06-09 | 2012-01-18 | 国网电力科学研究院 | Multi-stage segmented high-precision data sampling method |
-
2008
- 2008-11-21 CN CNU2008202225461U patent/CN201294493Y/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101431315B (en) * | 2008-11-21 | 2011-12-14 | 陕西海泰电子有限责任公司 | Graded amplifying circuit and multifunctional data acquisition card |
| CN102323498A (en) * | 2011-06-09 | 2012-01-18 | 国网电力科学研究院 | Multi-stage segmented high-precision data sampling method |
| CN102323498B (en) * | 2011-06-09 | 2013-09-18 | 国网电力科学研究院 | Multi-stage segmented high-precision data sampling method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20090819 Effective date of abandoning: 20081121 |