CN2548346Y

CN2548346Y - Intelligent reactive power automatic-compensation controller

Info

Publication number: CN2548346Y
Application number: CN 02228940
Authority: CN
Inventors: 李文联; 吕治安; 李文群
Original assignee: Individual
Current assignee: Individual
Priority date: 2002-04-03
Filing date: 2002-04-03
Publication date: 2003-04-30
Anticipated expiration: 2012-04-03

Abstract

The utility model relates to an intelligence reactive power automation-compensated controller, consisting of a dividing voltage circuit, a current transform circuit, an A/D converter, a slave processor, an interface circuit, a main processor, an output control circuit, a memory and a real-time clock. Under the controlling of the slave processor, the slave processor analyzes the signals which is sampled by the A/D converter to calculate effective value of each phase voltage and current, the active power, the reactive power and the power factor; the main processor compares the power factor with the preset data to calculate the best compensation capacitance value; the output control circuit controls the input or resection of the compensation capacitor to achieve fast phase separation compensation and then stores the parameters into the memory regularly. The utility model integrates the fast phase separation compensation of the reactive power in three-phase four-line low-voltage power supply circuit, the electricity parameters automatic monitoring and the long-time record function as a whole, which has the advantages of multiple functions, good control performance, high reliability, etc.

Description

Intelligent reactive power self-compensating controlling device

Technical field

The utility model relates to and a kind ofly is used to power or the reactive power self-compensating controlling device of distribution system.

Background technology

Exist reactive current in electric power system, it not only causes the user side voltage instability, also can increase line loss, so power department requires at user side reactive power compensator to be installed.Existing compensating controller can only carry out onesize compensation to three-phase line according to the power factor of circuit, but because the reactive current size of each phase is unequal often in the three-phase line, therefore if three-phase is carried out undercompensation or the overcompensation that onesize compensation will inevitably cause certain phase.Can't grasp the effect of compensation on the other hand, because of the function of controller no record power supply parameter, power supply department often will be installed the power supply quality detector in addition.

Summary of the invention

The purpose of this utility model is to provide that the reactive power in a kind of set pair low pressure three-phase and four-line distribution line is carried out fast, phase splitting compensation and power consumption parameter is monitored automatically, the non-volatile recording function is in the intelligent reactive power self-compensating controlling device of one.

The technical solution of the utility model comprises the bleeder circuit that respectively three-phase voltage is transformed to suitable A/D converter desired signal; Respectively three-phase current is transformed to the current conversion circuit that is fit to the A/D converter desired signal; An A/D converter, the input of this A/D converter are connected with the output of bleeder circuit, current conversion circuit respectively; And keyboard-display circuit; A real time clock circuit; A communication interface; It also comprises

One from processor, by chip U ₂And memory U ₄, triple gate U ₃, GALU ₆, latch U ₅Auxiliary circuit is formed, the output of its input and A/D converter joins, with the control A/D converter signal is sampled, and sampled signal is carried out obtaining after the analytical calculation power factor of effective value, three phases active power, three phase reactive power and the three-phase of three-phase voltage, electric current;

A primary processor, its input links to each other with output from processor through interface circuit, connects swap data by interface circuit between the two processor;

One by latch U ₁₂Be connected in series the output control circuit that forms with coincidence detection circuitry, photoelectrical coupler, its input is connected with primary processor through number bus, each phase power factor that primary processor will measure and initialize data are relatively, calculate the The optimal compensation capacitance, and input or excision by output control circuit control compensation capacitor, realize compensation fast.

A big capacity serial storage that is used for record data, the P of itself and primary processor ₁Mouth connects.

The utility model becomes the lower signal of voltage with three-phase voltage behind electric resistance partial pressure, by A/D converter it is sampled; Three-phase current is transformed to voltage signal through accurate instrument transformer, samples through A/D converter then.A/D converter is provided with 6 passages, can sample to above-mentioned 6 signals simultaneously, signal after the sampling is sent into the microprocessor (from processor) of a slice special use, the power factor of effective value, three phases active power, three phase reactive power and three-phase through draw three-phase voltage, three-phase current after processor analysis, calculating etc.Other work of controller are finished by another sheet microprocessor (primary processor), connect swap data by interface circuit between two processors of principal and subordinate; Each phase power factor that primary processor will measure and the power factor that presets in advance compare, and obtain best building-out capacitor value after as calculated, again by the input or the excision of output control circuit control compensation capacitor, realize compensation fast.Primary processor has a jumbo serial FLASH memory and a real time clock circuit.Real-time clock provides calendar and clock as the markers of working for controller.Timing microprocessor is deposited into the circuit parameter that measures in the FLASH memory by certain format, is provided with the back inquiry.Because adopt serial line interface FLASH memory, so its circuit structure is simple, recording capacity is big, the data reliability height.Primary processor has display circuit and key circuit, utilizes keyboard and display, running parameter or query note data that the user can setting controller.Microprocessor also has communication interface, can utilize certain communication media and host computer communication, and to form real-time supervisory control system, communications protocol meets related standards.For making control reliable, the output circuit of this controller has adopted " meeting " testing circuit, and during work, microprocessor control signal is kept in two latchs, have only that control circuit just can move when the output of two latchs is identical, otherwise the control circuit tripping.

Compared with prior art, the utlity model has modern design, function is many, and control performance is good, the reliability advantages of higher.

Description of drawings

Fig. 1 is a circuit block diagram of the present utility model; Fig. 2 is an A/D converter of the present utility model and circuit diagram from parts such as processors; Fig. 3 is the circuit diagram of parts such as master and slave processor interface circuit of the present utility model, FLASH memory and primary processor; Fig. 4 is the circuit diagram of output control part of the present utility model.

Embodiment

Among Fig. 1, the three-phase voltage of input is sent into bleeder circuit 1, three-phase current and is transformed to the signal that is fit to A/D converter 3 needs through current conversion circuit 2 respectively, bleeder circuit 1 is connected with A/D converter 3 with current conversion circuit 2, A/D converter 3 be connected from processor 4, under the control of processor 4,3 pairs of signals of A/D converter are sampled, from obtaining effective value, three phases active power, three phase reactive power and the power factor of three-phase voltage, electric current after 4 pairs of sampled signals of processor are carried out analytical calculation.Be connected with primary processor 6 by interface circuit 5 from processor 4, regularly send interruption application signal from processor 4 to primary processor 6, primary processor 6 reads the data of sending here from processor 4 after entering interrupt handling routine, relevant calculation of parameter according to parameter of setting in advance and actual measurement goes out each mutually required building-out capacitor value then, control signal is outputed to output control circuit 7, simultaneously major parameter is shown on keyboard-display circuit 8.Output control circuit 7 all is connected with primary processor 6 by data/address bus with keyboard-display circuit 8.Be used for the big capacity serial FLASH memory 10 of record data and the P of primary processor 6 ₁Mouth connects; The P of real time clock circuit 11 and primary processor 6 ₁Mouth connects, and primary processor 6 obtains calendar and clock informations from real-time clock 11.The data of record can be utilized keyboard-display circuit 8 inquiries, also can utilize communication interface 9 and host computer communication, and communication interface directly is connected with the serial port of primary processor 6.Wherein keyboard-display circuit 8, and communication interface 9 is a prior art.

Among Fig. 2, three-phase voltage V _A, V _B, V _C, be connected in A/D converter U through separately bleeder circuit respectively ₁, (AT73C501) AN ₁, AN ₃, AN ₅Input; Three-phase current is respectively through instrument transformer CT ₁, CT ₂, CT ₃Be connected in A/D converter U after being transformed to voltage signal ₁, AN ₂, AN ₄, AN ₆Input; U ₁, serial line interface three lead-in wires (CLKR, DATA, CLK) respectively with from processor chips U ₂, (AT73C506) corresponding connection of serial line interface (SCLK, STN, CLK).U ₂, STROB (latching) and U ₅With the U in the accompanying drawing 3 ₇, U ₈, U ₉Connect.Reset signal is through U ₂₀(not gate) adds to U ₂The XRES pin.Crystal oscillator X ₂Be used for producing U ₁And U ₂Required clock pulse.U ₄Be the memory (93C46) of a slice low capacity, be used to deposit correction coefficient.U ₃Be a slice triple gate, be used to realize U ₂With U ₄Interface.U ₆Be the GAL of a slice special use, be used to form logical circuit and realize U ₁, U ₂Between the conversion of required signal.Dial switch is used for setting U ₂Mode of operation; U ₅Be that a slice latch is used to produce U (74HC377) ₃The control signal that needs and to the U of primary processor ₇The Shen signal is interrupted in one of the INTO pin output of (in the accompanying drawing 3).

Among Fig. 3, U ₇(90S4414) be the host processor chip of system.U ₉Be a slice latch (74LS374), its input D ₀, D ₁, D ₂, D ₃, D ₄, D ₅, D ₆, D ₇Respectively with from processor chips U ₂Data wire D ₀, D ₁, D ₂, D ₃, D ₄, D ₅, D ₆, D ₇Corresponding connection, its output Q ₀, Q ₁, Q ₂, Q ₃, Q ₄, Q ₅, Q ₆, Q ₇Divide other and U ₇P ₀₀, P ₀₁, P ₀₂, P ₀₃, P ₀₄, P ₀₅, P ₀₆, P ₀₇Pin is corresponding to be connected.U ₁₈Be a d type flip flop (74HC74), its effect is with from processor " data are effective " signal broadening, so that U ₇Detect.U ₁₉Be address decoder, be used for producing selected signal, open U ₉Output.U during work ₂Data after utilizing the STROB signal with analytical calculation write latch U ₉, the STROB signal is with trigger U simultaneously ₁₈Be changed to " 0 ", U ₇After the reading of data again automatically with U ₁₈Be changed to " 1 ", set up both sides' contact, U with this ₇From U ₉Output obtain data.U ₈Be big capacity serial FLASH memory (AT45D041), this chip memory capacity is the 512K byte, can deposit the record data in 1 year, and its CS, SCK, SI, SO pin are connected to U ₇P ₁₄, P ₁₅, P ₁₆, P ₁₇Pin, its reset terminal RST and read-write control end WP fixedly connect high level, finish data write by the program generation corresponding driving signal of AT90S4414 during work.U ₁₀Be real-time timepiece chip, adopt P8583, it has I ²C interface, its pin SDA and SCK are connected to U respectively ₇P ₁₂, P ₁₃Pin is used software simulation I ²The work of C interface.X ₁, C ₆₂, C ₆₃The circuit of forming is used to produce U ₇Needed clock pulse signal.C ₆₁, R ₆₁Be U ₇Reset circuit.U ₁₁Be the RS485 interface chip, direct and U ₇Serial line interface connect.

Display circuit adopts the display driver circuit of a slice special use, drives 12 charactrons, is respectively applied for to show voltage in three phases, electric current and power factor; Keyboard circuit uses 74HC245 to be directly connected in U ₇Data/address bus.(not drawing among the figure).

Among Fig. 4, U ₁₂(74HC273) be a slice eight latchs, its input and U ₇P ₀The mouth correspondence is joined its output (Q ₁, Q ₅), (Q ₂, Q ₆), (Q ₃, Q ₇), (Q ₄, Q ₈) respectively with U _13A, U _13B, U _13C, U _13DCorrespondence is joined; U ₁₃Model be 74HC136, be open-collector XOR gate, be used to realize that " the meeting " of exporting control signal detect, simultaneously respectively through current-limiting resistor R ₁₄, R ₁₅, R ₁₆, R ₁₇With photoelectrical coupler U ₁₄, U ₁₅, U ₁₆, U ₁₇Connect, the output of photoelectrical coupler can be used to drive realization compensation condensers such as relay or controllable silicon throwing, cut.What the present embodiment adopted is 4 groups of switchings of branch, also can be divided into more groups.U ₇The high nibble of data and the content of low nibble are identical during the output control signal, U ₁₃To being latched in U ₁₂In high and low nibble compare, if conform to and could drive photoelectrical coupler work, thereby improved reliability.

(A, B, the every a slice of using mutually of C three-phase, structure is identical, only is the control circuit of a phase among the figure).

Claims

1, a kind of intelligent reactive power self-compensating controlling device comprises respectively three-phase voltage being transformed to the bleeder circuit (1) that is fit to the A/D converter desired signal; Respectively three-phase current is transformed to the current conversion circuit (2) that is fit to the A/D converter desired signal; An A/D converter (3), the input of this A/D converter (3) are connected with the output of bleeder circuit (1), current conversion circuit (2) respectively; An and keyboard-display circuit (8); A real time clock circuit (11); A communication interface (9), it is characterized in that: it also comprises

A control A/D converter (3) signal is sampled and sampled signal is carried out obtaining after the analytical calculation three-phase voltage, electric current effective value, three phases active power, three phase reactive power and three-phase power factor from processor (4), by chip U ₂And memory U ₄, triple gate U ₃, GALU ₆, latch U ₅Auxiliary circuit is formed, and the output of its input and A/D converter (3) joins;

A primary processor (6), its input links to each other with output from processor (4) through interface circuit (5), connects swap data by interface circuit (5) between the two processor;

One by latch U ₁₂Be connected in series the output control circuit (7) that forms with coincidence detection circuitry, photoelectrical coupler, its input is connected with primary processor (6) through number bus, each phase power factor that primary processor (6) will measure and initialize data are relatively, calculate the The optimal compensation capacitance, and pass through the input or the excision of output control circuit (7) control compensation electric capacity;

A big capacity serial storage (10) that is used for record data, the P of itself and primary processor (6) ₁Mouth connects.

2, automatic compensating controller according to claim 1 is characterized in that: primary processor (6) chip is AT90S4414; From processor (4) chip is AT73C506.

3, automatic compensating controller according to claim 1 is characterized in that communication interface (9) is connected with the serial port of primary processor (6), is used for carrying out communication with outside host computer.

4, automatic compensating controller according to claim 1 is characterized in that: said output control circuit (7) is the corresponding every phase a slice eight latch U that join ₁₂, U ₁₂Input respectively with host processor chip U ₇P ₀Mouthful corresponding connection, its output respectively with " meeting " testing circuit U _13A, U _13B, U _13C, U _13DCorrespondence is joined after current-limiting resistor and photoelectrical coupler U ₁₄, U ₁₅, U ₁₆, U ₁₇Connect, the output of photoelectrical coupler is used for driving the switching of relay or controllable silicon realization compensation condenser.