CN2369355Y - 半导体装置的封胶体装置 - Google Patents

半导体装置的封胶体装置 Download PDF

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Publication number
CN2369355Y
CN2369355Y CN99201395U CN99201395U CN2369355Y CN 2369355 Y CN2369355 Y CN 2369355Y CN 99201395 U CN99201395 U CN 99201395U CN 99201395 U CN99201395 U CN 99201395U CN 2369355 Y CN2369355 Y CN 2369355Y
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colloid
wafer
semiconductor device
substrate
adhesive body
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Expired - Fee Related
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CN99201395U
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李俊哲
方仁广
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

本实用新型涉及半导体装置的封胶装置,使之提高封胶质量。半导体装置的封胶体装置,其包括:一基板、一晶片、一上胶体及其上模具及一下胶体及其下模具;其特征是:基板包含一上表面及一下表面,并于基板设有一贯穿该上表面及下表面的孔;晶片位于基板下表面上;导线连接基板上表面的接点及晶片的接点;上胶体由上模具注入胶质材料形成,下胶体由下模具注入胶质材料形成,上胶体及下胶体将该晶片呈完全密封状态。用半导体装置封装。

Description

半导体装置的封胶体装置
本实用新型涉及封胶装置，尤其是指一种对半导体装置进行封胶的装置。
现有半导体装置封胶体如图1所示：其基板10有孔11，孔11下方设一垫片12，供晶片20设置，晶片20背面利用模具注胶，将液态胶包封突出于基板10表面的整个积体电路的晶片20背面，并形成一封胶体22。而晶片20的正面布设导线21部份则由于受基板10阻挡限制，因此，无法利用模具进行注胶，只能采用点胶方式。但采用点胶方式将液态胶滴于基板10上时，由于无法控制液态胶质材料所扩散的范围，造成封胶体23形状不规则、表面凹凸不平及导线裸露等缺点。此外，采用点胶，须在真空状态下进行，以避免封胶体23内产生气泡。
本实用新型的目的是提供一种具有控制封胶量、避免导线裸露及产生气泡的半导体装置的封胶体装置。
本实用新型的目的是这样实现的：半导体装置的封胶体装置，其包括：一基板、一晶片，一上胶体及其上模具及一下胶体及其下模具；其特征是：基板包含一上表面及一下表面，并于基板设有一贯穿该上表面及下表面的孔；晶片位于基板下表面上；导线连接基板上表面的接点及晶片的接点；上胶体由上模具注入胶质材料形成，下胶体由下模具注入胶质材料形成，上胶体及下胶体将该晶片呈完全密封状态。
上述设计，由于使用模具进行注胶，使基板不需在真空环境下进行封装，并使上胶体形状具有固定模型及表面平坦，从而达到导线不会裸露，上胶体内不会产生气泡的效果。
下面通过附图、实施例再作进一步说明。
图1现有半导体装置封胶体的示意图；
图2本实用新型半导体装置封胶前及其上、下模具示意图；
图3本实用新型半导体装置封胶后示意图。
如图2、3所示：本实用新型包括：一基板30、一晶片35、一上胶体38及其上模具42及一下胶体37及其下模具40；其特征是：基板30包含一上表面31及一下表面32，并于基板30设有一贯穿该上表面31及下表面32的孔33；晶片35位于基板30下表面32上；导线36连接基板30上表面31的接点及晶片35的接点；上胶体38由上模具42注入胶质材料形成，下胶体37由下模具40注入胶质材料形成，上胶体38及下胶体37将该晶片35呈完全密封状态。其中，基板30的孔33粘设有供该晶片35设置的垫片34。其中，上模具42位于基板30上表面31的孔33上方。其所封装的导线36可以有许多条。其中，下模具40位于基板30下表面32的孔33下方。其中，上模具42设有一注胶口43。其中，下模具40设有一注胶口41。
本实用新型不仅解决了采用点胶方式的半导体装置胶体所造成的液态胶质材料难以控制其扩散范围，封胶体形状不规则、表面凸凹不平及导线裸露，以及封胶体产生气泡等缺点，而且上胶体形状可随模具变化而变化，改善外观，胶量可控，避免浪费。

Claims (6)

1、半导体装置的封胶体装置，其包括：一基板、一晶片、一上胶体及其上模具及一下胶体及其下模具；其特征是：基板包含一上表面及一下表面，并于基板设有一贯穿该上表面及下表面的孔；晶片位于基板下表面上；导线连接基板上表面的接点及晶片的接点；上胶体由上模具注入胶质材料形成，下胶体由下模具注入胶质材料形成，上胶体及下胶体将该晶片呈完全密封状态。
2、如权利要求1所述的半导体装置的封胶体装置，其特征是：其中，基板的孔粘设有供该晶片设置的垫片。
3、如权利要求1所述的半导体装置的封胶体装置，其特征是：其中，上模具位于基板上表面的孔上方。
4、如权利要求1所述的半导体装置的封胶体装置，其特征是：其中，下模具位于基板下表面的孔下方。
5、如权利要求1所述的半导体装置的封胶体装置，其特征是：其中，上模具设有一注胶口。
6、如权利要求1所述的半导体装置的封胶体装置，其特征是：其中，下模具设有一注胶口。
CN99201395U 1999-02-09 1999-02-09 半导体装置的封胶体装置 Expired - Fee Related CN2369355Y (zh)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1315167C (zh) * 2002-08-26 2007-05-09 日月光半导体制造股份有限公司 具有静电放电防护的封装模具
CN100355390C (zh) * 2005-03-15 2007-12-19 深圳迈瑞生物医疗电子股份有限公司 硅胶指套血氧探头封线的方法和模具
CN101584044B (zh) * 2006-12-12 2014-12-17 艾格瑞***有限公司 集成电路封装体和用于在集成电路封装体中散热的方法
CN104409387A (zh) * 2014-10-27 2015-03-11 三星半导体(中国)研究开发有限公司 封装设备及封装方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1315167C (zh) * 2002-08-26 2007-05-09 日月光半导体制造股份有限公司 具有静电放电防护的封装模具
CN100355390C (zh) * 2005-03-15 2007-12-19 深圳迈瑞生物医疗电子股份有限公司 硅胶指套血氧探头封线的方法和模具
CN101584044B (zh) * 2006-12-12 2014-12-17 艾格瑞***有限公司 集成电路封装体和用于在集成电路封装体中散热的方法
CN104409387A (zh) * 2014-10-27 2015-03-11 三星半导体(中国)研究开发有限公司 封装设备及封装方法

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