CN221409010U

CN221409010U - Sensor pixel unit, signal processing circuit and electronic device

Info

Publication number: CN221409010U
Application number: CN202322664826.5U
Authority: CN
Inventors: 韩润泽
Original assignee: Pulse Vision Beijing Technology Co ltd
Current assignee: Pulse Vision Beijing Technology Co ltd
Priority date: 2023-09-28
Filing date: 2023-09-28
Publication date: 2024-07-23
Anticipated expiration: 2033-09-28

Abstract

The embodiment of the disclosure discloses a sensor pixel unit, a signal processing circuit and an electronic device, wherein the sensor pixel unit comprises: k signal acquisition modules, signal processing modules and signal output modules; wherein k is an integer greater than or equal to 1; each signal acquisition module is respectively connected with the signal processing module and the signal output module; the signal processing module is connected with each signal acquisition module in the k signal acquisition modules and is connected with the signal output module; the signal output module is connected with each signal acquisition module in the k signal acquisition modules and is connected with the signal processing module. According to the embodiment, the exposure time in the pixel unit is adjustable through the first feedback signal and the second feedback signal, and then high dynamic range imaging is achieved.

Description

Sensor pixel unit, signal processing circuit and electronic device

Technical Field

The disclosure relates to the technical field of image sensors, in particular to a sensor pixel unit, a signal processing circuit and electronic equipment.

Background

Image sensors have been widely used in the fields of digital cameras, mobile phones, medical treatment, automobiles, unmanned aerial vehicles, machine recognition, etc., and particularly, the rapid development of the technology for manufacturing complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors has led to higher demands on the quality of the output images of the image sensors. The dynamic range is an important evaluation index of the photoelectric image sensor.

Disclosure of utility model

According to an aspect of the embodiments of the present disclosure, there is provided a sensor pixel unit including: k signal acquisition modules, signal processing modules and signal output modules; wherein k is an integer greater than or equal to 1;

Each signal acquisition module is respectively connected with the signal processing module and the signal output module;

The signal processing module is connected with each signal acquisition module in the k signal acquisition modules and is connected with the signal output module;

the signal output module is connected with each signal acquisition module in the k signal acquisition modules and is connected with the signal processing module.

Optionally, the signal acquisition module includes: a photodiode and a first switching transistor;

One end of the photodiode is grounded, and the other end of the photodiode is connected with the signal processing module through the first switching transistor;

The drain terminal of the first switching transistor is connected with the signal processing module and the signal output module, the source terminal of the first switching transistor is connected with the photodiode, and the gate terminal of the first switching transistor receives a first feedback signal.

Optionally, the signal acquisition module further includes: a second switching transistor;

The drain terminal of the second switching transistor receives the first feedback signal, the source terminal of the second switching transistor is connected with the gate terminal of the first switching transistor, and the gate terminal of the second switching transistor receives the first switching signal.

Optionally, the signal processing module includes: a floating diffusion region, a reset transistor, and a reset control transistor;

One end of the floating diffusion area is grounded, and the other end of the floating diffusion area is connected with the source electrode end of the reset transistor to serve as a connecting end of the signal processing module; the signal acquisition module is connected with the signal output module through the connecting end;

the source end of the reset transistor is connected with the floating diffusion region, the drain end of the reset transistor receives a power supply signal, and the gate end of the reset transistor receives the second feedback signal through the reset control transistor;

The source end of the reset control transistor receives a second feedback signal, the gate end of the reset control transistor receives a second switching signal, and the drain end of the reset control transistor is connected with the gate end of the reset transistor.

Optionally, the signal output module includes: a source follower transistor and a select transistor;

The grid end of the source following transistor is connected with the signal processing module, the source end of the source following transistor is connected with the selection transistor, and the drain end of the source following transistor receives a power supply signal;

the drain terminal of the selection transistor is connected with the source terminal of the source following transistor, the source terminal is connected with the signal quantization module, and the gate terminal receives an external control signal.

According to another aspect of the embodiments of the present disclosure, there is provided a signal processing circuit including: a pixel array comprising m rows by n columns of sensor pixel cells according to any one of the embodiments above, and n by k column processors; wherein each of the column processors corresponds to at least part of the circuitry of each of m of the sensor pixel cells in a column; m and n are integers greater than or equal to 1 respectively;

The output ends of the m image sensor pixel units included in each column of the pixel array are respectively connected with the input ends of the corresponding k column processors, and the input ends of the m image sensor pixel units included in each column are respectively connected with the output ends of the corresponding k column processors.

Optionally, the method further comprises: n x k digital readout circuits and n x k double sampling readout circuits;

Each of said digital readout circuits is connected to one of said column processors;

Each of the double sampling readout circuits is connected to one of the column processors.

Optionally, the column processor includes: a comparator, a first AND logic circuit, and a second AND logic circuit;

The negative input end of the comparator is connected with the output end of the sensor pixel unit, the positive input end receives a reference signal, the output end is output as the output end of the column processor, and the output end is respectively connected with one input end of the first AND logic circuit and one input end of the second AND logic circuit;

One input end of the first AND logic circuit is connected with the output end of the comparator, the other input end receives a first external AND signal, and the output end outputs a first feedback signal;

one input end of the second AND logic circuit is connected with the output end of the comparator, the other input end receives a second external AND signal, and the output end outputs a second feedback signal.

Optionally, the column processor further comprises: a third AND logic circuit;

the output end of the comparator is also connected with one input end of the third AND logic circuit, and the other input end of the third AND logic circuit receives a power supply signal; the output end of the third AND logic circuit is connected with the enabling port of the double-sampling readout circuit;

And the input end of the double-sampling readout circuit is connected with the output end of the sensor pixel unit, and the enabling port is connected with the output end of the third AND logic circuit.

According to still another aspect of the embodiments of the present disclosure, there is provided an electronic device including: the sensor pixel unit of any embodiment or the signal processing circuit of any embodiment comprises a processor and a memory communicatively connected with the processor;

The memory stores computer-executable instructions;

The processor executes computer-executable instructions stored by the memory to control the sensor pixel unit or signal processing circuitry.

Optionally, the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.

The sensor pixel unit, the signal processing circuit and the electronic device provided based on the above embodiments of the present disclosure include: k signal acquisition modules, signal processing modules and signal output modules; wherein k is an integer greater than or equal to 1; each signal acquisition module is respectively connected with the signal processing module and the signal output module; the signal processing module is connected with each signal acquisition module in the k signal acquisition modules and is connected with the signal output module; the signal output module is connected with each signal acquisition module in the k signal acquisition modules and is connected with the signal processing module. According to the embodiment, the exposure time in the pixel unit is adjustable through the first feedback signal and the second feedback signal, and then high dynamic range imaging is achieved.

The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

Fig. 1 is a schematic circuit diagram of a sensor pixel unit according to an exemplary embodiment of the present disclosure;

Fig. 2 is a schematic circuit diagram of a signal acquisition module in a sensor pixel unit according to an exemplary embodiment of the present disclosure;

Fig. 3 is a schematic circuit diagram of a signal processing module in a sensor pixel unit according to an exemplary embodiment of the present disclosure;

FIG. 4 is a schematic diagram of an alternative circuit configuration of a sensor pixel cell provided in accordance with another exemplary embodiment of the present disclosure;

fig. 5 is a schematic circuit diagram of a signal processing circuit according to an exemplary embodiment of the present disclosure;

Fig. 6 is a schematic circuit diagram of a signal processing circuit provided in another exemplary embodiment of the present disclosure;

FIG. 7a is a schematic diagram of a digital sequence of digital readout circuit outputs in an alternative example of a signal processing circuit provided in an exemplary embodiment of the present disclosure;

FIG. 7b is a schematic diagram of an analog signal output by the dual sampling readout circuit according to the embodiment shown in FIG. 7 a;

fig. 8a is a schematic circuit diagram of a column processor in a signal processing circuit according to an exemplary embodiment of the present disclosure;

Fig. 8b is a schematic circuit diagram of a column processor in a signal processing circuit according to another exemplary embodiment of the present disclosure;

FIG. 9 is a timing diagram of various signals in one example of a signal processing circuit provided in an exemplary embodiment of the present disclosure;

fig. 10 illustrates a block diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present disclosure and not all of the embodiments of the present disclosure, and that the present disclosure is not limited by the example embodiments described herein.

It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.

It will be appreciated by those of skill in the art that the terms "first," "second," etc. in embodiments of the present disclosure are used merely to distinguish between different steps, devices or modules, etc., and do not represent any particular technical meaning nor necessarily logical order between them.

It should also be understood that in embodiments of the present disclosure, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.

It should also be appreciated that any component, data, or structure referred to in the presently disclosed embodiments may be generally understood as one or more without explicit limitation or the contrary in the context.

In addition, the term "and/or" in this disclosure is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the front and rear association objects are an or relationship. The data referred to in this disclosure may include unstructured data, such as text, images, video, and the like, as well as structured data.

It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.

Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In the process of implementing the present disclosure, the inventor finds that, in order to improve the dynamic range of the photoelectric image sensor, three main ways are currently adopted: the first method is multi-frame exposure synthesis, and images from underexposure to overexposure are continuously output in time and then fused, so that an image with a high dynamic range is obtained, and when an image sensor or a shooting object moves, the images from underexposure to overexposure are obtained at different time points, so that motion artifacts, blurring and the like of the synthesized images may occur. The second method is to provide two Photodiodes (PD) in size in a pixel, and read out the charge amount accumulated in the two photodiodes each time, thereby giving consideration to imaging of a low dark area and a high bright area. However, since the large photodiode and the small photodiode are integrated in the pixel respectively, the pixel area and the complexity of preparation in the process are increased, signals in the large photodiode and the small photodiode are required to be read out at the same time each time, the time for reading out the signals each time is increased, and the imaging speed is limited. The third mode is the LOFIC (Lateral Over Flow Integration Capacitor, lateral overflow collection capacitance) technology, when exposure, the PD only reaches half of the saturated well capacitance, the related circuit action is triggered, and the charge on the PD is transferred to the separately added storage capacitance, so that the charge storage capacity of the pixel is increased, and the high dynamic range imaging is realized. The main challenge of this technology is to efficiently manufacture large-capacity storage capacitors, and thus new pixel fabrication processes need to be developed.

The three ways of realizing the high dynamic range mainly comprise the synthesis of exposure images at different moments, and the addition of PD or capacitance in pixels to adjust the sensitivity of the pixels, which puts higher demands on algorithms and pixel preparation processes.

Fig. 1 is a schematic circuit diagram of a sensor pixel unit according to an exemplary embodiment of the present disclosure. As shown in fig. 1, includes: k signal acquisition modules 11, a signal processing module 12 and a signal output module 13.

Wherein k is an integer of 1 or more. Each signal acquisition module 11 is connected with a signal processing module 12 and a signal output module 13 respectively.

Each signal acquisition module 11 is respectively connected with the signal processing module 12 and the signal output module 13, and is used for receiving the optical signal in the exposure time period to generate photoelectric charges and outputting the photoelectric charges according to the control of the first feedback signal.

Alternatively, the main component in the signal acquisition module 11 may be a photoelectric conversion component (e.g., a photodiode, etc.), which receives an optical signal during the exposure period and converts the optical signal into photoelectric charges; and before the photoelectric charges are transmitted to the signal processing module, the photoelectric charges are stored, and the representation of the light intensity is realized through the quantity of the generated photoelectric charges. The first feedback signal may be determined based on the target signal output by the signal output module 13 through processing, that is, the exposure time is automatically adjusted based on the target signal. When the first feedback signal is at a high level, the control signal acquisition module 11 outputs photoelectric charge; when the first feedback signal is at a low level, the signal acquisition module 11 accumulates photoelectric charges and does not transmit.

In this embodiment, the signal acquisition functions of k independent sensor pixel units are realized by integrating k signal acquisition modules 11 in the same sensor pixel unit, but since only one set of signal processing module and signal output module is used, the chip size is compressed, the size of the hardware occupation space of the sensor applying the sensor pixel unit is reduced, and the application range of the sensor pixel unit is enlarged.

The signal processing module 12 is connected with each signal acquisition module 11 of the k signal acquisition modules 11, and is connected with the signal output module 13, and is used for performing resetting or sequentially reading photoelectric charges generated by each signal acquisition module of the k signal acquisition modules according to control of the second feedback signal.

Alternatively, the signal processing module 12 may perform the reset according to the control of the second feedback signal before processing the signal. The signal processing module 12 also generates photoelectric charges under the illumination condition, realizes the light detection function, and reads the photoelectric charges generated in the signal acquisition module according to the control of the second feedback signal when the preset condition is reached. When the second feedback signal is high level, the signal processing module 12 performs reset; when the second feedback signal is at a low level, the signal processing module 12 reads the photoelectric charge generated by each signal acquisition module 11 of the k signal acquisition modules 11 in turn.

The signal output module 13 is connected to each signal acquisition module 11 of the k signal acquisition modules 11, and is connected to the signal processing module 12, and is configured to output a target signal based on the photoelectric charge in the signal processing module according to control of an external control signal.

Alternatively, the target signal may comprise at least one of the following signals: pulse signals, potential signals, and values with limits, etc.

The embodiment of the disclosure provides a sensor pixel unit, a signal processing circuit and an electronic device, including: k signal acquisition modules, signal processing modules and signal output modules; wherein k is an integer greater than or equal to 1; each signal acquisition module is respectively connected with the signal processing module and the signal output module; the signal processing module is connected with each signal acquisition module in the k signal acquisition modules and is connected with the signal output module; the signal output module is connected with each signal acquisition module in the k signal acquisition modules and is connected with the signal processing module. According to the embodiment, the exposure time in the pixel unit is adjustable through the first feedback signal and the second feedback signal, and then high dynamic range imaging is achieved.

Fig. 2 is a schematic circuit diagram of a signal acquisition module in a sensor pixel unit according to an exemplary embodiment of the present disclosure. As shown in fig. 2, the signal acquisition module 11 includes: a photodiode 111 and a first switching transistor 112;

One end of the photodiode 111 is grounded, and the other end is connected to the signal processing module 12 through the first switching transistor 112.

Alternatively, the photodiode 111 may be another photoelectric conversion device capable of performing photoelectric conversion, so as to convert the optical signal into photoelectric charge. Under light conditions, the photodiode 111 generates a photoelectric charge, and the photoelectric charge is confined by the energy potential well in the depletion region of the photodiode 111 before the first switching transistor is turned off, and the photoelectric charge in the photodiode 111 gradually accumulates.

The drain terminal of the first switching transistor 112 is connected to the signal processing module 12 and the signal output module 13, the source terminal is connected to the photodiode 111, and the gate terminal receives the first feedback signal Φ _TXy for turning on or off according to the control of the first feedback signal Φ _TXy.

In this embodiment, the photodiode 111 is connected to the signal processing module 12 through the first switching transistor 112, when the first switching transistor 112 is opened, the photoelectric charges accumulated by the photodiode 111 cannot be transmitted, and only the accumulated charges can be continuously accumulated, and only when the first switching transistor 112 is closed, the photodiode 111 transmits the collected photoelectric charges to the signal processing module 12.

As shown in fig. 2, the signal acquisition module 11 further includes: a second switching transistor 113;

The drain terminal of the second switch transistor 113 receives the first feedback signal Φ _TXy, the source terminal is connected to the gate terminal of the first switch transistor 112, and the gate terminal receives the first switch signal Φ _TXx, which is used for conducting or disconnecting according to the control of the first switch signal Φ _TXx, so that when the second switch transistor 113 is conducted, the first feedback signal Φ _TXy is transmitted to the first switch transistor 112 to control the first switch transistor 112.

In the present embodiment, the control of the transmission of the first feedback signal Φ _TXy to the first switching transistor 112 is achieved by adding the second switching transistor 113, and the second switching transistor 113 is turned on only when the first switching signal Φ _TXx is at a high level. At this time, the first feedback signal Φ _TXy is transmitted to the gate terminal of the first switching transistor 112, so as to realize the conduction control of the first switching transistor 112, when the first feedback signal Φ _TXy is at a high level, the first switching transistor 112 is turned on, and the photodiode 111 sends the collected photoelectric charges to the signal processing module 12; when the first feedback signal Φ _TXy is low, the first switching transistor 112 is turned off. The present embodiment controls the first switching transistor 112 by adding the second switching transistor 113 to realize the control of the exposure time of the photodiode 111 by the first feedback signal Φ _TXy allowing the external transmission.

Fig. 3 is a schematic circuit diagram of a signal processing module in a sensor pixel unit according to an exemplary embodiment of the disclosure. As shown in fig. 3, the signal processing module 12 includes: a floating diffusion region 121, a reset transistor 122, and a reset control transistor 123.

One end of the floating diffusion region 121 is grounded GND, and the other end is connected to the source terminal of the reset transistor 122 as a connection terminal of the signal processing module; is connected with the signal acquisition module 11 and the signal output module 13 through connecting ends.

Alternatively, the floating diffusion region 121 performs reset when the reset transistor 122 is turned on; the floating diffusion region 121 receives the photoelectric charge generated by the photodiode of the signal acquisition module 11 when the reset transistor 122 is turned off and the first switching transistor 112 in one signal acquisition module 11 is turned on.

In this embodiment, the floating diffusion region 121 is a general structure in a pixel unit having a 4T structure, and the photo-detection function is realized by the floating diffusion region 121, and when the photodiode 111 is turned on between the signal processing modules 12, the photo-electric charges generated in the photodiode 111 are read to the floating diffusion region 121.

The source terminal of the reset transistor 122 is connected to the floating diffusion 121, the drain terminal receives the power supply signal Vdd, and the gate terminal receives the second feedback signal Φ _rsty through the reset control transistor 123.

Alternatively, the reset transistor 122, when turned on, turns on the floating diffusion 121 with the power supply signal Vdd, implements reset of the floating diffusion 121, and charges the voltage on the floating diffusion 121 to a high level. Under illumination conditions, photoelectric charges are generated in both the photodiode 111 and the floating diffusion region 121, wherein the voltage on the floating diffusion region 121 gradually decreases under the action of the photoelectric charges. The floating diffusion region 121 normally performs reset before photoelectric charge is generated.

The source terminal of the reset control transistor 123 receives the second feedback signal Φ _rsty, the gate terminal receives the second switching signal Φ _rstx, and the drain terminal is connected to the gate terminal of the reset transistor 122, and is used for being turned on or off according to the control of the second switching signal Φ _rstx, so that when the reset control transistor 123 is turned on, the second feedback signal Φ _rsty is transmitted to the gate terminal of the reset transistor.

The source terminal of the reset control transistor 123 receives the second feedback signal Φ _rsty, the gate terminal receives the second switching signal Φ _rstx, and the drain terminal is connected to the gate terminal of the reset transistor 122.

The present embodiment uses the amount of change in the voltage signal caused by the photoelectric charge in the floating diffusion region to determine whether or not to transfer and read out the photoelectric charge stored in the photodiode.

In this embodiment, whether the reset transistor 122 is turned on depends on whether the level received by the gate terminal is high, and the reset transistor 122 is turned on only when the second feedback signal Φ _rsty received by the gate terminal is high. While whether the second feedback signal Φ _rsty can be transmitted to the gate terminal of the reset transistor 122 depends on whether the reset control transistor 123 is turned on, the reset control transistor 123 is turned on when the second switch signal Φ _rstx is at a high level. The present embodiment realizes control of the reset transistor 122 by the second switching signal Φ _rstx allowing external input by providing the reset control transistor 123; the control of resetting or reading charges of the floating diffusion region 121 through the second switching signal phi _rstx and the second feedback signal phi _rsty is realized, when the floating diffusion region 121 is reset, the photodiode 111 completes exposure, the self-adaptive adjustment of the exposure time of the photodiode 111 is realized, and further, the high dynamic range imaging is realized. In addition, since the target signal linearly increases with time and the noise is in an open root relation with the increase of time, if the exposure time of the sensor pixel unit in the dark light area can be increased, the signal to noise ratio can be improved, and the image quality can be improved; in this embodiment, the exposure time of the photodiode 111 is adaptively adjusted, so that the exposure time of the sensor pixel unit in the dark light region can be adaptively increased, the signal-to-noise ratio is improved, and the quality of the acquired image is improved.

Fig. 4 is a schematic diagram of an alternative circuit structure of a sensor pixel unit according to another exemplary embodiment of the present disclosure. As shown in fig. 4, in this embodiment, a signal acquisition module 11 is included, and a signal output module 13 includes: a source follower transistor 131 and a select transistor 132;

The gate terminal of the source follower transistor 131 is connected with the signal processing module 12, the source terminal is connected with the selection transistor 132, and the drain terminal receives the power supply signal Vdd; for detecting and following the charge change of the floating diffusion region 121, and determining a target signal.

The drain terminal of the selection transistor 132 is connected to the source terminal of the source follower transistor 131, the source terminal is connected to the signal quantization module 12, the gate terminal receives the external control signal Φ _sel, and it is determined whether to output the target signal according to the control of the external control signal Φ _sel.

In this embodiment, the gate terminal of the source follower transistor 131 is connected to the signal processing module 12 and follows the potential change of the floating diffusion region 121 to obtain a potential signal, the process does not affect the photoelectric conversion of the photodiode 111, and on the premise that the first switch transistor 112 is turned off, the source follower transistor 131 reads the potential change of the floating diffusion region 121, and the photodiode 111 continues to perform photoelectric conversion to collect charges. The selection transistor 132 selects whether to output the target signal according to control of the external control signal Φ _sel, and the external control signal Φ _sel may be an external clock signal or an external pulse signal, etc.; the timing of the external control signal Φ _sel is set according to a specific scenario. Alternatively, the pixel selection transistor may be controlled to output the target signal based on the external control signal Φ _sel which is transmitted at regular time by the external clock circuit.

Fig. 5 is a schematic circuit diagram of a signal processing circuit according to an exemplary embodiment of the present disclosure. As shown in fig. 5, the signal processing circuit provided in this embodiment includes: a pixel array 510 consisting of m rows by n columns of sensor pixel units 511, and n by k column processors 520; wherein each column of m sensor pixel units 511 in the pixel array 510 corresponds to k column processors (for convenience of representation, only a schematic structure diagram with k being 1 is shown in the figure, and when k is an integer greater than 1, the connection relationship of other column processors is the same as that of the column processors); each column processor 520 corresponds to at least part of the circuitry of each sensor pixel cell 511 of the m sensor pixel cells 511 in a column; m, n and k are integers greater than or equal to 1.

Optionally, the signal acquisition module 11 in each sensor pixel unit 511 corresponds to one column processor 520; however, since the k signal acquisition modules 11 are connected to the signal processing module 12 and the signal output module 13, and the k signal acquisition modules 11 output the target signals through the output ports of the signal output module 13, each sensor pixel unit 511 corresponds to k column processors 520.

The output ends of the m image sensor pixel units 511 included in each column of the pixel array 510 are respectively connected to the input ends of the corresponding k column processors 520, and the input ends of the m image sensor pixel units 511 included in each column are respectively connected to the output ends of the corresponding k column processors 520.

The pixel array 510 is configured to quantize pixel signals for each row of the sensor pixel units 511 row by row according to control of an external control signal, output n target signals, and transmit the n target signals to n column processors, respectively.

In the present embodiment, the k signal acquisition modules 11 in each sensor pixel unit 511 sequentially perform the target signal output, that is, although the sensor pixel unit 511 has only one output terminal, since the k photodiodes 111 are integrated therein, the photoelectric charges acquired by the k signal acquisition modules 11 are sequentially output through k outputs. In this embodiment, each sensor pixel unit 511 is considered to be k pixel units in a row, but only output through one output port, that is, each row of the pixel array 510 can be understood to include n×k pixel units, but since each k pixel units corresponds to the same signal processing module and signal output module, the number of components in the sensor pixel unit is reduced, and the space occupied by the sensor pixel unit is greatly reduced.

The column processor 520 is configured to determine an encoded signal corresponding to the sensor pixel unit 510 according to the received target signal, and obtain a first feedback signal and a second feedback signal based on the encoded signal, and control the operation of the sensor pixel unit through the first feedback signal and the second feedback signal.

In this embodiment, the second switching transistor and the reset control transistor are disposed in the sensor pixel unit (hereinafter referred to as a pixel unit) 511, so that the pixel unit can realize the adjustable exposure time according to the received first feedback signal and the second feedback signal fed back by the column processor 520, and the exposure time of the sensor pixel unit in the dark light area can be adaptively increased, thereby improving the signal-to-noise ratio and the acquired image quality. In addition, the output of the pixel unit is controlled by the first feedback signal and the second feedback signal fed back by the column processor 520, so that the input of external signals is reduced, and the reset efficiency of the pixel unit is improved; and the number of components in the pixel unit is reduced, the size of the pixel unit is reduced, and the resolution of an image acquired by a sensor adopting the pixel unit is improved.

Fig. 6 is a schematic circuit diagram of a signal processing circuit provided in another exemplary embodiment of the present disclosure. As shown in fig. 6, the signal processing circuit provided in this embodiment further includes: n x k digital readout circuits 530 and n x k double sampling readout circuits 540.

Optionally, a row control unit 550 providing a first switching signal Φ _TXx, a second switching signal Φ _rstx, and an external control signal Φ _sel for each row of pixel units may be further included. The row control unit 550 sequentially transmits a first switching signal Φ _TXx, a second switching signal Φ _rstx and an external control signal Φ _sel with preset time sequences to each row of pixel units through preset logic, so as to realize exposure and reset control of the pixel units of the corresponding row.

Each digital readout circuit 530 is coupled to a column processor 520 for reading out the encoded signals at predetermined time intervals to obtain a digital sequence.

Alternatively, the digital sequence output by the digital readout circuit 530 is a sequence of 0's and 1's, for example, as shown in fig. 7a, for a particular point X in the imaging array, the digital sequence output by the digital readout circuit 530. Wherein time t0 represents the initial time, at which the transfer of the photoelectric charge of the photodiode in the pixel and the reset of the floating diffusion region are completed, so that the signals in the photodiode and the floating diffusion region are all cleared. The adjacent sampling time intervals are Δt (corresponding to preset time intervals), and each Δt time interval the digital readout circuit 530 outputs one high-order signal (1) or low-order signal (0), and the number of the low-order signals between the two high-order signals in the obtained digital sequence can represent the intensity of the light intensity of the specific point X corresponding to the current moment, alternatively, the more 0 between the two 1's indicates the weaker light intensity, and the less 0 between the two 1's indicates the stronger light intensity.

Each double sampling readout circuit 540 is connected to one column processor 520, and outputs an exposure charge amount when the encoding signal meets a preset condition.

In the pixel unit of the i-th row selected in the pixel array, the first switch signal Φ _TXx, the second switch signal Φ _rstx and the external control signal Φ _sel are high-level signals, the three other rows are set to be low-level signals, after each column reads out the target signal Vout output by the pixel unit, the height of the first feedback signal Φ _TXy and the second feedback signal Φ _rsty is determined according to the magnitude relation between the Vout signal and the reference signal Vth, and whether the double sampling readout circuit 540 of the corresponding column is enabled to output an analog voltage signal. Optionally, when Vout is greater than or equal to Vth, the digital readout circuit 530 outputs 0, the first feedback signal Φ _TXy and the second feedback signal Φ _TXy of the corresponding column pixel units are set to low level, the corresponding double sampling readout circuit 540 is turned off, no analog signal is output, and the i+1th row is continuously executed; when Vout is less than Vth, the digital readout circuit 530 outputs 1, the first feedback signal Φ _TXy and the second feedback signal Φ _rsty of the corresponding column of pixel cells are set to high level, the corresponding double sampling readout circuit 540 is enabled to output Vrst-Vsig, which represents the amount of exposure charge in the photodiode for a corresponding period of time, continuing to execute row i+1. For example, as shown in fig. 7b, referring to the digital sequence output in fig. 7a, it is known that the voltage output time closest to the start time has elapsed by 5 Δt, and the amount of charge accumulated on the photodiode during this time is characterized by Vs1, so the light intensity signal during this time is Vs1/5 Δt. The accumulation time at the time of the second readout is 3 Δt, the accumulated charge amount is Vs2, and the light intensity signal is Vs2/3 Δt. The third intensity signal may be characterized as Vs3/6Δt. And sequentially reading out the signal light intensity in each time period.

Fig. 8a is a schematic circuit diagram of a column processor in a signal processing circuit according to an exemplary embodiment of the present disclosure. As shown in fig. 8a, the column processor 520 includes: a comparator 521, a first and logic circuit 522, and a second and logic circuit 523.

The negative input end of the comparator 521 is connected with the output end of the sensor pixel unit 511 for receiving the target signal, the positive input end receives the reference signal Vth, and the output end outputs the encoded signal and is connected with the digital readout circuit; and the output terminal is connected to one input terminal of the first and logic circuit 522 and the second and logic circuit 523, respectively.

The first and logic circuit 522 has one input connected to the output of the comparator 521, the other input receiving the first external and signal Φ _and1, and the output outputting the first feedback signal Φ _TXy.

The second and logic circuit 523 has one input connected to the output of the comparator 521, the other input receiving the second external and signal Φ _and2, and the output outputting the second feedback signal Φ _rsty.

In this embodiment, the first feedback signal Φ _TXy and the second feedback signal Φ _rsty corresponding to the output of the and logic circuit based on the encoded signal output by the comparator are determined to realize the control of the exposure time in the sensor pixel unit by the column processor 520, alternatively, the first and logic circuit 522 and the second and logic circuit 523 are all and logic, and the corresponding operation rule is that only when both input ends are at high level, the high level is output, and the low level is output in other cases.

Fig. 8b is a schematic circuit diagram of a column processor in a signal processing circuit according to another exemplary embodiment of the present disclosure. As shown in fig. 8b, the column processor 520 further includes: third and logic 524.

The output terminal of the comparator 521 is further connected to one input terminal of the third and logic circuit 524, and the other input terminal of the third and logic circuit 524 receives the power supply signal Vdd; the output of the third AND logic circuit 524 is connected to the enable port en of the double sample readout circuit 540.

The input end of the double sampling readout circuit 540 is connected to the output end of the sensor pixel unit 511, and is used for receiving the target signal Vout, the enable port en is connected to the output end of the third and logic circuit 524, and when the third and logic circuit 524 outputs a high level, the double sampling readout circuit 540 processes the target signal Vout to obtain an exposure charge amount and outputs the exposure charge amount. In response to the third and logic circuit 524 outputting a low level, no analog signal is output.

The digital readout module is responsible for outputting a comparison result of the target signal Vout and the reference signal Vth, and the double-sampling readout circuit is responsible for outputting a double-sampled signal output result. According to the magnitude relation between the Vout signal and the reference signal Vth, it is determined whether the first feedback signal Φ _TXy and the second feedback signal Φ _rsty are high or low, and whether the double sampling readout circuit 540 of the corresponding column is enabled to output the analog voltage signal. Optionally, when Vout is greater than or equal to Vth, the digital readout circuit 530 outputs 0, the first feedback signal Φ _TXy and the second feedback signal Φ _rsty of the corresponding column pixel units are set to low level, the corresponding double sampling readout circuit 540 is turned off, no analog signal is output, and the i+1th row is continuously executed; when Vout is less than Vth, the digital readout circuit 530 outputs 1, the first feedback signal Φ _TXy and the second feedback signal Φ _rsty of the corresponding column of pixel cells are set to high level, the corresponding double sampling readout circuit 540 is enabled to output Vrst-Vsig, which represents the amount of exposure charge in the photodiode for a corresponding period of time, continuing to execute row i+1.

Fig. 9 is a timing diagram of signals of a signal processing circuit provided in an example according to an exemplary embodiment of the present disclosure. As shown in fig. 9, in the initial state, the reset transistor on the floating diffusion region 121 is turned on, and the voltage on the floating diffusion region 121 is charged to a high level. Under illumination conditions, photoelectric charges are generated in the photodiode 111 and the floating diffusion region 121, wherein the voltage on the floating diffusion region 121 gradually drops under the action of the photoelectric charges, the photoelectric charges on the photodiode 111 are limited in the depletion region of the photodiode 111 by the energy potential well, and when the first switching transistor is in an off state, the photo-generated charges in the photodiode 111 gradually accumulate.

The voltage on the floating diffusion region 121 is output to the outside through the source follower transistor 131 and the select transistor 132 for readout, when the voltage on the floating diffusion region 121 drops to a certain value (for example, vout is smaller than Vth before time T1 in fig. 9, i.e. corresponds to the timing chart of reaching the threshold condition in fig. 9), the following circuit actions are triggered after the output voltage Vout is lower than the reference signal Vth: t1, when the second switch signal phi _rstx and the second feedback signal phi _rsty are high level, the reset transistor 122 is closed, the floating diffusion region 121 is reset, and the voltage Vrst after the reset on the floating diffusion region 121 is read; t2, when the first switching signal Φ _TXy and the first feedback signal Φ _TXy are at high level, the first switching transistor 112 is turned on, transferring the charges accumulated in the photodiode 111 onto the floating diffusion 121, and reading out the voltage Vsig on the floating diffusion 121 at this time; t3, when the second switch signal Φ _rstx and the second feedback signal Φ _rsty are at high level, the reset transistor 122 is closed, the floating diffusion region 121 is reset, the reset transistor 122 is closed after the floating diffusion region 121 is reset, and the next time the threshold is reached for triggering. If the voltage on the readout floating diffusion region 121 has not fallen below the reference signal Vth (corresponding to the timing chart of the right half of fig. 9 where the threshold is not reached), which indicates that the accumulated light intensity has not reached a certain threshold, the circuit operation is not triggered to transfer the charge on the photodiode 111 into the floating diffusion region 121, and the floating diffusion region 121 continues to hold the accumulated charge. The state of application of the port voltages is as indicated in fig. 9 when the threshold condition is not reached, in which case the first feedback signal Φ _TXy and the second feedback signal Φ _rsty are always low, and the corresponding digital output circuit outputs 0.

The electronic device provided by the present disclosure may be incorporated as any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

The electronic device provided by the present disclosure may be applied to any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

Next, an electronic device according to an embodiment of the present disclosure is described with reference to fig. 10. The electronic device may be either or both of the first device and the second device, or a stand-alone device independent thereof, which may communicate with the first device and the second device to receive the acquired input signals therefrom.

As shown in fig. 10, the electronic device includes one or more processors and memory.

The processor may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device to perform the desired functions.

The memory may store one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program products may be stored on the computer readable storage medium that can be run by a processor to implement the sensor pixel units and/or other desired functions of the various embodiments of the present disclosure as described above.

In one example, the electronic device may further include: input devices and output devices, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).

In addition, the input device may include, for example, a keyboard, a mouse, and the like.

The output device may output various information including the determined distance information, direction information, etc., to the outside. The output device may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.

Of course, only some of the components of the electronic device relevant to the present disclosure are shown in fig. 10 for simplicity, components such as buses, input/output interfaces, and the like being omitted. In addition, the electronic device may include any other suitable components depending on the particular application.

The basic principles of the present disclosure have been described above in connection with specific embodiments, but it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present disclosure. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, since the disclosure is not necessarily limited to practice with the specific details described.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to. For system embodiments, the description is relatively simple as it essentially corresponds to method embodiments, and reference should be made to the description of method embodiments for relevant points.

The block diagrams of the devices, apparatuses, devices, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the disclosure to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims

1. A sensor pixel cell, comprising: k signal acquisition modules, signal processing modules and signal output modules; wherein k is an integer greater than or equal to 1;

2. The pixel cell of claim 1, wherein the signal acquisition module comprises: a photodiode and a first switching transistor;

3. The pixel cell of claim 2, wherein the signal acquisition module further comprises: a second switching transistor;

4. The pixel cell of claim 1, wherein the signal processing module comprises: a floating diffusion region, a reset transistor, and a reset control transistor;

The source end of the reset control transistor receives a second feedback signal, the gate end of the reset control transistor receives a second switching signal, and the drain end of the reset control transistor is connected with the gate end of the reset transistor;

The source terminal of the reset transistor is connected with the floating diffusion region, the drain terminal of the reset transistor receives a power supply signal, and the gate terminal of the reset transistor receives the second feedback signal through the reset control transistor.

5. The pixel cell of any one of claims 1-4, wherein the signal output module comprises: a source follower transistor and a select transistor;

6. A signal processing circuit, comprising: a pixel array of m rows by n columns of sensor pixel units according to any one of claims 1 to 5, and n x k column processors; wherein each of the column processors corresponds to at least part of the circuitry of each of m of the sensor pixel cells in a column; m and n are integers greater than or equal to 1 respectively;

The output ends of m sensor pixel units included in each column of the pixel array are respectively connected with the input ends of corresponding k column processors, and the input ends of m sensor pixel units included in each column are respectively connected with the output ends of corresponding k column processors.

7. The signal processing circuit of claim 6, further comprising: n x k digital readout circuits and n x k double sampling readout circuits;

8. The signal processing circuit of claim 7, wherein the column processor comprises: a comparator, a first AND logic circuit, and a second AND logic circuit;

The negative input end of the comparator is connected with the output end of the sensor pixel unit, the positive input end receives a reference signal, the output end is connected with a digital readout circuit, and the output end is respectively connected with one input end of the first AND logic circuit and one input end of the second AND logic circuit;

9. The signal processing circuit of claim 8, wherein the column processor further comprises: a third AND logic circuit;

10. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor, further comprising the sensor pixel unit of any one of claims 1-5 or the signal processing circuit of any one of claims 6-9;

The memory stores computer-executable instructions;

11. The electronic device of claim 10, wherein the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.