CN221151493U - Pulse sequence type sensor pixel unit, pulse sequence type sensor and equipment - Google Patents

Abstract

The embodiment of the disclosure discloses a pulse sequence type sensor pixel unit, a pulse sequence type sensor and equipment, wherein the pulse sequence type sensor pixel unit comprises: the pulse generation circuit, the connection circuit, the counter and the readout circuit; the pulse generating circuit is connected with the counter through the connecting circuit; the input end of the counter is connected with the pulse generating circuit through the connecting circuit, and the output end of the counter is connected with the reading circuit; the readout circuit is connected with the counter; according to the embodiment, the number of the input signals is accumulated through the counter, and the accumulated counting result is output through the reading circuit without outputting an original pulse sequence, so that lossless compression of output data is realized, the data quantity output by the pixel units can be reduced under the same frame rate, and higher frame rate can be realized under the same data bandwidth.

Description

Pulse sequence type sensor pixel unit, pulse sequence type sensor and equipment

Technical Field

The present disclosure relates to sensor technology, and more particularly, to a pulse train sensor pixel unit, a pulse train sensor, and a device.

Background

Image sensors have been widely used in the fields of digital cameras, mobile phones, medical treatment, automobiles, unmanned aerial vehicles, machine recognition, etc., and particularly, the rapid development of the technology for manufacturing complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors has led to higher demands on the quality of the output images of the image sensors. CMOS image sensors can be classified into two categories according to the signal acquisition mode: one way is to set the exposure time length for the pixels and then measure the voltage signal variation; the second method is a method of setting a voltage change amount for a pixel and measuring an exposure time period, and such an image sensor is called a pulse train type image sensor.

Disclosure of utility model

According to an aspect of the embodiments of the present disclosure, there is provided a pulse train sensor pixel unit including: the pulse generation circuit, the connection circuit, the counter and the readout circuit;

The pulse generating circuit is connected with the counter through the connecting circuit;

the input end of the counter is connected with the pulse generating circuit through the connecting circuit, and the output end of the counter is connected with the reading circuit;

the readout circuit is connected with the counter.

Optionally, the counter includes a first input and a second input;

The first input end is connected with a clock signal or the pulse generating circuit through the connecting circuit;

The second input end is connected with an external reset signal or the pulse generating circuit through the connecting circuit.

Optionally, the connection circuit includes: a first switch, a second switch, a third switch and a fourth switch connected in parallel with each other; the first switch and the second switch are not conducted simultaneously, and the third switch and the fourth switch are not conducted simultaneously;

two ends of the first switch are respectively connected with the external reset signal and the second input end of the counter;

two ends of the second switch are respectively connected with the pulse generating circuit and the second input end of the counter;

two ends of the third switch are respectively connected with the pulse generating circuit and the first input end of the counter;

and two ends of the fourth switch are respectively connected with the clock signal and the first input end of the counter.

Optionally, the pulse generating circuit comprises a photodiode, a reset transistor, a comparator and a reverse delay circuit;

One end of the photodiode is grounded, and the other end of the photodiode is connected with the drain electrode of the reset transistor and the negative input end of the comparator;

The source electrode of the reset transistor is connected with the power supply module, the drain electrode of the reset transistor is connected with the photodiode and the negative input end of the comparator, and the grid electrode of the reset transistor is connected with the reverse delay circuit;

The negative input end of the comparator is connected with the other end of the photodiode and the drain electrode of the reset transistor, the positive input end of the comparator is connected with an external reference signal, and the output end of the comparator is connected with the input end of the reverse delay circuit;

The input end of the reverse delay circuit is connected with the output end of the comparator, the output end of the reverse delay circuit is connected with the grid electrode of the reset transistor, and the output end of the reverse delay circuit is used as the output end of the pulse generating circuit.

According to another aspect of the disclosed embodiments, there is provided a pulse train sensor including: a plurality of pulse train sensor pixel units according to any of the above embodiments.

According to still another aspect of the embodiments of the present disclosure, there is provided an electronic device including: the processor, and the memory communicatively connected with the processor, further including the pulse sequence type sensor pixel unit according to any one of the above embodiments or the pulse sequence type sensor according to the above embodiment;

the memory stores computer-executable instructions;

The processor executes computer-executable instructions stored by the memory to control the operation of the pulse train sensor pixel unit or the pulse train sensor.

Optionally, the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.

The pulse sequence type sensor pixel unit, the pulse sequence type sensor and the device provided based on the above embodiments of the present disclosure, wherein the pulse sequence type sensor pixel unit includes: the pulse generation circuit, the connection circuit, the counter and the readout circuit; the pulse generating circuit is connected with the counter through the connecting circuit; the input end of the counter is connected with the pulse generating circuit through the connecting circuit, and the output end of the counter is connected with the reading circuit; the readout circuit is connected with the counter; according to the embodiment, the number of the input signals is accumulated through the counter, and the accumulated counting result is output through the reading circuit without outputting an original pulse sequence, so that lossless compression of output data is realized, the data quantity output by the pixel units can be reduced under the same frame rate, and higher frame rate can be realized under the same data bandwidth.

The technical scheme of the present disclosure is described in further detail below through the accompanying drawings and examples.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The disclosure may be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

Fig. 1 is a schematic diagram of a pulse train sensor pixel unit according to an exemplary embodiment of the present disclosure;

Fig. 2 is a schematic structural diagram of a pulse train sensor pixel unit according to another exemplary embodiment of the present disclosure;

FIG. 3 is a schematic circuit diagram of a pulse train sensor pixel unit in an operating mode according to an exemplary embodiment of the present disclosure;

FIG. 4 is a schematic diagram of signal timing corresponding to a pixel unit of a pulse train sensor in an operation mode according to an exemplary embodiment of the present disclosure;

FIG. 5 is a schematic circuit diagram of a pulse train sensor pixel unit in another mode of operation according to an exemplary embodiment of the present disclosure;

FIG. 6 is a schematic diagram of signal timing corresponding to a pulse train sensor pixel unit in another operation mode according to another exemplary embodiment of the present disclosure;

FIG. 7 is a schematic circuit diagram of a pulse generating circuit in a pixel cell of a pulse train sensor according to an exemplary embodiment of the present disclosure;

fig. 8 illustrates a block diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

Hereinafter, example embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be apparent that the described embodiments are only some of the embodiments of the present disclosure and not all of the embodiments of the present disclosure, and that the present disclosure is not limited by the example embodiments described herein.

It should be noted that: the relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless it is specifically stated otherwise.

It will be appreciated by those of skill in the art that the terms "first," "second," etc. in embodiments of the present disclosure are used merely to distinguish between different steps, devices or modules, etc., and do not represent any particular technical meaning nor necessarily logical order between them.

It should also be understood that in embodiments of the present disclosure, "plurality" may refer to two or more, and "at least one" may refer to one, two or more.

It should also be appreciated that any component, data, or structure referred to in the presently disclosed embodiments may be generally understood as one or more without explicit limitation or the contrary in the context.

In addition, the term "and/or" in this disclosure is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" in the present disclosure generally indicates that the front and rear association objects are an or relationship. The data referred to in this disclosure may include unstructured data, such as text, images, video, and the like, as well as structured data.

It should also be understood that the description of the various embodiments of the present disclosure emphasizes the differences between the various embodiments, and that the same or similar features may be referred to each other, and for brevity, will not be described in detail.

Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.

Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

In implementing the present disclosure, the inventors have found that a pulse sequence image sensor in the prior art directly outputs a pulse sequence outwards, and the pulse sequence is encoded by an off-chip processor, so as to embody a color gray value of a pixel signal. The pulse sequence generated by the pixel unit consists of 0 and 1, the light intensity is reflected by the number of 0 at the interval between every two 1, when the light intensity is weaker, the more the number of 0 between the two 1 in the pulse sequence is, the more sparse the information is, and the excessive bandwidth is occupied; on the other hand, the upper limit of the speed of the full line scanning limits the upper limit of the frame rate.

Fig. 1 is a schematic diagram of a pulse train sensor pixel unit according to an exemplary embodiment of the present disclosure. As shown in fig. 1, a pulse train sensor pixel unit (hereinafter, may be abbreviated as a pixel unit) provided in this embodiment includes: a pulse generating circuit 11, a connecting circuit 12, a counter 13, and a readout circuit 14;

The pulse generating circuit 11 is connected with the counter 13 through the connecting circuit 12; the pulse generating circuit 11 is configured to convert the received optical signal into a pulse signal and send the pulse signal to the counter 13.

Alternatively, the main component in the pulse generation circuit 11 may be a photoelectric conversion element (for example, an element that can convert light energy into electric energy such as a photodiode) by which photoelectric conversion is achieved, and electric charges are obtained based on the conversion; the pulse generating circuit 11 may be provided with an element that resets the photoelectric conversion element, and the photoelectric conversion element may be reset by the reset element.

The counter 13 has an input connected to the pulse generating circuit 11 via the connection circuit 12 and an output connected to the readout circuit 14.

The counter 12 in this embodiment may be any counter or counter implementation capable of implementing a counting function in the prior art, for example, the counter may be any one of digital circuit modules such as a counter, a frequency divider, a digital memory, a register, a latch, etc., and the disclosure is not limited to the specific circuit structure of the counter 12.

The readout circuit 14 is connected with the counter 13; and a reading circuit 14 for reading the count result in the counter 13 and outputting the result in accordance with the control of the reading control signal.

Optionally, the counting result is binary data with preset digits or data recorded by other counting methods with preset digits; the preset bit number can be set according to an actual application scene, and the number of the signals input to the first input end of the counter 13 is only output by counting the binary system data and other methods, and the original pulse sequence is not output, so that lossless compression of output data is realized, the data quantity output by the pixel units can be reduced under the same frame rate, and higher frame rate can be realized under the same data bandwidth.

The pulse sequence type sensor pixel unit provided by the above embodiment of the present disclosure includes: the pulse generation circuit, the connection circuit, the counter and the readout circuit; the pulse generating circuit is connected with the counter through the connecting circuit; the input end of the counter is connected with the pulse generating circuit through the connecting circuit, and the output end of the counter is connected with the reading circuit; the readout circuit is connected with the counter; according to the embodiment, the number of the input signals is accumulated through the counter, and the accumulated counting result is output through the reading circuit without outputting an original pulse sequence, so that lossless compression of output data is realized, the data quantity output by the pixel units can be reduced under the same frame rate, and higher frame rate can be realized under the same data bandwidth.

Fig. 2 is a schematic structural diagram of a pulse train sensor pixel unit according to another exemplary embodiment of the present disclosure. As shown in fig. 2, in the pulse train sensor pixel unit provided in the embodiment of the present disclosure, the counter 13 includes a first input end 131 and a second input end 132;

The first input 131 is connected to the clock signal or pulse generating circuit 11 through the connection circuit 12;

The second input 132 is connected to the external reset signal or pulse generating circuit 11 via the connection circuit 12.

In this embodiment, the first input end 131 is a count input end (input), and the counter 13 counts the signals input by the first input end 131; and the second input terminal 132 is a reset terminal (reset), the counter 13 performs reset according to a signal input from the second input terminal 132.

The connection module 12 includes: a first switch 121, a second switch 122, a third switch 123, and a fourth switch 124 connected in parallel with each other. Wherein the first switch 121, the second switch 122, the third switch 123 and the fourth switch 124 are connected in parallel to form a switch array; the first switch 121 and the second switch 122 are not turned on at the same time, and the third switch 123 and the fourth switch 124 are not turned on at the same time.

The first switch 121 and the third switch 123 control the conduction of the first input of the counter 12, and the second switch 122 and the fourth switch 124 control the conduction of the second input of the counter 12.

Two ends of the first switch 121 are respectively connected with an external reset signal read_DN and a second input end 132 of the counter;

Both ends of the second switch 122 are respectively connected with the pulse generating circuit 11 and the second input end 132 of the counter;

both ends of the third switch 123 are respectively connected to the pulse generating circuit 11 and the first input terminal 131 of the counter;

Both ends of the fourth switch 124 are connected to the clock signal clk and the first input 131 of the counter, respectively.

The connection circuit 12 is used for determining the first connection mode or the second connection mode according to the counting result output by the reading circuit last time. The pulse generating circuit 11 is in communication with the first input 131 of the counter in the first communication mode, and the pulse generating circuit 11 is in communication with the second input 132 of the counter in the second communication mode.

In this embodiment, since the counter 13 counts the signals input to the first input end, the counter 13 directly counts the number of pulse signals generated by the pulse generating circuit 11 (the first communication mode) through the control of the connection module, and the first communication mode is more suitable for counting the light signals with stronger light intensity. Or the pulse signals are used as reset signals (second communication mode), the existing signals with known frequency are counted in one pulse signal, in the second communication mode, each pulse signal can be expressed according to the counting result output by the counter each time, the light signals with weaker light intensity can be expressed (the pulse sequence generated by the pixel unit consists of 0 and 1, the light intensity is reflected according to the number of 0 in the interval between every two 1, when the light intensity is weaker, the number of 0 in the pulse sequence is more, the intensity of the light signals corresponding to the pulse signals can be known according to the number of the known signals corresponding to each pulse signal, the larger the counting result corresponding to the pulse signals is, the weaker the light intensity corresponding to the pulse signals is, the smaller the counting result corresponding to the pulse signals is, and the stronger the light intensity corresponding to the pulse signals is.

As shown in fig. 3, when the first switch 121 and the third switch 123 are closed in the first communication mode, the second switch 122 and the fourth switch 124 are opened, an external reset signal is input to the second input terminal of the counter 13 through the first switch 121, and a pulse signal is input to the first input terminal of the counter 13 through the third switch 123.

In this embodiment, the first switch 121 connects an external reset signal to the second input end of the counter 13, where the external reset signal has a preset period, and outputs a high level every preset time period to control the counter 13 to execute reset; the pulse signal is connected to the first input terminal of the counter 13 through the third switch 123, the counter 13 restarts counting the number of pulse signals input by the first input terminal after each reset, and the number of pulse signals included in the preset period is determined as a counting result.

Alternatively, in response to the communication circuit 12 being in the first communication mode, the counter 13 receives the pulse signal through the first input terminal, and determines a count result based on the number of inversions of the pulse signal recorded in the preset period to output to the readout circuit according to control of the readout control signal of the readout circuit 14 every preset period.

The present embodiment realizes that the number of pulse signals received by the counter 13 is recorded in each preset period, and this number can be determined by the number of times of inversion of the pulse signals, for example, the data in the counter 13 is incremented by one every two times the pulse signals are inverted (usually, two times of inversion from low level to high level and then from high level to low level are recorded). In the first communication mode, when the counter 13 is operated, as shown in fig. 3, the input terminal (the first input terminal 131) is connected to the pulse generating circuit, the reset terminal (the second input terminal 132) is connected to the external reset (read_dn) signal, the read_dn signal is used to indicate that the counter is Read out, and the signal width is equal to the read_en signal when the Read control (read_en) signal rises along the falling edge. In the process of receiving illumination, the pulse generating circuit counts the turnover times of the pulse signal by the counter, and counts up one counter every two times of turnover, and resets the photoelectric acquisition component (for example, photodiode) in the pulse generating circuit 11 (acquires the next pulse signal after reset).

Alternatively, the counter 13 receives the external reset signal read_dn through the second input terminal 132, and performs reset according to control of the external reset signal after outputting the count result.

When pixel pulse frequency coding is carried out on a pixel array (including pixel units of a plurality of rows and a plurality of columns) in the pulse array sensor, the pixel array is read out in a synchronous mode, namely the whole pixel array is scanned and read out in a row mode at a fixed frequency; when the line scanning signal reaches a line of pixel units in the pixel array, the read_EN signal is set to be high level, the counter stops counting, and the pixel units output a counting result through the reading circuit; after the Read is completed, the read_en signal is set to low, and the counter is reset, and the cycle is performed.

Fig. 4 is a schematic signal timing diagram corresponding to a pulse train sensor pixel unit in an operation mode according to an exemplary embodiment of the present disclosure. As shown in fig. 4, in this example, only a partial timing chart of the readout control signal read_en, the external reset signal read_dn, the comparison signal S1, and the pulse signal DC in one example case, and the count result output by the counter are shown for understanding the relationship between the signals only, and are not used to limit the specific timing cases of the signals of the present disclosure, for convenience of understanding; based on the timing chart shown in fig. 4, the external reset signal is triggered after the control signal is read out, and the pulse signal has a certain delay relative to the comparison signal.

The original pulse sequence provided in the prior art reflects the light intensity through the pulse interval, the minimum time of the pulse interval is the time of complete scanning and reading of the array, and for strong light enough to enable the pixel unit to generate a plurality of pulse signals in one scanning time, the strong light exceeds the range capable of being described by the original pulse sequence, and the prior art cannot process the strong light. According to the embodiment of the disclosure, the pulse frequency is encoded in the pixel unit through the counter, so that the number of pulse signals generated by the pixel unit in one round of scanning time can be recorded, and the technical effect of describing the light signals with stronger light intensity is achieved.

As shown in fig. 5, when the second switch 122 and the fourth switch 124 are closed in the second communication mode, the first switch 121 and the third switch 123 are opened, the pulse signal is input to the second input terminal of the counter 13 through the second switch 122, and the external clock signal is input to the first input terminal of the counter 13 through the fourth switch 124.

The pulse signal is connected to the second input terminal of the counter 13 through the second switch 122, at this time, the pulse signal is used as a reset signal of the counter 13, and the counter 13 performs reset every time the pulse signal outputs a high level (output is 1); the external clock signal is connected to the first input end of the counter 13 through the fourth switch, the counter 13 restarts to count the number of the clock signals input by the first input end after reset each time, the number of the external clock signals corresponding to the pulse signals is determined as a counting result, and the counting result can determine the time interval generated by the pulse signals.

In this embodiment, an encoding mode automatic control module may be used inside or outside the sensor chip, to detect the counting result output by the readout circuit, and automatically control the switching between the first communication mode and the second communication mode according to the detection result.

Alternatively, in response to the communication circuit 12 being in the second communication mode, the external clock signal is received through the first input terminal 131, and the count result corresponding to the number of inversions of the external clock signal accumulated in the counter 13 is output to the readout circuit according to control of the readout control signal of the readout circuit 14.

The embodiment realizes that the counter counts the pulse width time corresponding to each pulse signal, and the counting result represents the turnover number of the external clock signal with fixed frequency in each pulse signal; for example, the data in the counter is incremented by one every two times the external clock signal toggles (typically recording two toggles from low to high and then from high to low). In the second communication mode, when the counter works, as shown in fig. 5, the reset terminal (the second input terminal) is connected with a pulse signal output by the pulse generating circuit, the input terminal (the first input terminal) of the counter 12 is connected to an external clock signal clk with a fixed frequency provided externally, the counter 12 counts the turnover number of the external clock signal in the process of receiving illumination, when the pulse signal is generated, the counter 12 stops counting according to the control of the pulse signal, the pixel unit sends a readout request to the peripheral circuit, the peripheral circuit sets a readout control signal read_en to be at a high level after the request is completed, the count result and the pixel coordinate are Read, and the count result of the counter 12 is a time interval from last reset to the generation of the current pulse signal.

Alternatively, the counter 13 receives a pulse signal through the second input terminal 132, and after outputting the count result, performs reset according to control of the pulse signal.

After the counter 13 outputs the count result, the Read control signal read_en signal is set to low level, and both the pulse generating circuit 11 and the counter 13 are reset, and the next pulse signal is continuously counted, and the cycle is thus repeated.

Alternatively, the readout circuit 14 is configured to determine a state of the readout control signal based on the pulse signal, and control the readout circuit 14 to read the count result of the counter 13 in response to the state of the readout control signal being the readout state.

In this embodiment, the pixel array (including pixel units in a plurality of rows and columns) in the pulse array sensor is read asynchronously, that is, the pixel units output the counting result and the pixel coordinates when generating the pulse signal. The original pulse sequence provided in the prior art shows the pulse interval by the number of zero levels, the wider the interval is, the wider the data bit width is output, and the counting result after the pixel unit provided by the embodiment encodes the pulse signal is a binary number with a fixed bit number, the data bit width is fixed, and the data quantity is compressed. For example, the original pulse sequence needs 100 pulse intervals represented by 0 s, and only needs to be output 01100100 after binary encoding is performed by an 8-bit counter, so that the output data quantity is greatly compressed.

Fig. 6 is a schematic signal timing diagram corresponding to a pulse train sensor pixel unit in another operation mode according to another exemplary embodiment of the present disclosure. As shown in fig. 6, in this example, only a partial timing chart of the readout control signal read_en, the external clock signal clk, the comparison signal S1, and the pulse signal DC in one example case is shown for ease of understanding, and the count result output by the counter is only used for understanding the relationship between signals, and is not used for limiting the specific timing cases of the signals of the present disclosure; as can be seen from the timing chart shown in fig. 6, the Read control signal read_en is synchronized with the comparison signal S1, the pulse signal DC has a certain delay with respect to the comparison signal S1, and the count results accumulate the number of times of toggling of the external clock signal clk between the two high levels of the pulse signal DC output.

Optionally, in an optional example, the connection module 12 may further include: a status recognition module (not shown);

A state recognition module for switching from the first communication mode to the second communication mode in response to the count result last outputted by the readout circuit 14 reaching a first preset condition; and switching from the second communication mode to the first communication mode in response to the count result last output by the reading circuit reaching a second preset condition.

Optionally, the first preset condition may be that a count result exceeding a first proportion in the plurality of sets of count results is less than or equal to 1; the second preset condition may be that the count result exceeding the second proportion in the plurality of sets of count results is less than or equal to 1; alternatively, the first ratio and the second ratio may be the same or different.

Optionally, in some optional examples, the first switch 121 and the third switch 123 may be N-type transistors, and the corresponding second switch 122 and fourth switch 124 are P-type transistors (or the first switch 121 and the third switch 123 may be P-type transistors, and the corresponding second switch 122 and fourth switch 124 are N-type transistors); the corresponding state recognition module recognizes and outputs a corresponding high level or low level according to the condition to realize the control of opening and closing of each switch, for example, when the state recognition module recognizes that the counting result reaches the first preset condition, the state recognition module outputs the low level to the first switch 121, the second switch 122, the third switch 123 and the fourth switch 124; the P-type transistor is controlled to be turned on, the N-type transistor is controlled to be turned off, and the switching from the first communication mode to the second communication mode is realized; for another example, when the state recognition module recognizes that the count result reaches the second preset condition, a high level is output to the first switch 121, the second switch 122, the third switch 123, and the fourth switch 124; the P-type transistor is controlled to be disconnected, and the N-type transistor is controlled to be conducted, so that the switching from the second communication mode to the first communication mode is realized.

In this embodiment, whether the communication mode needs to be adjusted is determined according to the counting result, when the communication mode is in the first communication mode, when it is detected that the counting result exceeding the first proportion (for example, 50%, 60% and the like, the specific proportion can be selected according to the actual scene) in the plurality of groups of counting results outputted by the readout circuit is less than or equal to 1, because the counting result indicates the number of pulse signals generated in a fixed time interval, the data less than or equal to 1 indicates that no pulse signal or only one pulse signal is generated in the time interval, and the data exceeding the first proportion in the plurality of groups of counting results is less than or equal to 1, that is, the light intensity is weak, and at this time, the communication mode is switched from the first communication mode to the second communication mode. When the second communication mode is in the second communication mode, when the counting result of the plurality of groups of counting results output by the reading circuit exceeds a second proportion (for example, 50%, 60% and the like, the specific proportion can be selected according to the actual scene) by less than or equal to 1, the counting result indicates that the time interval between the two pulses is smaller, the stronger the light intensity is indicated by the smaller time interval, the counting result is less than or equal to 1, the smaller time interval between the two pulses is indicated by the smaller time interval, and when the counting result exceeding the second proportion in the plurality of groups of technical results is less than or equal to 1, the light intensity is indicated by the stronger time interval, and the second communication mode is switched to the first communication mode.

Fig. 7 is a circuit schematic diagram of a pulse generating circuit in a pixel unit of a pulse train sensor according to an exemplary embodiment of the present disclosure. As shown in fig. 7, the pulse generating circuit 11 includes: a photodiode 111, a reset transistor 112, a comparator 113, and an inverse delay circuit 114;

The anode of the photodiode 111 is grounded Vss, and the cathode is connected to the drain of the reset transistor 112 and the negative input terminal of the comparator 113; and, the connection terminal of the photodiode 111 and the drain electrode of the reset transistor 112 is used for outputting a charge signal; receiving an optical signal to generate an opto-electric charge for an exposure period while the reset transistor 112 is turned off; when the reset transistor 112 is closed, reset is performed.

A photodiode is a photodetector capable of converting light into a current or voltage signal depending on the manner of use. The die often uses a PN junction with photosensitive characteristics, is very sensitive to light changes, has unidirectional conductivity, and changes electrical characteristics when different light intensities are used, so that the intensity of the light can be used to change the voltage or current in the circuit.

The source of the reset transistor 112 is connected to the power supply module Vdd, the drain is connected to the photodiode 111 and the negative input terminal of the comparator 113, and the gate is connected to the reverse delay circuit 114; for controlling on or off of the pulse signal transmitted from the reverse delay circuit 114 and controlling whether or not the photodiode 111 is on with the power supply module Vdd by the on or off of the reset transistor 112.

Alternatively, the reset transistor 112 is turned on or off according to control of the pulse signal output by the inverse delay circuit 114, for example, when the pulse signal is at a high level, the reset transistor 112 is turned on, and the photodiode 111 is controlled to be reset (the reset signal is a voltage signal of the voltage module); when the pulse signal is at a low level, the reset transistor 112 is turned off, and the photodiode 111 is controlled to stop reset, thereby starting to collect the optical signal.

The negative input end of the comparator 113 is connected with the other end of the photodiode 111 and the drain electrode of the reset transistor 112, the positive input end of the comparator 113 is connected with an external reference signal Vth, and the output end of the comparator 113 is connected with the input end of the inverse delay circuit 114;

alternatively, the comparison between the charge signal and the reference signal Vth is implemented by the comparator 113, and when the charge signal is smaller than the reference signal Vth, the comparison signal output from the output terminal is at a high level; when the charge signal is greater than the reference signal Vth, the comparison signal output by the output terminal is at a low level; optionally, the reference signal Vth is a voltage signal that is less than the power supply module voltage Vdd.

An input terminal of the inverse delay circuit 114 is connected to an output terminal of the comparator 113, an output terminal is connected to a gate of the reset transistor 112, and an output terminal of the inverse delay circuit 114 serves as an output terminal of the pulse generating circuit 11.

The inverse delay circuit 114 delays the comparison signal for a preset period of time, and sends the obtained pulse signal to the counter 13 and the reset transistor 112.

Optionally, the reverse delay circuit 114 may be a circuit that implements a delay of a preset duration, such as an inverse delay chain, and the embodiment does not limit the circuit structure of the reverse delay circuit 114, so long as a delay function can be implemented, and the specific preset duration may be set according to an actual application situation; the inverse delay circuit 114 in the present embodiment is used only for delay and does not perform any other processing on the comparison signal, and therefore, the pulse signal output from the inverse delay circuit 114 and the comparison signal output from the comparator 113 are delayed in time sequence only.

In this embodiment, after the photodiode 111 stops resetting, the exposure collection optical signal starts, the voltage Vpd of the photodiode starts to drop from the reset voltage Vdd, when the voltage Vpd of the photodiode drops to the reference signal Vth, the comparison signal S1 output by the comparator 113 becomes high level, a pulse is generated, a high level pulse signal is obtained after the delay processing of the inverse delay circuit 114, at this time, the reset transistor 112 is turned on, the photodiode 111 is reset, and the cycle is thus repeated.

In another aspect of the embodiments of the present disclosure, there is also provided a pulse train type sensor including: a plurality of pulse train sensor pixel units according to any of the above embodiments.

The electronic device provided by the present disclosure may be incorporated as any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

The electronic device provided by the present disclosure may be applied to any one of the following: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices, and the like.

Next, an electronic device according to an embodiment of the present disclosure is described with reference to fig. 8. The electronic device may be either or both of the first device and the second device, or a stand-alone device independent thereof, which may communicate with the first device and the second device to receive the acquired input signals therefrom.

Fig. 8 illustrates a block diagram of an electronic device according to an embodiment of the disclosure.

As shown in fig. 8, the electronic device includes one or more processors and memory.

The processor may be a Central Processing Unit (CPU) or other form of processing unit having data processing and/or instruction execution capabilities, and may control other components in the electronic device to perform the desired functions.

The memory may store one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program products may be stored on the computer readable storage medium that can be run by a processor to implement the workflow and/or other desired functions of the pulse train sensor pixel unit of the various embodiments of the present disclosure described above.

In one example, the electronic device may further include: input devices and output devices, which are interconnected by a bus system and/or other forms of connection mechanisms (not shown).

In addition, the input device may include, for example, a keyboard, a mouse, and the like.

The output device may output various information including the determined distance information, direction information, etc., to the outside. The output device may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.

Of course, only some of the components of the electronic device relevant to the present disclosure are shown in fig. 8, components such as buses, input/output interfaces, and the like are omitted for simplicity. In addition, the electronic device may include any other suitable components depending on the particular application.

The basic principles of the present disclosure have been described above in connection with specific embodiments, but it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are merely examples and not limiting, and these advantages, benefits, effects, etc. are not to be considered as necessarily possessed by the various embodiments of the present disclosure. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, since the disclosure is not necessarily limited to practice with the specific details described.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different manner from other embodiments, so that the same or similar parts between the embodiments are mutually referred to. For system embodiments, the description is relatively simple as it essentially corresponds to method embodiments, and reference should be made to the description of method embodiments for relevant points.

The block diagrams of the devices, apparatuses, devices, systems referred to in this disclosure are merely illustrative examples and are not intended to require or imply that the connections, arrangements, configurations must be made in the manner shown in the block diagrams. As will be appreciated by one of skill in the art, the devices, apparatuses, devices, systems may be connected, arranged, configured in any manner. Words such as "including," "comprising," "having," and the like are words of openness and mean "including but not limited to," and are used interchangeably therewith. The terms "or" and "as used herein refer to and are used interchangeably with the term" and/or "unless the context clearly indicates otherwise. The term "such as" as used herein refers to, and is used interchangeably with, the phrase "such as, but not limited to.

The methods and apparatus of the present disclosure may be implemented in a number of ways. For example, the methods and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, firmware. The above-described sequence of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the sequence specifically described above unless specifically stated otherwise. Furthermore, in some embodiments, the present disclosure may also be implemented as programs recorded in a recording medium, the programs including machine-readable instructions for implementing the methods according to the present disclosure. Thus, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

It is also noted that in the apparatus, devices and methods of the present disclosure, components or steps may be disassembled and/or assembled. Such decomposition and/or recombination should be considered equivalent to the present disclosure.

The previous description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the aspects shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The foregoing description has been presented for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the disclosure to the form disclosed herein. Although a number of example aspects and embodiments have been discussed above, a person of ordinary skill in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims (7)

1. A pulse train sensor pixel cell, comprising: the pulse generation circuit, the connection circuit, the counter and the readout circuit;

The pulse generating circuit is connected with the counter through the connecting circuit;

the input end of the counter is connected with the pulse generating circuit through the connecting circuit, and the output end of the counter is connected with the reading circuit;

the readout circuit is connected with the counter.

2. The pixel cell of claim 1, wherein the counter comprises a first input and a second input;

The first input end is connected with a clock signal or the pulse generating circuit through the connecting circuit;

The second input end is connected with an external reset signal or the pulse generating circuit through the connecting circuit.

3. The pixel cell of claim 2, wherein the connection circuit comprises: a first switch, a second switch, a third switch and a fourth switch connected in parallel with each other; the first switch and the second switch are not conducted simultaneously, and the third switch and the fourth switch are not conducted simultaneously;

two ends of the first switch are respectively connected with the external reset signal and the second input end of the counter;

two ends of the second switch are respectively connected with the pulse generating circuit and the second input end of the counter;

two ends of the third switch are respectively connected with the pulse generating circuit and the first input end of the counter;

and two ends of the fourth switch are respectively connected with the clock signal and the first input end of the counter.

4. A pixel cell according to any one of claims 1-3, wherein the pulse generating circuit comprises a photodiode, a reset transistor, a comparator and a reverse delay circuit;

One end of the photodiode is grounded, and the other end of the photodiode is connected with the drain electrode of the reset transistor and the negative input end of the comparator;

The source electrode of the reset transistor is connected with the power supply module, the drain electrode of the reset transistor is connected with the photodiode and the negative input end of the comparator, and the grid electrode of the reset transistor is connected with the reverse delay circuit;

The negative input end of the comparator is connected with the other end of the photodiode and the drain electrode of the reset transistor, the positive input end of the comparator is connected with an external reference signal, and the output end of the comparator is connected with the input end of the reverse delay circuit;

The input end of the reverse delay circuit is connected with the output end of the comparator, the output end of the reverse delay circuit is connected with the grid electrode of the reset transistor, and the output end of the reverse delay circuit is used as the output end of the pulse generating circuit.

5. A pulse train sensor, comprising: a plurality of pulse train sensor pixel units according to any one of claims 1-4.

6. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor, further comprising a pulse train sensor pixel unit according to any one of claims 1-4 or a pulse train sensor according to claim 5;

the memory stores computer-executable instructions;

The processor executes computer-executable instructions stored by the memory to control the operation of the pulse train sensor pixel unit or the pulse train sensor.

7. The electronic device of claim 6, wherein the electronic device is incorporated as any one of: pulse cameras, high-speed cameras, audio/video players, navigation devices, fixed location terminals, entertainment units, smartphones, communication devices, devices in motor vehicles, cameras, motion or wearable cameras, detection devices, flight devices, medical devices, security devices.