CN221303773U - Array substrate and display panel - Google Patents
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- CN221303773U CN221303773U CN202323367535.6U CN202323367535U CN221303773U CN 221303773 U CN221303773 U CN 221303773U CN 202323367535 U CN202323367535 U CN 202323367535U CN 221303773 U CN221303773 U CN 221303773U
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Abstract
The utility model provides an array substrate and a display panel, wherein the array substrate comprises a plurality of sub-pixel columns and a plurality of data lines which are arranged on a substrate, and a first data line and a second data line are arranged between two adjacent columns of sub-pixel columns; the first data line comprises a plurality of first sub-lines and second sub-lines connected between two adjacent first sub-lines, and the first sub-lines and the second sub-lines are arranged on different layers; the second data line comprises a plurality of third sub-lines and a fourth sub-line connected between two adjacent third sub-lines, and the third sub-line and the fourth sub-line are arranged on different layers; the first sub-line and the third sub-line are arranged on the same layer, the first sub-line corresponds to the fourth sub-line, the second sub-line corresponds to the third sub-line, so that sub-line parts which are positioned on the same layer in two adjacent data lines are staggered, the risk of short circuit of the two adjacent data lines is reduced, the yield is improved, and the technical problem that the yield is lower in the existing display panel adopting HG2D architecture pixel design is solved.
Description
Technical Field
The utility model relates to the technical field of display, in particular to an array substrate and a display panel.
Background
With the development of display technology, in a large-size display panel with high refresh rate and high resolution, such as 120Hz and 8K pixels, the resolution of the display panel is larger and larger, and the refresh frequency is higher and higher, so that the charging time of the display panel is greatly shortened, and in order to increase the charging time, the pixel design of HG2D (two data) architecture is adopted at present. That is, the structure of a row of sub-pixels corresponding to two data lines changes the charging time to 2 times of the original charging time, so that the problem of insufficient charging rate is well solved, however, the display panel adopting HG2D architecture pixel design has the problem of lower yield.
Disclosure of utility model
The utility model provides an array substrate and a display panel, which are used for solving the technical problem of low yield of the existing display panel adopting HG2D architecture pixel design.
In order to solve the problems, the technical scheme provided by the utility model is as follows:
The embodiment of the utility model provides an array substrate, which comprises a substrate and a plurality of sub-pixels arranged on the substrate in an array manner, wherein the sub-pixels are arranged into sub-pixel rows in a first direction, and the sub-pixels are arranged into sub-pixel columns in a second direction;
The array substrate further comprises a plurality of data lines arranged on the substrate, the data lines extend along the second direction and are distributed at intervals along the first direction, two data lines are arranged between two adjacent rows of sub-pixel rows, and the two data lines are a first data line and a second data line;
The first data line comprises a plurality of first sub-lines which are arranged at intervals in the second direction and a second sub-line which is connected between two adjacent first sub-lines, and the first sub-lines and the second sub-lines are arranged on different layers; the second data line comprises a plurality of third sub-lines which are arranged at intervals in the second direction and a fourth sub-line which is connected between two adjacent third sub-lines, and the third sub-line and the fourth sub-line are arranged on different layers; the first sub-line and the third sub-line are arranged in the same layer, the first sub-line is arranged corresponding to the fourth sub-line, and the second sub-line is arranged corresponding to the third sub-line.
In the array substrate provided by the embodiment of the utility model, the sub-pixels in each sub-pixel column are connected with the adjacent first data line and second data line.
In the array substrate provided by the embodiment of the utility model, in two adjacent sub-pixel columns and the first data line and the second data line between the two adjacent sub-pixel columns, the first data line is connected with one of the two adjacent sub-pixel columns, and the second data line is connected with the other of the two adjacent sub-pixel columns.
In the array substrate provided by the embodiment of the utility model, in the same sub-pixel column, one of two adjacent sub-pixels is connected with the first data line, and the other sub-pixel is connected with the second data line.
In the array substrate provided by the embodiment of the utility model, in the first direction, the sub-pixel connected with the first data line is located between the adjacent first sub-line and fourth sub-line and is connected with the first sub-line; the sub-pixel connected to the second data line is located between the adjacent second sub-line and the third sub-line and is connected to the third sub-line.
In the array substrate provided by the embodiment of the utility model, orthographic projections of the first sub-line and the third sub-line in the first direction are separated; or orthographic projections of the second sub-line and the fourth sub-line in the first direction are separated.
In the array substrate provided by the embodiment of the utility model, each sub-pixel comprises a transistor and a pixel electrode connected with the transistor, the pixel electrode is positioned at one side of the transistor far away from the substrate, the first sub-line and the third sub-line are arranged on the same layer as part of the metal layer of the transistor, and the second sub-line and the fourth sub-line are arranged on the same layer as the pixel electrode.
In the array substrate provided by the embodiment of the utility model, in the first direction, the width of the second sub-line is larger than the width of the first sub-line, and the width of the fourth sub-line is larger than the width of the third sub-line.
In the array substrate provided by the embodiment of the utility model, the array substrate further comprises a plurality of scanning lines arranged on the substrate, the plurality of scanning lines extend along the first direction, one scanning line is arranged between two adjacent sub-pixel rows, and each scanning line is connected with all the sub-pixels in the same sub-pixel row; and in two adjacent scanning lines, one scanning line has an overlapping area with the adjacent first sub-line and the adjacent fourth sub-line, and the other scanning line has an overlapping area with the adjacent second sub-line and the adjacent third sub-line.
The embodiment of the utility model also provides a display panel, which comprises the array substrate of one of the above embodiments.
The beneficial effects of the utility model are as follows: in the array substrate and the display panel provided by the utility model, the array substrate comprises a plurality of data lines arranged on the substrate, the plurality of data lines extend along a second direction and are distributed at intervals along the first direction, two data lines are arranged between two adjacent rows of sub-pixel columns, and the two data lines are a first data line and a second data line; the first data line comprises a plurality of first sub-lines which are arranged at intervals in the second direction and a second sub-line which is connected between two adjacent first sub-lines, and the first sub-lines and the second sub-lines are arranged on different layers; the second data line comprises a plurality of third sub-lines which are arranged at intervals in the second direction and a fourth sub-line which is connected between two adjacent third sub-lines, and the third sub-line and the fourth sub-line are arranged on different layers; the first sub-line and the third sub-line are arranged on the same layer, the first sub-line corresponds to the fourth sub-line, the second sub-line corresponds to the third sub-line, so that sub-line parts positioned on the same layer in two adjacent data lines are staggered, the risk of short circuit of the two adjacent data lines is reduced, the yield is improved, and the technical problem that the yield is lower in the existing display panel adopting HG2D architecture pixel design is solved.
Drawings
In order to more clearly illustrate the embodiments or the technical solutions in the prior art, the following description will briefly introduce the drawings that are needed in the embodiments or the description of the prior art, it is obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic plan view of a portion of a display panel according to the related art.
Fig. 2 is a schematic plan view of an array substrate according to an embodiment of the present utility model.
Fig. 3 is a schematic diagram of a partial film structure of an array substrate according to an embodiment of the present utility model.
Fig. 4 is a schematic plan view of another planar structure of an array substrate according to an embodiment of the present utility model.
Fig. 5 is a schematic plan view of another embodiment of an array substrate according to the present utility model.
Fig. 6 is a schematic cross-sectional structure of a display panel according to an embodiment of the utility model.
Detailed Description
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the utility model may be practiced. The directional terms mentioned in the present utility model, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., are only referring to the directions of the attached drawings. Accordingly, directional terminology is used to describe and understand the utility model and is not limiting of the utility model. In the drawings, like elements are designated by like reference numerals. In the drawings, the thickness of some layers and regions are exaggerated for clarity of understanding and ease of description. I.e., the size and thickness of each component shown in the drawings are arbitrarily shown, but the present utility model is not limited thereto.
For the problem of low yield of the display panel adopting the HG2D architecture pixel design in the related art, the present inventors found in the study: referring to fig. 1, fig. 1 is a schematic plan view of a portion of a display panel in the related art, the display panel adopts a pixel design of HG2D (half gate, two data) architecture, the display panel includes a plurality of scanning lines GL and a plurality of data lines, one row of sub-pixels corresponds to two data lines, two data lines are disposed between two adjacent rows of sub-pixels, the two data lines are a first data line DL1 and a second data line DL2, a distance between the first data line DL1 and the second data line DL2 is relatively short, and short circuit is easy to occur, thereby resulting in a low yield of the display panel.
In order to solve the problems, the utility model provides an array substrate and a display panel.
Referring to fig. 2 and fig. 3, fig. 2 is a schematic plan view of an array substrate according to an embodiment of the present utility model, and fig. 3 is a schematic partial film structure of the array substrate according to an embodiment of the present utility model. Referring to fig. 2, the array substrate 100 includes a substrate 10 and a plurality of sub-pixels arranged on the substrate 10 in an array, the plurality of sub-pixels being arranged in a sub-pixel row (e.g., sub-pixel rows SPH1, SPH2, SPH3 shown in fig. 2) in a first direction X, and the plurality of sub-pixels being arranged in a sub-pixel column (e.g., sub-pixel columns SPL1, SPL2, SPL3 shown in fig. 2) in a second direction Y.
It should be noted that fig. 2 schematically illustrates three sub-pixel rows and three sub-pixel columns, but the present utility model is not limited thereto, and the array substrate 100 of the present utility model may include more or fewer sub-pixel rows and sub-pixel columns. The first direction X and the second direction Y are different, for example, the first direction X is a row direction, the second direction Y is a column direction, and the first direction X is perpendicular to the second direction Y.
The array substrate 100 further includes a plurality of data lines 20 and a plurality of scan lines 30 disposed on the substrate 10, wherein the plurality of data lines 20 extend along the second direction Y and are arranged at intervals along the first direction X, and the plurality of scan lines 30 extend along the first direction X and are arranged at intervals along the second direction Y. Two data lines 20 are disposed between two adjacent columns of the sub-pixel columns, and the two data lines 20 are a first data line 21 and a second data line 22. The first data line 21 includes a plurality of first sub-lines 211 arranged at intervals in the second direction Y, and a second sub-line 212 connected between two adjacent first sub-lines 211, wherein the first sub-lines 211 and the second sub-lines 212 are disposed at different layers; the second data line 22 includes a plurality of third sub-lines 221 arranged at intervals in the second direction Y, and a fourth sub-line 222 connected between two adjacent third sub-lines 221, wherein the third sub-lines 221 and the fourth sub-lines 222 are disposed in different layers; the first sub-line 211 and the third sub-line 221 are arranged in the same layer, the first sub-line 211 corresponds to the fourth sub-line 222, the second sub-line 212 corresponds to the third sub-line 221, so that sub-line parts located in the same layer in two adjacent data lines 20 are staggered, the risk of short circuit of the two adjacent data lines 20 is reduced, the yield is improved, and the technical problem that the yield of the display panel adopting the HG2D architecture pixel design in the related art is lower is solved.
Specifically, with continued reference to fig. 2, each of the sub-pixel columns is connected to the adjacent first data line 21 and the second data line 22, that is, each of the sub-pixel columns is connected to two data lines 20, and the two data lines 20 may be located at two sides of the sub-pixel column. For example, taking the sub-pixel column SPL1 as an example, the sub-pixel column SPL1 is connected to the first data line 21 and the second data line 22 located at both sides thereof.
Further, among the first data line 21 and the second data line 22 located between two adjacent sub-pixel columns, the first data line 21 is connected to one of the two adjacent sub-pixel columns, and the second data line 22 is connected to the other of the two adjacent sub-pixel columns. For example, taking two adjacent sub-pixel columns SPL1 and SPL2 as an example, among the first data line 21 and the second data line 22 between the sub-pixel column SPL1 and the sub-pixel column SPL2, the first data line 21 is connected to the sub-pixel column SPL1, and the second data line 22 is connected to the sub-pixel column SPL 2.
Further, in the same sub-pixel column, one of two adjacent sub-pixels is connected to the first data line 21, the other is connected to the second data line 22, and the first data line 21 and the second data line 22 are used for providing data signals to the corresponding sub-pixels. In the first direction X, the sub-pixel connected to the first data line 21 is located between the adjacent first sub-line 211 and fourth sub-line 222, and is connected to the first sub-line 211; the sub-pixel connected to the second data line 22 is located between the adjacent second sub-line 212 and third sub-line 221, and is connected to the third sub-line 221.
The orthographic projections of the first sub-line 211 and the third sub-line 221 in the first direction X are separated, or the orthographic projections of the second sub-line 212 and the fourth sub-line 222 in the first direction X are separated. Wherein, the separation means that there is no overlapping portion between the two orthographic projections, for example, the orthographic projections of the first sub-line 211 and the third sub-line 221 in the first direction X are separated from each other, which means that there is no overlapping portion between the orthographic projection of the first sub-line 211 in the first direction X and the orthographic projection of the third sub-image in the first direction X.
One scanning line 30 is arranged between two adjacent sub-pixel rows, and each scanning line 30 is connected with all the sub-pixels in the same sub-pixel row and is used for providing scanning signals for the corresponding sub-pixels; of the two adjacent scan lines 30, one scan line 30 has an overlapping area with the adjacent first sub-line 211 and the fourth sub-line 222, and the other scan line 30 has an overlapping area with the adjacent second sub-line 212 and the third sub-line 221, that is, the first sub-line 211, the second sub-line 212, the third sub-line 221 and the fourth sub-line 222 each cross over one scan line 30 in the second direction Y, so that the lengths of the first sub-line 211, the second sub-line 212, the third sub-line 221 and the fourth sub-line 222 in the second direction Y are substantially the same and are equivalent to the sizes of the sub-pixels in the second direction Y, so as to facilitate connection of the data line 20 with the corresponding sub-pixels.
Referring to fig. 2 and 3 in combination, each of the sub-pixels includes a transistor 40 and a pixel electrode 50 connected to the transistor 40, the pixel electrode 50 being located on a side of the transistor 40 remote from the substrate 10, the first sub-line 211 and the third sub-line 221 being disposed in the same layer as a portion of the metal layer of the transistor 40, and the second sub-line 212 and the fourth sub-line 222 being disposed in the same layer as the pixel electrode 50.
Specifically, referring to fig. 3, the transistor 40 is disposed on one side of the substrate 10, and the substrate 10 may be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, the substrate may include a rigid substrate such as a glass substrate; when the substrate 10 is a flexible substrate, the substrate may include a Polyimide (PI) film, an ultrathin glass film, or the like. The transistor 40 is a thin film transistor, and the transistor 40 includes an active layer 44, a gate electrode 41, a source electrode 42, and a drain electrode 43. The pixel electrode 50 is disposed on a side of the transistor 40 remote from the substrate 10 and is electrically connected to the source 42 or the drain 43 of the transistor 40. Of course, the array substrate 100 further includes a plurality of insulating layers, such as a buffer layer 11 between the substrate 10 and the active layer 44, a gate insulating layer 12 between the active layer 44 and the gate electrode 41, an interlayer insulating layer 13 between the gate electrode 41 and the source and drain electrodes 42 and 43, and a planarization layer 14 between the source and drain electrodes 42 and 43 and the pixel electrode 50.
Alternatively, the gate 41 is disposed in the same layer as the scan line 30, and the gate 41 and the scan line 30 are electrically connected, for example, the gate 41 may be integrally disposed with the corresponding scan line 30. The first sub-line 211 and the third sub-line 221 are each arranged in the same layer as the source electrode 42 and the drain electrode 43, and the second sub-line 212 and the fourth sub-line 222 are each arranged in the same layer as the pixel electrode 50. In the first direction X, the width of the second sub-line 212 is greater than the width of the first sub-line 211, and the width of the fourth sub-line 222 is greater than the width of the third sub-line 221, so as to reduce the resistances of the second sub-line 212 and the fourth sub-line 222.
The buffer layer 11, the gate insulating layer 12, and the interlayer insulating layer 13 are inorganic layers, such as a silicon oxide layer or a silicon nitride layer, and the planarization layer 14 is an organic layer, such as an organic photoresist layer. The active layer 44 is a semiconductor layer, such as a polysilicon layer or an oxide semiconductor layer. The gate 41, the source 42 and the drain 43 are all metal layers, such as copper, aluminum, titanium, molybdenum, etc., forming a metal monolayer or metal stack. The pixel electrode 50 is a transparent conductive layer, such as a transparent conductive layer formed of Indium Tin Oxide (ITO).
In an embodiment, please refer to fig. 2 to fig. 4 in combination, fig. 4 is another schematic plan view of an array substrate 100 according to an embodiment of the present utility model. Unlike the above embodiment, the orthographic projections of the second sub-line 212 and the fourth sub-line 222 in the first direction X are separated, and there is a gap between the orthographic projections of the second sub-line 212 and the fourth sub-line 222 in the first direction X, at this time, the first sub-line 211 and the third sub-line 221 each span two adjacent scan lines 30. In this embodiment, the risk of short circuit between two adjacent data lines 20 can be reduced, and the yield can be improved, and other descriptions refer to the above embodiments, which are not repeated here.
In an embodiment, please refer to fig. 2 to 5 in combination, fig. 5 is a schematic plan view of an array substrate 100 according to another embodiment of the present utility model. Unlike the above embodiment, the orthographic projections of the first sub-line 211 and the third sub-line 221 in the first direction X are separated, and a gap exists between the orthographic projections of the first sub-line 211 and the third sub-line 221 in the first direction X, at this time, the second sub-line 212 and the fourth sub-line 222 each span two adjacent scan lines 30. In this embodiment, the risk of short circuit between two adjacent data lines 20 can be reduced, and the yield can be improved, and other descriptions refer to the above embodiments, which are not repeated here.
In an embodiment, referring to fig. 1 to fig. 6, fig. 6 is a schematic cross-sectional structure of the display panel according to the embodiment of the present utility model. The display panel 1000 includes the array substrate 100 according to one of the foregoing embodiments. The display panel 1000 further includes an opposite substrate 200 disposed opposite to the array substrate 100. The display panel 1000 may be a liquid crystal display panel, and in this case, the opposable substrate 200 is a color film substrate.
As can be seen from the above embodiments:
In the array substrate and the display panel provided by the utility model, the array substrate comprises a plurality of data lines arranged on the substrate, the plurality of data lines extend along a second direction and are distributed at intervals along the first direction, two data lines are arranged between two adjacent rows of sub-pixel columns, and the two data lines are a first data line and a second data line; the first data line comprises a plurality of first sub-lines which are arranged at intervals in the second direction and a second sub-line which is connected between two adjacent first sub-lines, and the first sub-lines and the second sub-lines are arranged on different layers; the second data line comprises a plurality of third sub-lines which are arranged at intervals in the second direction and a fourth sub-line which is connected between two adjacent third sub-lines, and the third sub-line and the fourth sub-line are arranged on different layers; the first sub-line and the third sub-line are arranged on the same layer, the first sub-line corresponds to the fourth sub-line, the second sub-line corresponds to the third sub-line, so that sub-line parts positioned on the same layer in two adjacent data lines are staggered, the risk of short circuit of the two adjacent data lines is reduced, the yield is improved, and the technical problem that the yield is lower in the existing display panel adopting HG2D architecture pixel design is solved.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The foregoing has described in detail embodiments of the present utility model, and specific examples have been employed herein to illustrate the principles and embodiments of the present utility model, the above description of the embodiments being only for the purpose of aiding in the understanding of the technical solution and core idea of the present utility model; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.
Claims (10)
1. An array substrate is characterized by comprising a substrate and a plurality of sub-pixels arranged on the substrate in an array manner, wherein the sub-pixels are arranged in a sub-pixel row in a first direction, and the sub-pixels are arranged in a sub-pixel column in a second direction;
The array substrate further comprises a plurality of data lines arranged on the substrate, the data lines extend along the second direction and are distributed at intervals along the first direction, two data lines are arranged between two adjacent rows of sub-pixel rows, and the two data lines are a first data line and a second data line;
The first data line comprises a plurality of first sub-lines which are arranged at intervals in the second direction and a second sub-line which is connected between two adjacent first sub-lines, and the first sub-lines and the second sub-lines are arranged on different layers; the second data line comprises a plurality of third sub-lines which are arranged at intervals in the second direction and a fourth sub-line which is connected between two adjacent third sub-lines, and the third sub-line and the fourth sub-line are arranged on different layers; the first sub-line and the third sub-line are arranged in the same layer, the first sub-line is arranged corresponding to the fourth sub-line, and the second sub-line is arranged corresponding to the third sub-line.
2. The array substrate of claim 1, wherein the subpixels in each subpixel column are connected to the adjacent first and second data lines.
3. The array substrate of claim 2, wherein among two adjacent sub-pixel columns and the first data line and the second data line between the two adjacent sub-pixel columns, the first data line is connected to one of the two adjacent sub-pixel columns, and the second data line is connected to the other of the two adjacent sub-pixel columns.
4. The array substrate of claim 3, wherein one of two adjacent sub-pixels is connected to the first data line and the other is connected to the second data line in the same sub-pixel column.
5. The array substrate of claim 4, wherein the sub-pixel connected to the first data line is located between the adjacent first sub-line and fourth sub-line in the first direction and connected to the first sub-line; the sub-pixel connected to the second data line is located between the adjacent second sub-line and the third sub-line and is connected to the third sub-line.
6. The array substrate of any one of claims 1 to 5, wherein orthographic projections of the first sub-line and the third sub-line in the first direction are separated; or (b)
The orthographic projections of the second sub-line and the fourth sub-line in the first direction are separated.
7. The array substrate according to any one of claims 1 to 5, wherein each of the sub-pixels includes a transistor and a pixel electrode connected to the transistor, the pixel electrode being located on a side of the transistor remote from the substrate, the first and third sub-lines being disposed in-layer with a portion of a metal layer of the transistor, and the second and fourth sub-lines being disposed in-layer with the pixel electrode.
8. The array substrate of claim 7, wherein in the first direction, a width of the second sub-line is greater than a width of the first sub-line, and a width of the fourth sub-line is greater than a width of the third sub-line.
9. The array substrate according to claim 7, further comprising a plurality of scan lines disposed on the substrate, each of the plurality of scan lines extending in the first direction, one of the scan lines disposed between two adjacent sub-pixel rows, each of the scan lines being connected to all of the sub-pixels in the same sub-pixel row; and in two adjacent scanning lines, one scanning line has an overlapping area with the adjacent first sub-line and the adjacent fourth sub-line, and the other scanning line has an overlapping area with the adjacent second sub-line and the adjacent third sub-line.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323367535.6U CN221303773U (en) | 2023-12-08 | 2023-12-08 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323367535.6U CN221303773U (en) | 2023-12-08 | 2023-12-08 | Array substrate and display panel |
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| Publication Number | Publication Date |
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| CN221303773U true CN221303773U (en) | 2024-07-09 |
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| CN202323367535.6U Active CN221303773U (en) | 2023-12-08 | 2023-12-08 | Array substrate and display panel |
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| CN (1) | CN221303773U (en) |
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