CN221151348U - High-voltage level shift circuit and DC-DC chip - Google Patents
High-voltage level shift circuit and DC-DC chip Download PDFInfo
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- CN221151348U CN221151348U CN202323080451.4U CN202323080451U CN221151348U CN 221151348 U CN221151348 U CN 221151348U CN 202323080451 U CN202323080451 U CN 202323080451U CN 221151348 U CN221151348 U CN 221151348U
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Abstract
The utility model discloses a high-voltage level shift circuit and a DC-DC chip, wherein the high-voltage level shift circuit comprises a low-power-domain low-voltage input end, a low-power-domain high-voltage input end, a high-power-domain low-voltage input end, a high-power-domain high-voltage input end, a low-power-domain logic control circuit and a high-power-domain level shift circuit. The high power domain low voltage input end is connected with the floatable voltage, the high power domain high voltage input end is connected with bootstrap boosting of the floatable voltage, and the high power domain level shift circuit is connected with the high power domain low voltage input end and the high power domain high voltage input end. The low power domain logic control circuit controls the high power domain level shift circuit to output the voltage of the high power domain high voltage input end or the voltage of the high power domain low voltage input end based on the input first level, so that the voltage of the high power domain high voltage input end can be larger than the gate breakdown voltage of the MOS tube, and the high voltage level shift circuit can output higher voltage to be used for driving the high power tube in the DC-DC chip.
Description
Technical Field
The utility model relates to the technical field of integrated circuits, in particular to a high-voltage level shift circuit and a DC-DC chip.
Background
The level shift circuit plays an important role in an electronic circuit, and can be applied to electronic devices such as computers, televisions, audio equipment, mobile phones, tablet computers and the like. The level shift circuit is based on a logic control circuit, and can realize the conversion of logic '0' and '1' levels of a low power domain into logic '0' and '1' levels of a high power domain.
In the electronic process, since the low-side voltage of the high power domain of the level shift circuit is connected to the low-side voltage of the low power domain and is generally commonly grounded, the high-side voltage of the high power domain of the level shift circuit cannot be greater than the gate breakdown voltage of the MOS transistor in order to prevent the gate oxide layer from being damaged due to the excessively high voltage of the circuit. However, in practical applications, such as in the design of a DC-DC chip, the level shift circuit needs to be used for logically driving the high power transistor, and then the level shift circuit needs to output a higher level, so the high-side voltage of the high power domain may reach a higher voltage value or even exceed 20V, and the voltage applied between the gate sources of the MOS transistor in the prior art cannot exceed 18V in most cases. Thus, there is a need to design a high voltage level shift circuit to meet the requirements of driving high power transistors in a DC-DC chip.
Disclosure of utility model
The utility model mainly aims to provide a high-voltage level displacement circuit which aims to meet the requirement of driving a high-power tube in a DC-DC chip.
In order to achieve the above object, the present utility model provides a high-voltage level shift circuit, comprising:
A low power domain low voltage input;
a low power domain high voltage input;
The high power domain low voltage input end is used for being connected with floatable low voltage;
The high-voltage input end of the high power domain is used for being connected with a floatable low-voltage bootstrapped and boosted high voltage connected with the low-voltage input end of the high power domain;
the low power domain logic control circuit is respectively connected with the low power domain low voltage input end and the low power domain high voltage input end; the low power domain logic control circuit is provided with a logic level input end and is used for inputting a first level;
The high power domain level shift circuit is respectively connected with the high power domain low voltage input end, the high power domain high voltage input end and the low power domain logic control circuit; the high power domain level shift circuit is provided with a logic level output end and is used for outputting a second level;
The low power domain logic control circuit is further configured to control the high power domain level shift circuit to output a second level according to the first level.
Optionally, the high power domain level shift circuit further includes a clamp circuit; the input end of the clamping circuit is respectively connected with the low-voltage input end of the high power domain and the common connection point of the high-voltage level shift circuit and the logic control circuit of the low power domain; the clamping circuit is used for limiting the voltage of the low-voltage input end of the high power domain and inputting the limited voltage to the high power domain level shift circuit.
Optionally, the low power domain logic control circuit includes a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;
The source electrode of the third PMOS tube is connected with the high-voltage input end of the low power domain; the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are connected with a low-power-domain low-voltage input end; the grid electrode of the fourth NMOS tube is connected with the logic level input end; the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube are connected with the grid electrode of the fifth NMOS tube;
The output end of the low power domain logic control circuit is provided with a first connecting wire and a second connecting wire; the first connecting wire of the output end of the low power domain logic control circuit is connected with the drain electrode of the fourth NMOS tube; and a second connecting wire at the output end of the low power domain logic control circuit is connected with the drain electrode of the fifth NMOS tube.
Optionally, the high power domain level shift circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and a seventh NMOS transistor;
The source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube, the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube are connected with the high-power-domain high-voltage input end; the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are connected with the low-voltage input end of the high power domain;
The input end of the high-voltage level displacement circuit is provided with a first connecting wire and a second connecting wire; the first connecting wire of the input end of the high-voltage level shift circuit, the drain electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the seventh NMOS tube are connected; the second connecting wire of the input end of the high-voltage level shift circuit, the grid electrode of the fourth PMOS tube and the drain electrode of the fifth PMOS tube are connected with the grid electrode of the sixth NMOS tube;
The drain electrode of the sixth PMOS tube and the drain electrode of the sixth NMOS tube are connected with the grid electrode of the seventh PMOS tube; and the grid electrode of the sixth PMOS tube, the drain electrode of the seventh PMOS tube and the drain electrode of the seventh NMOS tube are connected with the logic level output end.
Optionally, the input end of the high-voltage level shift circuit is provided with a first connecting wire and a second connecting wire; the clamping circuit comprises a first diode and a second diode; the positive electrode of the first diode and the positive electrode of the second diode are connected with the low-voltage input end of the high power domain; the negative electrode of the first diode is connected with a first connecting wire of the input end of the high-voltage level shift circuit; and the cathode of the second diode is connected with a second connecting wire of the input end of the high-voltage level shift circuit.
Optionally, the low power domain logic control circuit further comprises a low power domain drive enhancement circuit; the low power domain drive enhancement circuit is respectively connected with the low power domain low voltage input end and the low power domain high voltage input end; the low power domain drive enhancement circuit has an input and an output; the input end of the low power domain drive enhancement circuit is connected with the logic level input end; the low power domain drive enhancing circuit is used for driving and enhancing the first level and outputting the first level through the output end of the low power domain drive enhancing circuit.
Optionally, the high power domain level shift circuit further comprises a high power domain drive enhancement circuit; the high power domain drive enhancement circuit is respectively connected with the high power domain low voltage input end and the high power domain high voltage input end; the high power domain drive enhancement circuit has an input and an output; the input end of the high power domain drive enhancement circuit is connected with the logic level output end; the high power domain drive enhancing circuit is used for driving and enhancing the second level and outputting the second level through the output end of the high power domain drive enhancing circuit.
Optionally, the low power domain driving enhancement circuit includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the high-voltage input end of the low power domain; the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with the low-voltage input end of the low power domain; the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with the logic level input end; the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the second PMOS tube are connected with the grid electrode of the second NMOS tube; and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube and the output end of the low power domain drive enhancement circuit.
Optionally, the high power domain driving enhancement circuit includes an eighth PMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, and a ninth NMOS transistor; the source electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube are connected with the high-voltage input end of the high power domain; the source electrode of the eighth NMOS tube and the source electrode of the ninth NMOS tube are connected with the low-voltage input end of the high power domain; the grid electrode of the eighth PMOS tube and the grid electrode of the eighth NMOS tube are connected with the logic level output end; the drain electrode of the eighth PMOS tube, the drain electrode of the eighth NMOS tube and the grid electrode of the ninth PMOS tube are connected with the grid electrode of the ninth NMOS tube; and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube and the output end of the high power domain drive enhancement circuit.
The utility model also provides a DC-DC chip, which comprises the high-voltage level shift circuit.
The technical scheme of the utility model adopts a high-voltage level shift circuit, which comprises a low-power-domain low-voltage input end, a low-power-domain high-voltage input end, a high-power-domain low-voltage input end, a high-power-domain high-voltage input end, a low-power-domain logic control circuit and a high-power-domain level shift circuit. In this embodiment, when the input first level is a high level, the low power domain logic control circuit controls the second level output by the high power domain level shift circuit to be also a high level. The high power domain level shift circuit is respectively connected with the high power domain low voltage input end and the high power domain high voltage input end, wherein the high power domain low voltage input end inputs floatable low voltage, and the high power domain high voltage input end inputs high voltage which is input by the high power domain low voltage input end and is obtained by bootstrap boosting, so that the output second level is the voltage input by the high power domain high voltage input end. When the input first level is low level, the low power domain logic control circuit controls the second level output by the high power domain level shift circuit to be low level, namely the voltage input by the low voltage input end of the high power domain. The utility model can output the voltage input by the high voltage input end of the high power domain, can also output the voltage input by the low voltage input end of the high power domain, the output voltage is higher voltage, and can be used for driving the high power tube in the DC-DC chip.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a high voltage level shift circuit according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of a high voltage level shift circuit according to another embodiment of the present utility model;
fig. 3 is a schematic diagram of a DC-DC chip according to an embodiment of the utility model.
Reference numerals illustrate:
the achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
In the electronic process, since the low-side voltage of the high power domain of the level shift circuit is connected to the low-side voltage of the low power domain and is generally commonly grounded, the high-side voltage of the high power domain of the level shift circuit cannot be greater than the gate breakdown voltage of the MOS transistor in order to prevent the gate oxide layer from being damaged due to the excessively high voltage of the circuit. However, in practical applications such as the design of a DC-DC chip, the level shift circuit is required to logically drive a high power transistor, and the high voltage of the high power domain may reach a relatively high voltage value or even exceed 20V, while the voltage applied between the gate sources of the MOS transistor in the prior art cannot exceed 18V in most cases. Thus, there is a need to design a high voltage level shift circuit to meet the requirements of driving high power transistors in a DC-DC chip.
In order to solve the above problems, the present utility model provides a high-voltage level shift circuit.
In one embodiment of the present utility model, as shown in fig. 1, a high voltage level shift circuit is applied to a DC-DC chip, and includes:
A low power domain low voltage input;
a low power domain high voltage input;
The high power domain low voltage input end is used for being connected with floatable low voltage;
The high-voltage input end of the high power domain is used for being connected with a floatable low-voltage bootstrapped and boosted high voltage connected with the low-voltage input end of the high power domain;
The low power domain logic control circuit 10, the low power domain logic control circuit 10 is connected with a low voltage input end of the low power domain and a high voltage input end of the low power domain respectively; the low power domain logic control circuit 10 has a logic level input terminal for inputting a first level;
The high power domain level shift circuit 20, the high power domain level shift circuit 20 is connected with the high power domain low voltage input end, the high power domain high voltage input end and the low power domain logic control circuit 10 respectively; the high power domain level shifter circuit 20 has a logic level output for outputting a second level;
The low power domain logic control circuit 10 is further configured to control the high power domain level shift circuit 20 to output the second level according to the first level.
In this embodiment, the low voltage represents the logic signal "0", and the high voltage represents the logic signal "1". The "0" of the low power domain represents the low voltage of the low voltage input terminal of the low power domain, and the "1" of the low power domain represents the high voltage input by the high voltage input terminal of the low power domain. The "0" of the high power domain represents the low voltage of the low voltage input terminal of the high power domain, and the "1" of the high power domain represents the high voltage input by the high voltage input terminal of the high power domain. The circuits connected with VSS-VDD are low power supply domains, and the circuits connected with SW-BTST are high power supply domains.
In this embodiment, when the first level logic input at Vin is "1", the low power domain logic control circuit 10 controls the second level logic output by the high power domain level shift circuit 20 to be "1" as well. Since the high power domain level shift circuit 20 is connected to the high power domain low voltage input terminal and the high power domain high voltage input terminal respectively, and the high power domain low voltage input terminal inputs SW, the high power domain high voltage input terminal inputs BTST, the output second level is BTST. When the first level logic input at Vin is "0", the low power domain logic control circuit 10 controls the second level logic output by the high power domain level shift circuit 20 to be "0", that is, the second level output is SW. For example, VSS may be 0, VDD may be 5V, SW may be 15V, BTST may be 18.3V. When the first level input at Vin is 5V, representing input "1", the low power domain logic control circuit 10 controls the second level output by the high power domain level shift circuit 20 to be "1", i.e. the output second level is 18.3V. Similarly, when the first level input at Vin is 0, which represents an input of "0", the low power domain logic control circuit 10 controls the second level output by the high power domain level shift circuit 20 to be "0", i.e. the output second level is 15V. When the level shift circuit is required to logically drive a high power transistor, a higher voltage needs to be input, and the voltage of the second level to be output is required to be higher. If the low voltage input end of the high power domain is grounded, the MOS tube of the level shift circuit is broken down due to the fact that the high voltage input end of the high power domain is connected with a higher voltage. In this embodiment, by connecting the floatable low voltage SW to the low voltage input end of the high power domain, SW can float between the input voltages hv_vin to 0 of the high power transistor, instead of being grounded, even if the high voltage input end of the high power domain is connected to a higher voltage, the voltage between the gate sources of the MOS transistor will not exceed the maximum voltage value that can be borne between the gate sources of the MOS transistor, and damage to the MOS transistor will not be caused.
According to the utility model, the floatable low-voltage SW is connected to the low-voltage input end of the high power domain instead of being grounded, even if the high-voltage input end of the high power domain is connected to higher voltage, the voltage between the grid sources of the MOS tube does not exceed the maximum voltage value bearable between the grid sources of the MOS tube, so that the MOS tube is not damaged, and the output second level voltage is higher and can be used for driving the high-power device in the DC-DC chip.
Further, in an embodiment of the present utility model, as shown in fig. 2, the high power domain level shift circuit further includes a clamp circuit 22; the input end of the clamping circuit 22 is respectively connected with the low-voltage input end of the high-power domain and the common connection point of the high-voltage level shift circuit 20 and the logic control circuit 10 of the low-power domain; the clamp circuit 22 is used for limiting the voltage of the low voltage input terminal of the high power domain and inputting the limited voltage to the high power domain level shift circuit 20.
In this embodiment, the clamp circuit 22 can limit the voltage input to the high power domain level shifter circuit 20. In this embodiment, the voltage difference between BTST and SW may be 3.3V. The gate-source voltage of the MOS transistor of the high power domain level shift circuit 20 can bear 3.3V, but in the situation that only some MOS transistors with poor gate-source voltage resistance or some thin gate MOS transistors are needed to be used under the influence of the process, even the situation that the MOS transistor is damaged when 3.3V is added between the gate sources, the clamping circuit 22 is added to the original high voltage level shift circuit to further limit the voltage input to the high power domain level shift circuit 20, if the voltage provided by the clamping circuit 22 is 0.7V, the gate-source voltage can be clamped within 2.6V and not more than 2.7V. Therefore, the MOS transistor in the high power domain level shift circuit 20 can be free from the limitation of the process, and even the MOS transistor with poor gate-source voltage resistance will not be damaged.
Further, in an embodiment of the present utility model, as shown in fig. 2, the low power domain logic control circuit 10 includes a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;
The source electrode of the third PMOS tube is connected with the high-voltage input end of the low power domain; the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are connected with a low-voltage input end of a low power supply domain; the grid electrode of the fourth NMOS tube is connected with the logic level input end; the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube are connected with the grid electrode of the fifth NMOS tube;
The output end of the low power domain logic control circuit 10 is provided with a first connecting wire and a second connecting wire; the first connecting wire of the output end of the low power domain logic control circuit 10 is connected with the drain electrode of the fourth NMOS tube; the second connection line of the output end of the low power domain logic control circuit 10 is connected with the drain electrode of the fifth NMOS tube.
In this embodiment, when the first level logic input at Vin is "1", the level input at EN1 is VDD, NM4 is turned on, and the voltage at Vo1 is pulled down to the voltage at the low voltage input terminal of the high power domain. When the first level inputs "0", the level inputted at the EN1 point is VSS, PM3 is turned on, the level inputted at the EN2 point is VDD, NM5 is turned on, and the potential at the Vo2 point is pulled down to the voltage inputted at the low voltage input terminal of the high power domain. Thus, the embodiment can realize that when the logic level of the first level changes, the potentials of the Vo1 point and the Vo2 point also change synchronously.
It should be noted that, when the voltages input from the low voltage input terminals of the high power domain are relatively large, if the common NMOS transistors are used for the NM4 and the NM5, the drain-source voltage between the NM4 and the NM5 may exceed the maximum withstand voltage values of the drain-source voltages of the NM4 and the NM5, resulting in damage to the NM4 and the NM5. Therefore, the high-voltage NMOS transistor is adopted in the embodiment to avoid damage to NM4 and NM5, namely HVNM4 and HVNM5 in the figure.
Further, in an embodiment of the present utility model, as shown in fig. 2, the high power domain level shift circuit 20 includes a fourth PMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and a seventh NMOS transistor;
the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube, the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube are connected with the high-voltage input end of the high power domain; the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are connected with the low-voltage input end of the high power domain;
The input end of the high-voltage level shift circuit is provided with a first connecting wire and a second connecting wire; the first connecting wire of the input end of the high-voltage level shift circuit, the drain electrode of the fourth PMOS tube and the grid electrode of the fifth PMOS tube are connected with the grid electrode of the seventh NMOS tube; the second connecting wire of the input end of the high-voltage level shift circuit, the grid electrode of the fourth PMOS tube and the drain electrode of the fifth PMOS tube are connected with the grid electrode of the sixth NMOS tube;
The drain electrode of the sixth PMOS tube and the drain electrode of the sixth NMOS tube are connected with the grid electrode of the seventh PMOS tube; the grid electrode of the sixth PMOS tube, the drain electrode of the seventh PMOS tube and the drain electrode of the seventh NMOS tube are connected with the logic level output end.
In this embodiment, when the potential at the Vo1 point is pulled down to the voltage input by the low voltage input terminal of the high power domain, the PM5 is turned on, and the potential at the Vo2 point is pulled up to the voltage input by the high voltage input terminal of the high power domain. NM6 is turned on, and the potential of Vo4 is pulled down to the voltage input at the low voltage input terminal of the high power domain. PM7 is turned on, and the potential at the Vo3 point is pulled up to the voltage input at the high-voltage input terminal of the high power domain. I.e., the second level of the Vout point output also outputs a "1", i.e., the output is BTST. When the potential at the Vo2 point is pulled down to the voltage input by the low voltage input end of the high power domain, the PM4 is turned on, and the potential at the Vo1 point is pulled up to the voltage input by the high voltage input end of the high power domain. The NM7 is turned on, and the potential at the Vo3 point is pulled down to the voltage input by the low voltage input end of the high power domain. I.e., the second level of the Vout point output is "0", i.e., the output is SW. It should be noted that, in this embodiment, the gate-source voltage of PM5 is always smaller than the breakdown voltage of the MOS transistor, which is generally 5V, and the voltage between SW and BTST may be 3.3V, so as to realize protection of PM 5.
Further, in an embodiment of the present utility model, as shown in fig. 2, an input end of the high voltage level shift circuit has a first connection line and a second connection line; the clamping circuit 22 includes a first diode and a second diode; the positive electrode of the first diode and the positive electrode of the second diode are connected with the low-voltage input end of the high power domain; the cathode of the first diode is connected with a first connecting wire of the input end of the high-voltage level shift circuit; the negative pole of the second diode is connected with a second connecting wire of the input end of the high-voltage level shift circuit.
In this embodiment, the on voltage of D1 and D2 is 0.7V, and D1 and D2 are set to further reduce the risk of damaging the MOS transistor with poor gate-source voltage resistance.
Further, in an embodiment of the present utility model, as shown in fig. 2, the low power domain logic control circuit 10 further includes a low power domain drive enhancing circuit 11; the low power domain drive enhancing circuit 11 is respectively connected with a low voltage input end of the low power domain and a high voltage input end of the low power domain; the low power domain drive enhancement circuit 11 has an input terminal and an output terminal; the input end of the low power domain drive enhancement circuit 11 is connected with the logic level input end; the low power domain driving enhancing circuit 11 is configured to enhance the first level and output the first level through an output terminal of the low power domain driving enhancing circuit 11.
In this embodiment, the low power domain driving enhancing circuit 11 may be composed of a plurality of MOS transistors, and if the logic level input end is connected to the high power transistor, the parasitic capacitance between the gate source and the gate drain of the high power transistor is larger, so that the low power domain driving enhancing circuit 11 may be used for enhancing driving, so that the high power transistor is turned on or off rapidly, and the switching loss of the high power transistor is reduced.
Further, in an embodiment of the present utility model, as shown in fig. 2, the low power domain driving enhancement circuit 11 includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the high-voltage input end of the low power domain; the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with the low-voltage input end of the low power domain; the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with the logic level input end; the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the second PMOS tube are connected with the grid electrode of the second NMOS tube; the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube and the output end of the low power domain drive enhancement circuit 11.
In this embodiment, when the first level input at Vin is "1", the low power domain logic control circuit 10 inputs a high level, NM1 is turned on and PM2 is turned on, and EN1 inputs VDD. When the first logic level input terminal Vin inputs the first level input "0", the low power domain logic control circuit 10 inputs the low level, PM1 is turned on and NM2 is turned on, and EN1 is inputted with VSS.
Further, in an embodiment of the present utility model, as shown in fig. 2, the high power domain level shifter 20 further includes a high power domain drive enhancing circuit 21; the high power domain drive enhancing circuit 21 is connected with the high power domain low voltage input terminal and the high power domain high voltage input terminal respectively; the high power domain drive enhancement circuit 21 has an input terminal and an output terminal; the input end of the high power domain drive enhancement circuit 21 is connected with the logic level output end; the high power domain driving enhancing circuit 21 is configured to enhance the second level and output the second level through an output terminal of the high power domain driving enhancing circuit 21.
In this embodiment, the high power domain driving enhancing circuit 21 may be composed of a plurality of MOS transistors, and if the logic level output end is connected to the high power transistor, the parasitic capacitance between the gate source and the gate drain of the high power transistor is larger, so that the high power transistor can be rapidly turned on or off by enhancing the driving process by the high power domain driving enhancing circuit 21, and the switching loss of the high power transistor is reduced.
Further, in an embodiment of the present utility model, as shown in fig. 2, the high power domain driving enhancement circuit 21 includes an eighth PMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, and a ninth NMOS transistor; the source electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube are connected with the high-voltage input end of the high power domain; the source electrode of the eighth NMOS tube and the source electrode of the ninth NMOS tube are connected with the low-voltage input end of the high power domain; the grid electrode of the eighth PMOS tube and the grid electrode of the eighth NMOS tube are connected with the logic level output end; the drain electrode of the eighth PMOS tube, the drain electrode of the eighth NMOS tube and the grid electrode of the ninth PMOS tube are connected with the grid electrode of the ninth NMOS tube; the drain electrode of the ninth PMOS tube and the drain electrode of the ninth NMOS tube are connected with the output end of the high power domain drive enhancement circuit 21.
In this embodiment, when the second level of Vo3 point output is "1", NM8 is turned on and PM9 is turned on, and the high power domain level shift circuit 20 outputs BTST. When the second level of Vo3 point output is "0", PM8 is turned on and ninth NMOS transistor NM9 is turned on, and high power domain level shift circuit 20 outputs SW.
The utility model also provides a DC-DC chip, as shown in figure 3, which comprises a high-voltage level shift circuit. The specific structure of the high-voltage level shift circuit refers to the above embodiments, and since the DC-DC chip adopts all the technical solutions of all the embodiments, at least the DC-DC chip has all the beneficial effects brought by the technical solutions of the embodiments, which are not described in detail herein.
It should be noted that the DC-DC chip includes not only the high voltage level shift circuit, but also the high voltage upper tube logic driving, the high voltage lower tube logic driving, the high voltage tube M1, the high voltage tube M2, the input voltage hv_vin of the high voltage tube M1, the bootstrap capacitor C, the bootstrap capacitor charging voltage Vinc, the lower tube logic driving input voltage Vinl and the third diode D3. The bootstrap capacitor C is used for outputting a low voltage SW and a high voltage BTST. The SW is connected to the source electrode of M1, the low-voltage side of the high-voltage upper tube logic drive, the high-power low-voltage input end of the high-voltage level shift circuit and the source electrode of M2 respectively. BTST are respectively connected to the high-power high-voltage input end of the high-voltage side and high-voltage level shift circuit driven by the high-voltage upper tube logic. Bootstrap capacitor charging voltage VinC charges bootstrap capacitor C through a diode. The source electrode of M2 is grounded, and the grid electrode of M2 is connected with a high-voltage down-tube logic driving input Vinl. The output end of the high-voltage level shift circuit is in logic driving connection with the grid electrode of the M1 through a high-voltage upper pipe. Based on the above, when the logic level of Vin input is "1", the high voltage level shift circuit may output the level of logic "1", i.e., the high voltage level BTST is used to control the high-voltage upper pipe logic driving to drive the high-voltage pipe M1. The bootstrap capacitor C can increase SW and BTST voltages for a high power domain of the high-voltage level shift circuit.
The working principle of the present utility model is specifically described below with reference to fig. 1, 2 and 3, as follows:
When the voltage input at Vin point is 5V (VSS is 0 and vdd=5v), that is, when the first level logic is "1", NM1 is turned on and PM2 is turned on, and the level input at EN1 is VDD. NM4 is conducted, and the potential of the Vo1 point is pulled down to SW-VDth (VDth is the conducting voltage of D1 and D2). PM5 is turned on, and the potential at the Vo2 point is pulled up to BTST. NM6 is turned on, and the potential of Vo4 is pulled down to SW. PM7 is turned on, and the potential at the Vo3 point is pulled up to the voltage at BTST input. Vo3 point output BTST, NM8 is on and PM9 is on, and Vout point output BTST of high power domain level shifter circuit 20. I.e., the second level logic of the Vout point output is also "1", a boost from 5V to BTST is achieved. In this process, SW floats between 0 and hv_vin (input voltage of the high-power transistor M1), and D1 plays a clamping role. And the gate-source voltage of PM5 is BTST- (SW-VDth), and the gate-source voltage of PM5 is always smaller than the breakdown voltage of the MOS transistor, so that PM5 is prevented from being damaged.
When the voltage input at Vin point is 0 (VSS is 0 and vdd=5v), that is, when the logic of the first level input at Vin point is "0", PM1 is turned on and NM2 is turned on, and the level input at EN1 is VDD. PM3 turns on, EN2 is input VDD, NM5 turns on, and the potential at Vo2 is pulled down to SW-VDth (VDth is the on voltage of D1, D2). PM4 is turned on, and the potential at the Vo1 point is pulled up to BTST. The NM7 is turned on, and the potential at the Vo3 point is pulled down to SW. Vo3 point output SW, PM8 is on and NM9 is on, and Vout point output SW of high power domain level shift circuit 20, i.e., the second level logic of Vout point output is also "0". In the process, SW floats from HV_vin to 0, and the diode D2 plays a role in clamping, so that the PM4 gate-source voltage is BTST- (SW-VDth), and the PM4 gate-source voltage is always smaller than the breakdown voltage of the MOS transistor, so that the PM4 is prevented from being damaged.
In the utility model, the low-voltage input end of the high power domain is not grounded, but is connected with floatable voltage 0-HV_vin, so that the voltage applied between the grid sources of NM4 and NM5 does not exceed the bearable voltage value all the time, the utility model realizes the displacement of high voltage level, can output high voltage BTST for driving a high-power tube, and is applicable to DV-DC chips.
The foregoing description is only of the optional embodiments of the present utility model, and is not intended to limit the scope of the utility model, and all the equivalent structural changes made by the description of the present utility model and the accompanying drawings or the direct/indirect application in other related technical fields are included in the scope of the utility model.
Claims (10)
1. A high voltage level shift circuit for use with a DC-DC chip, comprising:
A low power domain low voltage input;
a low power domain high voltage input;
The high power domain low voltage input end is used for being connected with floatable low voltage;
The high-voltage input end of the high power domain is used for being connected with a floatable low-voltage bootstrapped and boosted high voltage connected with the low-voltage input end of the high power domain;
the low power domain logic control circuit is respectively connected with the low power domain low voltage input end and the low power domain high voltage input end; the low power domain logic control circuit is provided with a logic level input end and is used for inputting a first level;
The high power domain level shift circuit is respectively connected with the high power domain low voltage input end, the high power domain high voltage input end and the low power domain logic control circuit; the high power domain level shift circuit is provided with a logic level output end and is used for outputting a second level;
The low power domain logic control circuit is further configured to control the high power domain level shift circuit to output the second level according to the first level.
2. The high voltage level shifting circuit of claim 1, further comprising a clamp circuit; the input end of the clamping circuit is respectively connected with the low-voltage input end of the high power domain and the common connection point of the high-voltage level shift circuit and the logic control circuit of the low power domain; the clamping circuit is used for limiting the voltage of the low-voltage input end of the high power domain and inputting the limited voltage to the high power domain level shift circuit.
3. The high voltage level shift circuit of claim 1, wherein the low power domain logic control circuit comprises a third PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;
The source electrode of the third PMOS tube is connected with the high-voltage input end of the low power domain; the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are connected with the low-voltage input end of the low power supply domain; the grid electrode of the fourth NMOS tube is connected with the logic level input end; the drain electrode of the third PMOS tube and the drain electrode of the third NMOS tube are connected with the grid electrode of the fifth NMOS tube;
The output end of the low power domain logic control circuit is provided with a first connecting wire and a second connecting wire; the first connecting wire of the output end of the low power domain logic control circuit is connected with the drain electrode of the fourth NMOS tube; and a second connecting wire at the output end of the low power domain logic control circuit is connected with the drain electrode of the fifth NMOS tube.
4. The high voltage level shift circuit of claim 1, wherein the high power domain level shift circuit comprises a fourth PMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor, a seventh PMOS transistor, and a seventh NMOS transistor;
The source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube, the source electrode of the sixth PMOS tube and the source electrode of the seventh PMOS tube are connected with the high-power-domain high-voltage input end; the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are connected with the low-voltage input end of the high power domain;
The input end of the high-voltage level displacement circuit is provided with a first connecting wire and a second connecting wire; the first connecting wire of the input end of the high-voltage level shift circuit, the drain electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the seventh NMOS tube are connected; the second connecting wire of the input end of the high-voltage level shift circuit, the grid electrode of the fourth PMOS tube and the drain electrode of the fifth PMOS tube are connected with the grid electrode of the sixth NMOS tube;
The drain electrode of the sixth PMOS tube and the drain electrode of the sixth NMOS tube are connected with the grid electrode of the seventh PMOS tube; and the grid electrode of the sixth PMOS tube, the drain electrode of the seventh PMOS tube and the drain electrode of the seventh NMOS tube are connected with the logic level output end.
5. The high voltage level shift circuit of claim 2, wherein an input of the high voltage level shift circuit has a first connection line and a second connection line; the clamping circuit comprises a first diode and a second diode; the positive electrode of the first diode and the positive electrode of the second diode are connected with the low-voltage input end of the high power domain; the negative electrode of the first diode is connected with a first connecting wire of the input end of the high-voltage level shift circuit; and the cathode of the second diode is connected with a second connecting wire of the input end of the high-voltage level shift circuit.
6. The high voltage level shift circuit of claim 1, wherein the low power domain logic control circuit further comprises a low power domain drive enhancement circuit; the low power domain drive enhancement circuit is respectively connected with the low power domain low voltage input end and the low power domain high voltage input end; the low power domain drive enhancement circuit has an input and an output; the input end of the low power domain drive enhancement circuit is connected with the logic level input end; the low power domain drive enhancing circuit is used for driving and enhancing the first level and outputting the first level through the output end of the low power domain drive enhancing circuit.
7. The high voltage level shifting circuit of claim 1, wherein the high power domain level shifting circuit further comprises a high power domain drive enhancement circuit; the high power domain drive enhancement circuit is respectively connected with the high power domain low voltage input end and the high power domain high voltage input end; the high power domain drive enhancement circuit has an input and an output; the input end of the high power domain drive enhancement circuit is connected with the logic level output end; the high power domain drive enhancing circuit is used for driving and enhancing the second level and outputting the second level through the output end of the high power domain drive enhancing circuit.
8. The high voltage level shift circuit of claim 6, wherein the low power domain drive enhancement circuit comprises a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor; the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are connected with the high-voltage input end of the low power domain; the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are connected with the low-voltage input end of the low power domain; the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube are connected with the logic level input end; the drain electrode of the first PMOS tube, the drain electrode of the first NMOS tube and the grid electrode of the second PMOS tube are connected with the grid electrode of the second NMOS tube; and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube and the output end of the low power domain drive enhancement circuit.
9. The high voltage level shift circuit of claim 7, wherein the high power domain drive enhancement circuit comprises an eighth PMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, and a ninth NMOS transistor; the source electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube are connected with the high-voltage input end of the high power domain; the source electrode of the eighth NMOS tube and the source electrode of the ninth NMOS tube are connected with the low-voltage input end of the high power domain; the grid electrode of the eighth PMOS tube and the grid electrode of the eighth NMOS tube are connected with the logic level output end; the drain electrode of the eighth PMOS tube, the drain electrode of the eighth NMOS tube and the grid electrode of the ninth PMOS tube are connected with the grid electrode of the ninth NMOS tube; and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the ninth NMOS tube and the output end of the high power domain drive enhancement circuit.
10. A DC-DC chip, characterized in that the DC-DC chip comprises a high voltage level shift circuit according to any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323080451.4U CN221151348U (en) | 2023-11-14 | 2023-11-14 | High-voltage level shift circuit and DC-DC chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323080451.4U CN221151348U (en) | 2023-11-14 | 2023-11-14 | High-voltage level shift circuit and DC-DC chip |
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| CN221151348U true CN221151348U (en) | 2024-06-14 |
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| CN202323080451.4U Active CN221151348U (en) | 2023-11-14 | 2023-11-14 | High-voltage level shift circuit and DC-DC chip |
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| CN (1) | CN221151348U (en) |
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- 2023-11-14 CN CN202323080451.4U patent/CN221151348U/en active Active
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