CN220933741U

CN220933741U - Test circuit

Info

Publication number: CN220933741U
Application number: CN202322408782.XU
Authority: CN
Inventors: 谢辉; 唐浯
Original assignee: Unicorn Electric Shenzhen Co ltd
Current assignee: Unicorn Electric Shenzhen Co ltd
Priority date: 2023-09-05
Filing date: 2023-09-05
Publication date: 2024-05-10
Anticipated expiration: 2033-09-05

Abstract

The utility model provides a test circuit, comprising: the device comprises a control circuit, a grid base voltage generating circuit, a source base voltage generating circuit and a test voltage generating circuit; the control circuit is respectively connected with the grid base voltage generating circuit, the source base voltage generating circuit and the test voltage generating circuit; the grid base voltage generating circuit is respectively connected with the source base voltage generating circuit and the test voltage generating circuit; the source base voltage generating circuit is connected with the test voltage generating circuit. The grid base voltage generating circuit generates a first base voltage and a first test voltage under the action of the control circuit; the source base voltage generating circuit generates a second base voltage under the action of the control circuit and the grid base voltage generating circuit; the test voltage generating circuit generates a second test voltage under the action of the control circuit, the grid base voltage generating circuit and the source base voltage generating circuit. The test circuit provided by the embodiment of the utility model has a simple structure and can effectively reduce the cost.

Description

Test circuit

Technical Field

The utility model relates to the technical field of display, in particular to a test circuit.

Background

Thin film transistor (Thin Film Transistor, TFT) liquid crystal display modules are widely used in various industries, and the TFT liquid crystal display modules include TFT display panels and Chip On Glass (COG). The detection for the TFT liquid crystal display module generally includes detection before the TFT liquid crystal display module is formed and detection after the TFT liquid crystal display module is formed.

Before the TFT liquid crystal display module is formed, a TFT display panel is included, and COG and the TFT display panel are not bound yet. The detection method before molding is commonly used: a special test box is purchased from a test company or a scheme company, and the TFT display panel is functionally tested by using the test box.

Because of the high cost of purchasing the cartridge, it is too costly for the tester, and therefore a lower cost test circuit is needed.

Disclosure of utility model

In view of the above, the present utility model provides a testing circuit for testing a TFT LCD module before molding, and reducing the cost.

In a first aspect, an embodiment of the present utility model provides a test circuit, including: the device comprises a control circuit, a grid base voltage generating circuit, a source base voltage generating circuit and a test voltage generating circuit;

The control circuit is respectively connected with the grid base voltage generating circuit, the source base voltage generating circuit and the test voltage generating circuit and is used for outputting a plurality of voltage signals and a plurality of control signals;

The grid base voltage generating circuit is respectively connected with the source base voltage generating circuit and the test voltage generating circuit; the grid base voltage generating circuit is used for generating a first base voltage and a first test voltage under the action of the control circuit and outputting the first base voltage to the source base voltage generating circuit and the test voltage generating circuit;

The source base voltage generating circuit is connected with the test voltage generating circuit and is used for generating a second base voltage under the action of the control circuit and the grid base voltage generating circuit and outputting the second base voltage to the test voltage generating circuit;

The test voltage generating circuit is used for generating a second test voltage under the action of the control circuit, the grid base voltage generating circuit and the source base voltage generating circuit.

The embodiment of the utility model provides a test circuit, which comprises a control circuit, a grid base voltage generating circuit, a source base voltage generating circuit and a test voltage generating circuit; the control circuit is used for generating a plurality of control signals and a plurality of voltage signals, so that the grid base voltage generating circuit can generate a first base voltage and a first test voltage under the action of the control circuit, and the first base voltage is output to the source base voltage generating circuit and the test voltage generating circuit; the source base voltage generating circuit can generate a source base voltage under the action of the control circuit and the grid base voltage generating circuit, and output the source base voltage to the test voltage generating circuit; the test voltage generating circuit generates a second test voltage under the action of the control circuit, the grid base voltage generating circuit and the source base voltage generating circuit. Detection of the TFT display panel may be achieved according to the first test voltage and the second test voltage. The test circuit provided by the embodiment of the utility model has a simple structure and can effectively reduce the cost.

Drawings

FIG. 1 is a schematic diagram of a test circuit according to an embodiment of the present utility model;

Fig. 2 is a schematic structural diagram of a control circuit according to an embodiment of the present utility model;

fig. 3 is a schematic diagram of a specific structure of a voltage control circuit according to an embodiment of the present utility model;

Fig. 4 is a schematic diagram of a specific structure of a signal control circuit according to an embodiment of the present utility model;

fig. 5 is a schematic diagram of a gate base voltage generating circuit according to an embodiment of the present utility model;

FIG. 6 is a schematic diagram of a specific structure of a first test voltage generating circuit and a second power voltage generating circuit according to an embodiment of the present utility model;

Fig. 7 is a schematic diagram of a specific structure of a gate high voltage generating circuit according to an embodiment of the present utility model;

fig. 8 is a schematic diagram of a specific structure of a gate low voltage generating circuit according to an embodiment of the present utility model;

FIG. 9 is a schematic diagram of a source base voltage generating circuit according to an embodiment of the present utility model;

FIG. 10 is a schematic diagram showing a result of processing an initial source square wave signal by a first square wave processing circuit according to an embodiment of the present utility model;

fig. 11 is a schematic diagram of a specific structure of a first adjusting circuit according to an embodiment of the present utility model;

FIG. 12 is a graph showing the result of shifting up the center value of the second square wave V ₀ according to the embodiment of the present utility model;

fig. 13 is a schematic diagram of a specific structure of a source turn-on voltage generating circuit according to an embodiment of the present utility model;

fig. 14 is a schematic diagram of a specific structure of a source turn-off voltage generating circuit according to an embodiment of the present utility model;

Fig. 15 is a schematic diagram of a specific structure of a source gray voltage generating circuit according to an embodiment of the present utility model;

FIG. 16 is a schematic diagram of a test voltage generating circuit according to an embodiment of the present utility model;

FIG. 17 is a schematic diagram of a source test voltage generating circuit according to an embodiment of the present utility model;

FIG. 18 is a schematic diagram showing a specific structure of a gate test voltage generating circuit according to an embodiment of the present utility model;

FIG. 19 is a diagram showing the result of generating different types of control signals according to an embodiment of the present utility model;

Fig. 20 is a schematic diagram of a test result of a red display screen according to an embodiment of the present utility model.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

The technical scheme of the utility model is described in detail below with reference to the accompanying drawings. The embodiments described below by referring to the drawings are illustrative and intended to explain the present utility model and should not be construed as limiting the utility model.

Fig. 1 is a schematic diagram of a test circuit according to an embodiment of the present utility model, and as shown in fig. 1, the test circuit includes a control circuit 10, a gate base voltage generating circuit 20, a source base voltage generating circuit 30, and a test voltage generating circuit 40.

Specifically, the control circuit 10 is connected to the gate base voltage generating circuit 20, the source base voltage generating circuit 30 and the test voltage generating circuit 40, respectively, and the control circuit 10 is configured to output a plurality of voltage signals and a plurality of control signals; the gate base voltage generating circuit 20 is connected to the source base voltage generating circuit 30 and the test voltage generating circuit 40, respectively; the gate base voltage generating circuit 20 is used for generating a first base voltage and a first test voltage under the action of the control circuit 10, and outputting the first base voltage to the source base voltage generating circuit 30 and the test voltage generating circuit 40.

The source base voltage generating circuit 30 is connected to the test voltage generating circuit 40, and the source base voltage generating circuit 30 is configured to generate a second base voltage under the action of the control circuit 10 and the gate base voltage generating circuit 20, and output the second base voltage to the test voltage generating circuit 40; the test voltage generating circuit 40 is used for generating a second test voltage under the action of the control circuit 10, the gate base voltage generating circuit 20 and the source base voltage generating circuit 30.

The voltage signals may be the same or different, which is not particularly limited in the embodiment of the present application; the plurality of control signals may be the same or different, and the embodiment of the present application is not particularly limited thereto. The first base voltage comprises a second power voltage AVDD, a gate high voltage VGH and a gate low voltage VGL; the second base voltage includes a Source-on voltage source_on, a Source-off voltage source_off, and a Source gray voltage source_gray; the second test voltage includes a source test voltage and a gate test voltage.

The specific structure of each circuit in the above-described test circuit is specifically described below with reference to the drawings.

First, a specific structure of the control circuit 10 is explained with reference to fig. 2, 3, and 4.

In order to reduce the size of the test circuit, the control circuit 10 employs a single chip microcomputer.

Fig. 2 is a schematic structural diagram of a control circuit according to an embodiment of the present utility model, and as shown in fig. 2, the control circuit 10 may include a voltage control circuit 101 and a signal control circuit 102.

Specifically, the voltage control circuit 101 is connected to the signal control circuit 102, the first power gate base voltage generation circuit 20, and the test voltage generation circuit 30, respectively, and the voltage control circuit 101 is configured to output a plurality of voltage signals to the signal control circuit 102, the gate base voltage generation circuit 20, and the test voltage generation circuit 30.

The signal control circuit 102 is connected to the gate base voltage generating circuit 20, the source base voltage generating circuit 30, and the test voltage generating circuit 40, respectively, and the signal control circuit 104 is configured to output a plurality of control signals to the gate base voltage generating circuit 20, the source base voltage generating circuit 30, and the test voltage generating circuit 40 under the action of the voltage control circuit 101.

Fig. 3 is a schematic diagram of a specific structure of a voltage control circuit according to an embodiment of the present utility model, as shown in fig. 3, the voltage control circuit 101 includes a fuse F1, a fuse F2, a fuse F3, a fuse F4, an ac capacitor C4, a dc capacitor C5, a resistor R13, and a light emitting diode led1.

Specifically, the first power supply is connected to an input terminal of the voltage control circuit 101, and is used for inputting the voltage VDD to the voltage control circuit 101; the positive electrode of the light emitting diode led1 is connected with the first end of the resistor R13, and the negative electrode of the light emitting diode led1 is grounded; the second end of the resistor R13 is connected with the input end of the voltage control circuit 101; the input terminal of the voltage control circuit 101 is further connected to the first terminal of the ac capacitor C4, the first terminal of the dc capacitor C5, the first terminal of the fuse F1, the first terminal of the fuse F2, the first terminal of the fuse F3, and the first terminal of the fuse F4, respectively.

The second end of the alternating current capacitor C4 and the second end of the direct current capacitor C5 are commonly grounded; the second end of the fuse F1 is connected with the first output end of the voltage control circuit 101, the second end of the fuse F2 is connected with the second output end of the voltage control circuit 101, the second end of the fuse F3 is connected with the third output end of the voltage control circuit 101 and the second end of the fuse F4 is connected with the fourth output end of the voltage control circuit 101.

The voltage control circuit 101 is configured to convert the first voltage VDD into four voltage signals and output the four voltage signals. The voltage control circuit 101 has a first output terminal outputting a first sub power voltage VDD1, a second output terminal outputting a second sub power voltage VDD2, a third terminal outputting a third sub power voltage VDD3, and a fourth terminal outputting a fourth sub power voltage VDD4. The required voltages can be subsequently supplied to the different circuits.

The voltage values of the first sub power supply voltage VDD1, the second sub power supply voltage VDD2, the third sub power supply voltage VDD3 and the fourth sub power supply voltage VDD4 may be the same or different, which is not particularly limited in the embodiment of the present utility model. Wherein the resistance value of the resistor R13 is 10 kiloohms (KΩ); the capacitance value of the AC capacitor C4 is 0.1 micro Farad (muF), and the forward withstand voltage value is 25 volts (V); the capacitance value of the direct current capacitor C5 is 47 mu F, and the forward withstand voltage value is 16V; the fuses F1-F4 are selected from FCC16, and rated current is 1.6A times (A), namely, when the current exceeds 1.6A, the fuses of the corresponding branches are fused, and the protection circuit is realized. It will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

Fig. 4 is a schematic diagram of a specific structure of a signal control circuit according to an embodiment of the present utility model, and as shown in fig. 4, a signal control circuit 102 may include a chip AT89S52 and a chip CON1.

Specifically, the chip AT89S52 is configured to output a first pulse width modulation signal PWM1, a second pulse width modulation signal PWM2, and a third pulse width modulation signal PWM3; the chip CON1 is configured to output an initial Source square wave signal source_signal, a first Source Control signal control_so1, a second Source Control signal control_so2, a third Source Control signal control_so3, a first gate Control signal control_tgo, a second gate Control signal control_tge, and a gray Control signal control_gray.

First, the chip AT89S52 is described, and the chip AT89S52 includes some peripheral circuits, such as a reset circuit, a crystal oscillator circuit, a switching circuit, and a chip resistor PR1. The RESET circuit comprises a RESET switch RESET, a resistor R14, a resistor R15 and a direct-current capacitor C3. The first end of the key switch RESET is connected with the first end of the resistor R15, and the second end of the key switch RESET is connected with the positive electrode of the direct-current capacitor C3. The negative electrode of the direct-current capacitor C3 is connected with the second end of the resistor R15, the second end of the resistor R15 is also connected with the first end of the resistor R14, and the second end of the resistor R14 is grounded. The positive electrode of the direct-current capacitor C3 is also connected with a fourth output end of the voltage control circuit 101 and is used for receiving a fourth sub-power supply voltage VDD4 output by the voltage control circuit 101; the negative electrode of the direct-current capacitor C3 is also connected with the No. 9 pin of the chip ATS89S 52.

The RESET circuit is used for enabling the test circuit to execute a program from the beginning and restarting the test circuit by pressing a RESET switch RESET when the test circuit is abnormal or disordered.

Wherein, the capacitance value of the direct current capacitor C3 is 10 mu F, and the forward voltage resistance value is 16V; the resistance value of the resistor R14 is 10KΩ; the resistance value of the resistor R15 is 33Ω. It will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

The crystal oscillator circuit comprises an alternating current capacitor C1, an alternating current capacitor C2 and a crystal oscillator generator Y1. The No. 1 pin of the crystal oscillator generator Y1 is respectively connected with the No. 19 pin of the chip AT89S52 and the first end of the alternating current capacitor C2, the No. 2 pin of the crystal oscillator generator Y1 is respectively connected with the No. 18 pin of the chip AT89S52 and the first end of the alternating current capacitor C1, and the second end of the alternating current capacitor C1 and the second end of the alternating current capacitor C2 are grounded. The crystal oscillator circuit is configured to provide clock signals of the signal Control circuit 102, and the signal Control circuit 102 may output different Control signals, that is, a first pulse width modulation signal PWM1, a second pulse width modulation signal PWM2, a third pulse width modulation signal PWM3, an initial Source square wave signal, a first Source Control signal control_so1, a second Source Control signal control_so2, a third Source Control signal control_so3, a first gate Control signal control_tgo, a second gate Control signal control_tge, a gray Control signal control_gray, and the like, according to the clock signals.

Wherein, the crystal oscillation frequency of the crystal oscillation generator Y1 is 12 megahertz (MHz); the capacitance of each of the ac capacitor C1 and the ac capacitor C2 was 20 picofarads (pF). It will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

The switch circuit comprises a switch S1, a switch S2 and a switch S3. The first ends of the switches S1 to S3 are all grounded, the second end of the switch S1 is connected with the No. 28 pin of the chip AT89S52, the second end of the switch S2 is connected with the No. 27 pin of the chip AT89S52, and the second end of the switch S3 is connected with the No. 26 pin of the chip AT89S 52. The switch S1 is used for indicating that the test circuit is in a test state, namely, the switch S1 is pressed, and the test circuit is in the test state; both switches S2 and S3 are used to indicate that the test circuit is in a storage state, i.e. switch S2 and/or switch S3 are pressed and the test circuit is in a storage state. In order to save cost, the switches S1 to S3 may be mechanical key switches. It is understood that the switches S1 to S3 may be other types of switches, such as electronic switches, and the embodiment of the present utility model is not limited thereto.

The chip resistor PR1 includes 8 resistors, and the sum of the resistances of the 8 resistors may be 10kΩ. The second ends of the 8 resistors are connected with a fourth output end of the voltage control circuit 101 and are used for receiving a fourth sub-power supply voltage VDD4; the first end of the first resistor is connected with the No. 39 pin of the chip AT89S52, the first end of the second resistor is connected with the No. 38 pin of the chip AT89S52, the first end of the third resistor is connected with the No. 37 pin of the chip AT89S52, the first end of the fourth resistor is connected with the No. 36 pin of the chip AT89S52, the first end of the fifth resistor is connected with the No. 35 pin of the chip AT89S52, the first end of the sixth resistor is connected with the No. 34 pin of the chip AT89S52, the first end of the seventh resistor is connected with the No. 33 pin of the chip AT89S52, and the first end of the eighth resistor is connected with the No. 32 pin of the chip AT89S 52.

The chip resistor PR1 is used to provide a stable resistance value. The number of resistors in the chip resistor PR1 may be increased or decreased according to actual needs, or the sum of the resistors may be increased according to actual needs, which is not particularly limited in the embodiment of the present utility model.

Next, the chip AT89S52 is described, and pin No. 20 of the chip AT89S52 is grounded; the pins 40 and 31 of the chip AT89S52 are connected with the fourth output end of the voltage control circuit 101 and are used for receiving the fourth sub-power supply voltage VDD4; the pin 23 of the chip AT89S52 is used for generating the first PWM signal PWM1, the pin 22 of the chip AT89S52 is used for generating the second PWM signal PWM2, and the pin 21 of the chip AT89S52 is used for generating the third PWM signal PWM3.

The connection relation between the chip CON1 and the AT89S52 is as follows: the fourth sub-power supply voltage of the voltage control circuit 101 is connected to the 1 st pin and the 20 nd pin of the chip CON1, the 39 th pin of the chip AT89S52 is connected to the 2 nd pin of the chip CON1, the 38 th pin of the chip AT89S52 is connected to the 3 rd pin of the chip CON1, the 37 th pin of the chip AT89S52 is connected to the 4 th pin of the chip CON1, the 36 th pin of the chip AT89S52 is connected to the 5 th pin of the chip CON1, the 35 th pin of the chip AT89S52 is connected to the 6 th pin of the chip CON1, the 34 th pin of the chip AT89S52 is connected to the 7 th pin of the chip CON1, the 33 th pin of the chip AT89S52 is connected to the 8 th pin of the chip CON1, the 32 th pin of the chip AT89S52 is connected to the 9 th pin of the chip CON1, and the 6 th pin of the chip CON 89S52 is connected to the 19 th pin of the chip AT89S 52.

The 18 th pin of the chip CON1 outputs an initial Source square wave signal source_signal, the 17 th pin of the chip CON1 outputs a first Source Control signal control_so1, the 16 th pin of the chip CON1 outputs a second Source Control signal control_so2, the 15 th pin of the chip CON1 outputs a third Source Control signal control_so3, the 14 th pin of the chip CON1 outputs a first gate Control signal control_tgo, the 13 th pin of the chip CON1 outputs a second gate Control signal control_tge and the 12 th pin of the chip CON1 outputs a gray Control signal control_gray.

Next, the structure of the gate base voltage generation circuit will be described with reference to fig. 5, 6, 7, and 8.

Fig. 5 is a schematic diagram of a gate base voltage generating circuit according to an embodiment of the present utility model, and as shown in fig. 5, the gate base voltage generating circuit 20 includes a first test voltage generating circuit 201, a second power voltage generating circuit 202, a gate high voltage generating circuit 203 and a gate low voltage generating circuit 204.

Specifically, the second power supply voltage generation circuit 202 is connected to the voltage control circuit 101, the signal control circuit 102, the first test voltage generation circuit 201, and the source base voltage generation circuit 30, respectively; the second power supply voltage generating circuit 202 is configured to generate a second power supply voltage AVDD under the action of the voltage control circuit 101 and the signal control circuit 102, and output the second power supply voltage AVDD to the source base voltage generating circuit 30 and the first test voltage generating circuit 40; the first test voltage generating circuit 40 is used for generating a first test voltage SW under the action of the second power voltage AVDD. The voltage value of the first test voltage SW is higher than the voltage value of the second power voltage AVDD.

The gate high voltage generation circuit 203 is connected to the voltage control circuit 101, the signal control circuit 102, and the test voltage generation circuit 40, respectively; the gate high voltage generation circuit 203 is configured to generate the gate high voltage VGH by the voltage control circuit 101 and the signal control circuit 102, and output the gate high voltage VGH to the test voltage generation circuit 40.

The gate low voltage generating circuit 204 is connected to the voltage control circuit 101, the signal control circuit 102, the source base voltage generating circuit 30 and the test voltage generating circuit 40, respectively; the gate low voltage generation circuit 204 is configured to generate the gate low voltage VGL by the voltage control circuit 101 and the signal control circuit 102, and output the gate low voltage VGL to the source base voltage generation circuit 30 and the test voltage generation circuit 40.

Fig. 6 is a schematic diagram of a specific structure of a first test voltage generating circuit and a second power voltage generating circuit according to an embodiment of the present utility model, as shown in fig. 6, the second power voltage generating circuit 202 includes a first dc-dc controller U3 and peripheral components thereof, and the first test voltage generating circuit includes a first charge pump circuit.

In order to save cost and reduce the volume of the test circuit, the first direct current to direct current controller U3 selects the chip AP3012. The peripheral components of the first dc-dc controller U3 include an ac capacitor C16, an ac capacitor C17, a resistor R28, a resistor R29, a schottky diode D4, and an inductor L3.

Specifically, the first voltage terminal Vin of the chip AP3012 (i.e. pin No. 5 of the chip AP 3012) is connected to the third output terminal of the voltage control circuit 101, and is configured to receive the third sub-power supply voltage VDD3; pin 5 of the chip AP3012 is further connected to the first end of the ac capacitor C16 and the first end of the inductor L3, respectively.

The second end of the alternating current capacitor C16 is grounded; a second end of the inductor L3 is connected to a first node of the chip AP 3012; pin 1 of the chip AP3012 is connected with a first node of the chip AP 3012; the positive electrode of the schottky diode D4 is connected to the first node of the chip AP3012, and the negative electrode of the schottky diode D4 is connected to the first end of the resistor R28 and the first end of the ac capacitor C17, respectively.

The second end of the resistor R28 is respectively connected with the No. 3 pin of the chip AP3012 and the first end of the resistor R29; the second end of the resistor R29 and the second end of the alternating current capacitor C17 are grounded; second voltage terminal of chip AP3012The pin No. 21 of the chip AT89S52 in the signal control circuit 102 is connected (i.e., pin No. 4 of the chip AP 3012) for receiving the third pulse width modulation signal PWM3.

The node of the first end of the ac capacitor C17 connected to the cathode of the schottky diode D4 is referred to as a second node of the chip AP 3012; pin number 2 of chip AP3012 is grounded. For easy connection, a wire is introduced, a first end of which is connected to the second node of the chip AP3012, and a second end of which is an output terminal TP4 of the second power supply voltage generating circuit.

Wherein, the first node of the chip AP3012 is used for outputting the waveform of the SW-SW; the second node of the chip AP3012 and the output terminal TP4 of the second power supply voltage generating circuit are configured to output the second power supply voltage AVDD, which is a negative voltage.

The capacity values of the alternating current capacitor C16 and the alternating current capacitor C17 are 1 mu F, and the forward voltage withstand values are 25V; the resistance value of the resistor R28 is 3.7KΩ; the resistance value of the resistor R29 is 510 omega; the schottky diode D4 is IN5819; the model of the inductor L3 is PS4018, 100M represents that the tolerance range of the inductor L3 is 100+/-20%, the working frequency of the inductor L3 is 100 kilohertz (KHz), and the inductance is 10 microhenry (mu H); it will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

The second power supply voltage generating circuit 202 operates according to the following principle: when pin 1 of the chip AP3012 is turned on, the inductor L3 charges, the voltage at the first node of the chip AP3012 is SW-SW, at this time SW-SW is the voltage of ground (i.e. 0V), the schottky diode D4 is in an off state, the capacitor C17 discharges, and the voltage at the second node of the chip AP3012 is the second power supply voltage AVDD.

After a period of time, pin 1 of the chip AP3012 is turned off, the inductor L3 discharges, the voltage of the first node of the chip AP3012 is SW-SW, at this time SW-SW is high voltage, the schottky diode D4 is in an on state, the capacitor C17 charges, and the voltage of the second node of the chip AP3012 is still the second power supply voltage AVDD. The capacitor C17 may maintain the voltage of the second node of the chip AP3012 at the second power supply voltage AVDD at all times.

The first charge pump circuit (i.e., the third supply voltage generating circuit) includes an ac capacitor C12, an ac capacitor C13, an ac capacitor C14, an ac capacitor C15, a resistor R26, a resistor R27, a first rectifying diode 1, a second rectifying diode 2, a zener diode ZD1, and a transistor Q1.

Specifically, a first voltage end of the first charge pump circuit is connected with a first node of the second power supply voltage generating circuit and is used for receiving the SW-SW waveform; the second voltage end of the first charge pump circuit is connected with a second node of the second power supply voltage generating circuit and is used for receiving the second power supply voltage AVDD.

The first end of the alternating current capacitor C12 is connected with the first voltage end of the first charge pump circuit, and the second end of the alternating current capacitor C12 is respectively connected with the cathode (namely the negative electrode) of the first rectifying diode 1 and the anode of the second rectifying diode 2; the anode of the first rectifying diode 1 is connected to the second voltage terminal of the first charge pump circuit. The cathode of the second rectifying diode 2 is respectively connected with the first end of the alternating current capacitor C13 and the first end of the resistor R26; the first end of the ac capacitor C13 is further connected to the first end of the resistor R26, and the second end of the ac capacitor C13 is grounded. The first end of the resistor R26 is also connected with the collector of the triode Q1, and the second end of the resistor R26 is respectively connected with the base of the triode Q1, the first end of the alternating current capacitor C14 and the cathode of the zener diode ZD 1.

The second end of the alternating current capacitor C14 and the anode (i.e. the positive electrode) of the zener diode ZD1 are grounded; the emitter of the triode Q1 is respectively connected with the first end of the alternating current capacitor C15 and the first end of the resistor R27; the second terminal of ac capacitor C15 and the second terminal of resistor R27 are both grounded. For easy connection, a wire is introduced, a first end of the wire is connected to a first end of the resistor R27, a second end of the wire is an output end TP5 of the third power supply voltage generating circuit, and a first test voltage SW is output, and the first test voltage SW is a positive voltage.

Wherein, the capacity value of the alternating current capacitor C12 is 100 nano Farad (nF), and the forward voltage withstand value is 50V; the capacitance value of the alternating current capacitor C13 is 470nF, and the forward withstand voltage value is 50V; the capacitance value of the alternating current capacitor C15 is 1 mu F, and the forward withstand voltage value is 35V; the alternating current capacitor C14 is a standby capacitor; the resistance value of the resistor R26 is 13KΩ; the resistance value of the resistor R27 is 100KΩ; the model of the first rectifying diode 1 and the second rectifying diode 2 is BAT54S; the model number of the zener diode ZD1 is LBZX C20LT1G, and the supply voltage should be 20V; the model of the triode Q1 is BC850B/SOT-23. It will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

The first charge pump circuit is used for converting the second power supply voltage AVDD into a first test voltage SW, and the voltage value of the first test voltage SW is greater than that of the second power supply voltage AVDD. The first charge pump circuit (first test voltage SW) operates on the principle that: when pin 1 of the chip AP3012 is turned on, the inductor L3 charges, the voltage at the first node of the chip AP3012 is SW-SW, and at this time SW-SW is the voltage of ground (i.e., 0V), the schottky diode D4 is in an off state, the capacitor C17 discharges, the voltage at the second node of the chip AP3012 is the second power supply voltage AVDD, and the second power supply voltage AVDD is obtained after the capacitor C2 is fully charged by charging the capacitor C12 through the first rectifying tube 1.

After a period of time, when pin 1 of the chip AP3012 is turned off, the inductor L3 discharges, the voltage of the first node of the chip AP3012 is SW-SW, at this time SW-SW is high voltage, the capacitor C12 discharges, the magnitude of the discharged voltage is the second power supply voltage AVDD, the second power supply voltage AVDD flows through the second rectifying tube 2, the schottky diode D4 is in a conducting state, the capacitor C17 charges, the voltage of the second node of the chip AP3012 is still the second power supply voltage AVDD, and the second power supply voltage AVDD flows through the first rectifying tube 1 and the second rectifying tube 2, so that the cathode of the second rectifying tube 2 outputs twice the second power supply voltage AVDD. The doubled second power voltage AVDD is subjected to the voltage stabilizing effect of the zener diode ZD1 and the current spreading effect of the triode Q1 to finally form the first test voltage SW. The first test voltage SW is used to turn on all driving transistors in the TFT display panel.

Fig. 7 is a schematic diagram of a specific structure of a gate high voltage generating circuit according to an embodiment of the present utility model, and as shown in fig. 7, the gate high voltage generating circuit 203 includes a second dc-dc converter controller U1 and peripheral components thereof.

In order to save cost and reduce the volume of the test circuit, the second direct current-to-direct current controller U1 selects the chip AP3012. The peripheral components of the second dc-dc converter U1 include an ac capacitor C18, an ac capacitor C19, a resistor R30, a resistor R31, a schottky diode D5, and an inductor L1.

Specifically, the first voltage terminal Vin of the chip AP3012 (i.e. pin No. 5 of the chip AP 3012) is connected to the first output terminal of the voltage control circuit 101, and is configured to receive the first sub-power supply voltage VDD1; pin 5 of the chip AP3012 is further connected to the first end of the ac capacitor C18 and the first end of the inductor L1, respectively. The second end of the alternating current capacitor C18 is grounded; the second end of the inductor L1 is connected to a pin 1 of the chip AP 3012; pin 1 of the chip AP3012 is also connected with the anode of the Schottky diode D5; the cathode of the schottky diode D5 is connected to the first terminal of the resistor R30 and the first terminal of the ac capacitor C19, respectively. The second end of the resistor R30 is respectively connected with the No. 3 pin of the chip AP3012 and the first end of the resistor R31; the second end of the resistor R31 and the second end of the alternating current capacitor C19 are grounded; second voltage terminal of chip AP3012(I.e., pin 4 of the chip AP 3012) is connected to pin 23 of the chip AT89S52 in the signal control circuit 102, for receiving the first pulse width modulation signal PWM1; pin number 2 of chip AP3012 is grounded.

For convenience of connection, a wire is introduced, a first end of the wire is connected to a first end of the ac capacitor C19, a second end of the wire is an output end TP2 of the gate high voltage generating circuit, the gate high voltage VGH is output, and the gate high voltage VGH is a positive voltage.

The capacity values of the alternating current capacitor C18 and the alternating current capacitor C19 are 1 mu F, and the forward voltage withstand values are 25V; the resistance value of the resistor R30 is 5.23KΩ; the resistance value of the resistor R31 is 510 omega; the schottky diode D5 is IN5819; the model of the inductor L1 is PS4018, 100M represents that the tolerance range of the inductor L1 is 100+/-20%, the working frequency of the inductor L1 is 100KHz, and the inductance is 10 mu H; it will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

The operation principle of the gate high voltage generating circuit 203 is similar to that of the second power voltage generating circuit 202, and will not be described here again.

Fig. 8 is a schematic diagram of a specific structure of a gate low voltage generating circuit according to an embodiment of the present utility model, and as shown in fig. 8, the gate low voltage generating circuit 204 includes a second charge pump circuit, a third dc-dc controller U2 and peripheral components thereof.

In order to save cost and reduce the volume of the test circuit, the third DC-DC controller U2 selects the chip AP3012. The peripheral components of the third dc-dc converter U2 include an ac capacitor C10, an ac capacitor C11, a resistor R24, a resistor R25, a schottky diode D2, and an inductor L2.

Specifically, the first voltage terminal Vin of the chip AP3012 (i.e. pin No. 5 of the chip AP 3012) is connected to the second output terminal of the voltage control circuit 101, and is configured to receive the second sub-power supply voltage VDD2; the pin 5 of the chip AP3012 is further connected to the first end of the ac capacitor C10 and the first end of the inductor L2, respectively. The second end of the alternating current capacitor C10 is grounded; a second end of the inductor L2 is connected to a first node of the chip AP 3012; pin 1 of the chip AP3012 is connected with a first node of the chip AP 3012; the positive electrode of the schottky diode D2 is connected to the first node of the chip AP3012, and the negative electrode of the schottky diode D2 is connected to the first end of the resistor R24 and the first end of the ac capacitor C11, respectively. The second end of the resistor R24 is respectively connected with the No. 3 pin of the chip AP3012 and the first end of the resistor R25; the second end of the resistor R25 and the second end of the alternating current capacitor C11 are grounded; second voltage terminal of chip AP3012The pin No. 22 of the chip AT89S52 in the signal control circuit 102 is connected (i.e., pin No. 4 of the chip AP 3012) for receiving the second pulse width modulation signal PWM2. Pin number 2 of chip AP3012 is grounded.

Wherein, the first node of the chip AP3012 is used for outputting a GVL-SW waveform, which is a positive voltage. The capacity values of the alternating current capacitor C10 and the alternating current capacitor C11 are 1 mu F, and the forward voltage withstand values are 25V; the resistance value of the resistor R24 is 3.57KΩ; the resistance value of the resistor R25 is 510 omega; the schottky diode D2 is IN5819; the model of the inductor L2 is PS4018, 100M represents that the tolerance range of the inductor L3 is 100+/-20%, the working frequency of the inductor L3 is 100 kilohertz (KHz), and the inductance is 10 microhenry (mu H); it will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

The principle of generating the GHL-SW waveform is similar to that of the second power supply voltage generating circuit 202, and will not be described here again.

The second charge pump circuit includes an ac capacitor C9, an ac capacitor C8, an ac capacitor C7, an ac capacitor C6, a resistor R23, a resistor R22, a third rectifying diode, a fourth rectifying diode, a zener diode ZD2, and a triode Q2.

Specifically, the voltage terminal of the second charge pump circuit is connected to the first node of the chip AP3012 for receiving the VGL-SW waveform. The first end of the alternating current capacitor C9 is connected with the voltage end of the second charge pump circuit, and the second end of the alternating current capacitor C9 is respectively connected with the cathode of the third rectifying diode and the anode of the fourth rectifying diode; the anode of the third rectifier diode is connected to the first end of the resistor R23. The cathode of the fourth rectifying diode is grounded; the first end of the resistor R23 is also connected with the collector of the triode Q1, and the second end of the resistor R23 is respectively connected with the base of the triode Q1, the first end of the alternating current capacitor C8 and the cathode of the zener diode ZD 2. The first end of the alternating current capacitor C7 is connected with the base electrode of the triode Q1, and the second end of the alternating current capacitor C7, the anode (namely the positive electrode) of the zener diode ZD1 and the second end of the alternating current capacitor C8 are grounded; the emitter of the triode Q2 is respectively connected with the first end of the alternating current capacitor C6 and the first end of the resistor R22; the second terminal of ac capacitor C6 and the second terminal of resistor R22 are both grounded. For easy connection, a wire is introduced, a first end of the wire is connected to a first end of the resistor R22, and a second end of the wire is an output end TP3 of the gate low voltage generating circuit, outputting the gate low voltage VGL.

Wherein, the capacitance value of the alternating current capacitor C9 is 0.1 mu F, and the forward withstand voltage value is 25V; the capacitance value of the alternating current capacitor C8 is 470nF, and the forward withstand voltage value is 25V; the capacitance value of the alternating current capacitor C6 is 1 mu F, and the forward withstand voltage value is 25V; the alternating-current capacitor C7 is a standby capacitor; the resistance value of the resistor R23 is 6.8KΩ; the resistance value of the resistor R22 is 100KΩ; the model of the third rectifying diode and the fourth rectifying diode is BAT54S; the model number of the zener diode ZD2 is LBZX C10LT1G; the model of the triode Q2 is BC857B/SOT-23. It will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

The second charge pump circuit is used for converting VGL-SW of positive voltage into negative voltage, namely into grid low voltage VHL. The working principle of the second charge pump circuit is similar to that of the first charge pump, and will not be described here again.

Next, a specific structure of the source base voltage generation circuit will be described with reference to fig. 9 to 15.

Fig. 9 is a schematic diagram of a source base voltage generating circuit according to an embodiment of the present utility model, and as shown in fig. 9, the source base voltage generating circuit 30 includes a source-on voltage generating circuit 301, a source-off voltage generating circuit 302, and a source gray voltage generating circuit 302.

Specifically, the Source open voltage generating circuit 301 is connected to the gate low voltage generating circuit 204, the second power voltage generating circuit 202, the signal control circuit 102 and the test voltage generating circuit 40, respectively, and the Source open voltage generating circuit 301 is configured to generate a Source open voltage source_on under the action of the gate low voltage generating circuit 204, the second power voltage generating circuit 202 and the signal control circuit 102, and output the Source open voltage source_on to the test voltage generating circuit 40.

The Source turn-off voltage generating circuit 303 is connected to the gate low voltage generating circuit 204, the second power voltage generating circuit 202, the signal control circuit 102 and the test voltage generating circuit 40, respectively, and the Source turn-off voltage generating circuit 302 is configured to generate a Source turn-off voltage source_off under the action of the gate low voltage generating circuit 204, the second power voltage generating circuit 202 and the signal control circuit 102, and output the Source turn-off voltage source_off to the test voltage generating circuit 40.

The Source gray voltage generating circuit 303 is respectively connected to the gate low voltage generating circuit 204, the second power voltage generating circuit 202, the signal control circuit 102 and the test voltage generating circuit 40, and the Source gray voltage generating circuit 303 is configured to generate a Source gray voltage source_gray under the action of the gate low voltage generating circuit 204, the second power voltage generating circuit 202 and the signal control circuit 102, and output the Source gray voltage source_gray to the test voltage generating circuit 40.

As an alternative embodiment, the source-on voltage generation circuit 301, the source-off voltage generation circuit 302, and the source gradation voltage generation circuit 303 may be specific circuits.

Taking the source-open voltage generating circuit 301 as an example, the source-open voltage generating circuit 301 includes a first square-wave processing circuit and a first adjusting circuit connected. The first square wave processing circuit comprises a capacitive element and is used for processing an initial Source square wave signal source_signal; the first adjusting circuit comprises an amplitude adjusting circuit and a central value adjusting circuit, the amplitude adjusting circuit is used for adjusting the amplitude of the processed initial Source square wave signal source_signal, and the central value adjusting circuit is used for adjusting the central value of the signal output by the amplitude adjusting circuit; further, in order to improve the signal quality of the Source open voltage source_on, the first adjusting circuit may further include a voltage follower circuit.

The TFT display panel belongs to a liquid crystal display, and the driving voltage required by liquid crystal is alternating current, and the direct current can lead to polarization of the liquid crystal; each pixel of the TFT display panel has a transistor, and the voltage of the liquid crystal needs to use-V _ft as a reference voltage (abbreviated as a common voltage Vcom) because of the existence of a disturbing voltage (abbreviated as V _ft) in the transistor, so that the voltage of the liquid crystal in the positive and negative periods does not have a direct current component.

In the present embodiment, in order to simplify the common voltage Vcom, the common voltage in the TFT display panel is grounded, and the voltages of the positive and negative half periods of the initial Source square wave signal source_signal are adjusted so that the positive and negative half periods of the actual voltage on the liquid crystal are symmetrical after passing through the transistor, and no direct current component exists.

Specifically, a first end of the first square wave processing circuit is connected to pin 18 of the chip CON1 in the signal control circuit 102, receives an initial Source square wave signal source_signal output by the signal control circuit 102, and a second end of the first square wave processing circuit is connected to a first voltage end of the first adjusting circuit; the first square wave processing circuit is used for processing the initial Source square wave signal source_signal so that the amplitude range of the initial Source square wave signal source_signal is changed.

As a result of the processing, referring to fig. 10, a schematic diagram of a result of processing an initial Source square wave signal by a first square wave processing circuit according to an embodiment of the present utility model is shown in fig. 10, wherein a waveform of the initial Source square wave signal source_signal is shown in fig. 10 (a), an amplitude range of the initial Source square wave signal source_signal is 0V to 5V, that is, a high level of the initial Source square wave signal source_signal is 5V, and a low level of the initial Source square wave signal source_signal is 0V.

Since the first square wave circuit comprises a capacitor and has the function of passing alternating current and blocking direct current, the direct current component in the initial Source square wave signal source_signal can be filtered out, and only the alternating current component is reserved. The final result of the processed Source square wave signal source_signal is shown in fig. 10 (b), and the amplitude of the processed Source square wave signal source_signal ranges from-2.5V to 2.5V. For convenience of description, the processed initial Source square wave signal source_signal will be referred to as a first square wave V ₁.

Fig. 11 is a schematic diagram of a specific structure of a first adjusting circuit according to an embodiment of the present utility model, where, as shown in fig. 11, the first adjusting circuit includes an amplitude adjusting circuit, a voltage follower circuit, and a center value adjusting circuit. The amplitude adjusting circuit comprises an inverting amplifying circuit, and the central value adjusting circuit comprises a subtracting circuit.

Specifically, the circuit shown in (a) in fig. 11 is an inverting amplifier circuit including a first operational amplifier A1, a first input resistor R _a, and a first feedback resistor R _f.

Specifically, the inverting input terminal (i.e., "-" terminal) of the first operational amplifier A1 is connected to the second terminal of the first input resistor R _a and the first terminal of the first feedback resistor R _f, respectively; a first end of the first input resistor R ₁ is connected to a second end of the first square wave processing circuit (not shown), and a first end of the first input resistor R ₁ is a first voltage end of the first adjusting circuit; the second end of the first feedback resistor R _f is connected with the output end of the first operational amplifier A1; the non-inverting input (i.e., the "+" terminal) of the first operational amplifier A1 is grounded. The inverting amplification circuit is used for adjusting the amplitude of the first square wave V ₁ and outputting an amplitude-modulated square wave V ₀. The amplitude modulated square wave V ₀ has the relationship with the first square wave V ₁: v ₀＝-(R_f/R_a)*V₁.

By the inverting amplifier circuit, the first square wave V ₁ is amplified by R _f/R_a times, and since the source_signal is already adjusted by the first square wave processing circuit to an ac signal (i.e., the first square wave V ₁) symmetrical about the ground (0V), the positive and negative half cycles of the first square wave V ₁ are also amplified by equal ratio, and for driving the liquid crystal, the positive and negative inversion does not affect the operation of the liquid crystal.

It should be noted that, the first feedback resistor R _f is a variable resistor, and by using the variable resistor, the resistance value of the feedback resistor can be flexibly adjusted, so as to adjust the gain of the inverting amplifying circuit, so that the amplitude of the first square wave V ₁ can be flexibly adjusted. Therefore, the TFT display panel can display red, green, blue, white, black, odd horizontal bars, even horizontal bars and other pictures, and also can display gray pictures;

the circuit shown in (b) in fig. 11 is a voltage follower circuit including a second operational amplifier A2.

Specifically, the inverting input terminal of the second operational amplifier A2 is connected to the output terminal of the second operational amplifier A2, the non-inverting input terminal of the second operational amplifier A2 (i.e., the second voltage terminal of the first adjusting circuit) is connected to the gate low voltage VGL and the second power supply voltage AVDD through a variable resistor (not shown), respectively, and the output terminal of the second operational amplifier A2 outputs the third square wave V ₃. For convenience of description, the voltage commonly supplied to the non-inverting input terminal of the second operational amplifier A2 by the gate low voltage VGL and the second power supply voltage AVDD is hereinafter referred to as a second square wave V ₂.

The relationship of the third square wave V ₃ and the second square wave V ₂ is: v ₃＝V₂ the resistance of the variable resistor.

The circuit shown in fig. 11 (c) is a subtracting circuit including: the third operational amplifier A3, the second input resistor R _b, the second feedback resistor R _c, the third input resistor R _d, and the pull-down resistor R _e.

Specifically, a first end of the second input resistor R _b is connected to the output end of the second operational amplifier A2, and a second end of the second input resistor R _b is connected to the inverting input end of the third operational amplifier A3; the first end of the second feedback resistor R _c is connected with the inverting input end of the third operational amplifier A3, and the second end of the second feedback resistor R _c is connected with the output end of the third operational amplifier A3; the first end of the pull-down resistor R _e is connected with the non-inverting input end of the third operational amplifier A3, and the second end of the pull-down resistor R _e is grounded; the first end of the third input resistor R _d is connected to the output end of the first operational amplifier A1, and the second end of the third input resistor R _d is connected to the non-inverting input end of the third operational amplifier A3. The output end of the third operational amplifier A3 is an output end of the first adjusting circuit, and outputs the Source open voltage source_on.

The relationship between the Source open voltage source_on and the third square wave V ₃, amplitude modulated square wave V ₀ is: source open voltage Source_on＝[R_e/(R_d+R_e)]*[(R_b+R_c)/R_b]*V₀-(R_c/R_b)*V₃. when R _e＝R_d,R_c＝R_b, one can get: source_on=v ₀-V₃.

The subtracting circuit is used for adjusting the central value of the second square wave V ₀, and the principle is as follows: in the case of fixing the second square wave V ₀, the value of the third voltage V ₃ is adjusted, so that the second square wave V ₀ can be moved vertically, and the adjusted second square wave V ₀ is the Source open voltage source_on.

Since the common voltage of the TFT display panel is grounded in the present embodiment, the center value of the second square wave V ₀ needs to be shifted up by aV in the case where the requirement for the common voltage VCOM voltage is-aV; in the case where the requirement for the common voltage VCOM voltage is aV, the center value of the second square wave V ₀ needs to be shifted down by aV. An exemplary illustration is made by taking the center value of the second square wave V ₀ as an example.

Fig. 12 is a schematic diagram showing a result of shifting up the center value of the second square wave V ₀ according to the embodiment of the present utility model, as shown in fig. 12, the waveform diagram of the second square wave V ₀ is shown in fig. 12 (a), the center value of the second square wave V ₀ is-aV, and after the subtraction circuit, the center value of the second square wave V ₀ is adjusted to 0V, i.e. the center value of the Source open voltage source_on is 0V. The high level of the second square wave V ₀ is VSH, the low level of the second square wave V ₀ is VSL, the high level of the Source open voltage source_on is vsh+a, and the low level of the Source open voltage source_on is vsl+a. The first adjusting circuit formed by the operational amplifier can improve the driving capability of the Source open voltage source_on.

Note that, the specific circuit structures of the source off voltage generating circuit 302 and the source gray voltage generating circuit 303 are similar to the specific structure of the source on voltage generating circuit 301, and will not be repeated here.

In order to reduce the volume of the test circuit, the source-on voltage generation circuit 301, the source-off voltage generation circuit 302, and the source gray voltage generation circuit 303 may all include the chip LM324 and its peripheral components.

Fig. 13 is a schematic diagram of a specific structure of a source turn-on voltage generating circuit according to an embodiment of the present utility model, as shown in fig. 13, peripheral components of a chip LM324 include a first adjustable resistor VR3, a second adjustable resistor VR4, a resistor R40, a resistor R41, a resistor R42, a resistor R43, a resistor R44, a resistor R45, a resistor R46, and a resistor R47; the chip LM324 includes four sets of operational amplifiers, operational amplifier a, operational amplifier B, operational amplifier C, and operational amplifier D, respectively.

The pins of the operational amplifier A group comprise pins 1-3, the pins of the operational amplifier B group comprise pins 5-7, the pins of the operational amplifier C group comprise pins 8-10, and the pins of the operational amplifier D group comprise pins 12-14.

In the embodiment of the utility model, three groups of operational amplifiers, namely an operational amplifier A group, an operational amplifier B group and an operational amplifier C group, are selected. The operational amplifier A group is an inverting amplifying circuit, the operational amplifier B group is a voltage follower circuit, and the operational amplifier C group is a subtracting circuit.

Specifically, pin 1 of the chip LMS324 is connected to the first end of the first adjustable resistor VR3, and pin 1 of the chip LMS324 is connected to pin 10 of the chip LMS324 through the resistor R47; the pin 2 of the chip LMS324 is respectively connected with the second end of the resistor R40, the first end of the first adjustable resistor VR3 and the adjusting end; the first end of the resistor R40 is connected to the second end of the capacitor C21, and the first end of the resistor R40 is the first voltage end of the source open voltage generating circuit 301; the first end of the capacitor C21 is connected to pin 18 of the chip CON1 in the signal control circuit 102, receives the initial Source square wave signal source_signal output by the signal control circuit 102, and the capacitor C21 is the first square wave processing circuit.

Pin 3 of the chip LMS324 is grounded through resistor R41; the pin 4 of the chip LMS324 is connected to the second power voltage AVDD (i.e., the output terminal TP4 of the first dc-dc controller U3); the pin 5 of the chip LMS324 is connected with the adjusting end of the second adjustable resistor VR 4; the first end of the second adjustable resistor VR4 is connected to the second power voltage AVDD through a resistor R42, and the second end of the second adjustable resistor VR4 is connected to the gate low voltage VGL through a resistor R43.

The pin 6 of the chip LMS324 is respectively connected with the pin 7 of the chip LMS324 and the second end of the resistor R45; the first end of the resistor R45 is respectively connected with the second end of the resistor R44 and the No. 9 pin of the chip LMS 324; the first end of the resistor R44 is connected with the No. 8 pin of the chip LMS 324; a first end of the resistor R46 is connected to pin 10 of the chip LMS324, and a second end of the resistor R46 is grounded.

The 11 th pin of the chip LMS324 is connected to the gate low voltage VGL, the 12 th pin of the chip LMS324 is grounded, and the 13 th pin and the 14 th pin of the chip LMS324 are connected. For convenience of connection, a wire is introduced, a first end of the wire is connected to pin 8 of the chip LM324, and a second end of the wire is an output end TP7 of the Source open voltage generating circuit, outputting the Source open voltage source_on.

Wherein, the resistance value of the first adjustable resistor VR3 is 100KΩ; the resistance value of the second adjustable resistor VR4 is 100KΩ; the resistance value of the resistor R40 is 10KΩ; the resistance values of the resistor R41, the resistor R42 and the resistor R43 are all 0 omega, and are all used as standby resistors; the resistance values of the resistor R44, the resistor R45, the resistor R46 and the resistor R47 are all 51KΩ; the capacity of the ac capacitor C21 was 4.7 μf, and the forward withstand voltage was 10V. It will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

Fig. 14 is a schematic diagram of a specific structure of a source turn-off voltage generating circuit according to an embodiment of the present utility model, as shown in fig. 14, peripheral components of a chip LM324 include a third adjustable resistor VR1, a fourth adjustable resistor VR2, a resistor R32, a resistor R33, a resistor R34, a resistor R35, a resistor R36, a resistor R37, and a resistor R38; the chip LM324 includes four operational amplifiers, namely, an operational amplifier a, an operational amplifier B, an operational amplifier C, and an operational amplifier D, which are identical to the chip LM324 in the source turn-on voltage generating circuit, and are not described herein.

Specifically, pin 1 of the chip LMS324 is connected to the second end of the third adjustable resistor VR1, and pin 1 of the chip LMS324 is connected to pin 10 of the chip LMS324 through the resistor R39; the pin 2 of the chip LMS324 is respectively connected with the second end of the resistor R32, the first end and the adjusting end of the third adjustable resistor VR 1; the first end of the resistor R32 is connected to the second end of the capacitor C20, and the first end of the resistor R32 is the first voltage end of the source turn-off voltage generating circuit 302; the first end of the capacitor C20 is connected to pin 18 of the chip CON1 in the signal control circuit 102, receives the initial Source square wave signal source_signal output by the signal control circuit 102, and the capacitor C20 is the second square wave processing circuit.

Pin 3 of the chip LMS324 is grounded through resistor R33; the pin 4 of the chip LMS324 is connected to the second power voltage AVDD (i.e., the output terminal TP4 of the first dc-dc controller U3); the pin 5 of the chip LMS324 is connected with the adjusting end of the fourth adjustable resistor VR 2; the first end of the fourth adjustable resistor VR2 is connected to the second power voltage AVDD through a resistor R34, and the second end of the fourth adjustable resistor VR2 is connected to the gate low voltage VGL through a resistor R35.

The pin 6 of the chip LMS324 is respectively connected with the pin 7 of the chip LMS324 and the second end of the resistor R37; the first end of the resistor R37 is respectively connected with the second end of the resistor R36 and the No. 9 pin of the chip LMS 324; the first end of the resistor R36 is connected with the No. 8 pin of the chip LMS 324; a first end of the resistor R38 is connected to pin 10 of the chip LMS324, and a second end of the resistor R38 is grounded.

The 11 th pin of the chip LMS324 is connected to the gate low voltage VGL, the 12 th pin of the chip LMS324 is grounded, and the 13 th pin and the 14 th pin of the chip LMS324 are connected. For convenience of connection, a wire is introduced, a first end of the wire is connected to pin 8 of the chip LM324, and a second end of the wire is an output end TP6 of the Source off voltage generating circuit, outputting a Source off voltage source_off.

The resistance value of the third adjustable resistor VR1 is 100KΩ; the resistance value of the fourth adjustable resistor VR2 is 100KΩ; the resistance value of the resistor R32 is 10KΩ; the resistance values of the resistor R33, the resistor R34 and the resistor R35 are all 0 omega, and are all used as standby resistors; the resistance values of the resistor R36, the resistor R37, the resistor R38 and the resistor R39 are all 51KΩ; the capacity of the ac capacitor C20 was 4.7 μf, and the forward withstand voltage was 10V. It will be appreciated that the above device options are exemplary only, and that other types are possible in practice, and embodiments of the utility model are not particularly limited thereto.

Fig. 15 is a schematic diagram of a specific structure of a source gray voltage generating circuit according to an embodiment of the present utility model, as shown in fig. 15, peripheral components of a chip LM324 include a fifth adjustable resistor VR5, a sixth adjustable resistor VR6, a resistor R48, a resistor R49, a resistor R50, a resistor R51, a resistor R52, a resistor R53, and a resistor R54; the chip LM324 includes four operational amplifiers, namely, an operational amplifier a, an operational amplifier B, an operational amplifier C, and an operational amplifier D, which are identical to the chip LM324 in the source turn-on voltage generating circuit, and are not described herein.

Specifically, pin 1 of the chip LMS324 is connected to the second end of the fifth adjustable resistor VR5, and pin 1 of the chip LMS324 is connected to pin 10 of the chip LMS324 through the resistor R55; the pin 2 of the chip LMS324 is respectively connected with the second end of the resistor R48, the first end and the adjusting end of the fifth adjustable resistor VR 5; the first end of the resistor R48 is connected to the second end of the capacitor C22, and the first end of the resistor R48 is the first voltage end of the source gray voltage generating circuit 303; the first end of the capacitor C22 is connected to pin 18 of the chip CON1 in the signal control circuit 102, and receives the initial Source square wave signal source_signal output by the signal control circuit 102, where the capacitor C22 is a third-party wave processing circuit.

Pin 3 of chip LMS324 is grounded through resistor R49; the pin 4 of the chip LMS324 is connected to the second power voltage AVDD (i.e., the output terminal TP4 of the first dc-dc controller U3); the pin 5 of the chip LMS324 is connected with the adjusting end of the sixth adjustable resistor VR 6; the first end of the sixth adjustable resistor VR6 is connected to the second power voltage AVDD through the resistor R50, and the second end of the sixth adjustable resistor VR6 is connected to the gate low voltage VGL through the resistor R51.

The pin 6 of the chip LMS324 is respectively connected with the pin 7 of the chip LMS324 and the second end of the resistor R53; the first end of the resistor R53 is respectively connected with the second end of the resistor R52 and the No. 9 pin of the chip LMS 324; the first end of the resistor R52 is connected with the No. 8 pin of the chip LMS 324; a first end of the resistor R54 is connected to pin 10 of the chip LMS324, and a second end of the resistor R54 is grounded.

The 11 th pin of the chip LMS324 is connected to the gate low voltage VGL, the 12 th pin of the chip LMS324 is grounded, and the 13 th pin and the 14 th pin of the chip LMS324 are connected. For convenience of connection, a wire is introduced, a first end of the wire is connected to pin 8 of the chip LM324, a second end of the wire is an output end TP8 of the Source gray voltage generating circuit, and the Source gray voltage source_gray is output.

Next, a specific structure of the test voltage generating circuit will be described with reference to fig. 16, 17, and 18.

Fig. 16 is a schematic diagram of a test voltage generating circuit according to an embodiment of the present utility model, and as shown in fig. 16, the test voltage generating circuit 40 includes a source test voltage generating circuit 401 and a gate test voltage generating circuit 402.

Specifically, the source test voltage generation circuit 401 is connected to the voltage control circuit 101, the signal control circuit 102, the source on voltage generation circuit 301, the source off voltage generation circuit 302, and the source gradation voltage generation circuit 303, respectively; the source test voltage generation circuit 401 is configured to generate a source test voltage by the voltage control circuit 101, the signal control circuit 102, the source on voltage generation circuit 301, the source off voltage generation circuit 302, and the source gradation voltage generation circuit 303. The gate test voltage generation circuit 402 is connected to the voltage control circuit 101, the signal control circuit 102, the gate high voltage generation circuit 203, and the gate low voltage generation circuit 204, respectively; the gate test voltage generating circuit 402 is configured to generate a gate test voltage under the action of the voltage control circuit 101, the signal control circuit 102, the gate high voltage generating circuit 203, and the gate low voltage generating circuit 204.

The source test voltage comprises a first source test voltage SO1, a second source test voltage SO2 and a third source test voltage SO3; the gate test voltage includes a first gate test voltage TGO and a second gate test voltage TGE.

Fig. 17 is a schematic diagram of a specific structure of a source test voltage generating circuit according to an embodiment of the present utility model, and as shown in fig. 17, a source test voltage generating circuit 401 includes a first photo-coupling circuit U7, a second photo-coupling circuit U8, a third photo-coupling circuit U9, and a fourth photo-coupling circuit U10. The first optocoupler circuit U7 includes an optocoupler chip AQW212, a first resistor R1, a second resistor R2, and a third resistor R3.

Specifically, a first end of the first resistor R1 is connected to the fourth sub-power supply voltage VDD4, the first end of the first resistor R1 is a voltage end of the first optocoupler circuit, and a second end of the first resistor R1 is connected to pin 1 of the optocoupler chip AQW; the pin 2 of the optocoupler chip AQW is connected with the gray Control signal control_gray and the first end of the second resistor R2 respectively, and the pin 2 of the optocoupler chip AQW212 is the first Control end of the first optocoupler circuit; the second end of the second resistor R2 is connected with a No. 3 pin of the photoelectric coupling chip AQW212,212; pin number 4 of optocoupler chip AQW is grounded. Wherein, the resistance value of the first resistor R1 and the second resistor R2 is 500 omega; the third resistor R3 has a resistance value of 0Ω and serves as a backup resistor.

The pin 5 of the photocoupling chip AQW is connected with the Source gray voltage source_gray through a third resistor R3, and the pin 5 of the photocoupling chip AQW212 is a third control end of the first photocoupling circuit; the pin 8 of the photoelectric coupling chip AQW is connected with the Source opening voltage source_on, and the pin 8 of the photoelectric coupling chip AQW212 is the second control end of the first photoelectric coupling circuit; the pin 6 and the pin 7 of the optocoupler chip AQW are connected together to form the output end of the first optocoupler circuit.

The optocoupler chip AQW is configured to output the Source on voltage source_on or the Source gray voltage source_gray under the effect of the gray Control signal control_gray. The second photo-coupling circuit U8 includes a photo-coupling chip AQW, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6.

Specifically, a first end of the fourth resistor R4 is connected to the fourth sub-power supply voltage VDD4, the first end of the fourth resistor R4 is a voltage end of the second optocoupler circuit, and a second end of the fourth resistor R4 is connected to pin 1 of the optocoupler chip AQW; the pin 2 of the optocoupler chip AQW is connected to the first source Control signal control_so1 and the first end of the fifth resistor R5, respectively, and the pin 2 of the optocoupler chip AQW is the first Control end of the second optocoupler circuit; the second end of the fifth resistor R5 is connected with a No. 3 pin of the photoelectric coupling chip AQW 212; pin number 4 of optocoupler chip AQW is grounded. Wherein, the resistance value of the fourth resistor R4 and the fifth resistor R5 is 500 omega; the sixth resistor R6 has a resistance value of 0Ω and serves as a backup resistor.

The pin 5 of the photocoupling chip AQW is connected with a Source closing voltage source_off through a sixth resistor R6, and the pin 5 of the photocoupling chip AQW212 is a third control end of the first photocoupling circuit; the No. 8 pin of the photoelectric coupling chip AQW is connected with the output end of the first photoelectric coupling circuit U7, and the No. 8 pin of the photoelectric coupling chip AQW212 is the second control end of the second photoelectric coupling circuit; the pin 6 and the pin 7 of the photo-coupling chip AQW are connected together to form the output end of the second photo-coupling circuit. The optocoupler chip AQW is configured to output a first source test voltage SO1 at an output end under the action of a first source Control signal control_so1.

The third optocoupler circuit U9 includes an optocoupler chip AQW212, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9.

Specifically, a first end of the seventh resistor R7 is connected to the fourth sub-power supply voltage VDD4, a first end of the seventh resistor R7 is a voltage end of the third optocoupler circuit U9, and a second end of the seventh resistor R7 is connected to pin 1 of the optocoupler chip AQW 212; the pin 2 of the optocoupler chip AQW is connected to the second source Control signal control_so1 and the first end of the eighth resistor R8, respectively, and the pin 2 of the optocoupler chip AQW is the first Control end of the third optocoupler circuit; the second end of the eighth resistor R8 is connected with a No. 3 pin of the photoelectric coupling chip AQW212,212; pin number 4 of optocoupler chip AQW is grounded. Wherein, the resistance value of the seventh resistor R7 and the eighth resistor R8 is 500 omega; the resistance value of the ninth resistor R9 is 0Ω as a backup resistor.

The pin 5 of the photocoupling chip AQW is connected with a Source closing voltage source_off through a ninth resistor R9, and the pin 5 of the photocoupling chip AQW212 is a third control end of a third photocoupling circuit; the No. 8 pin of the photoelectric coupling chip AQW is connected with the output end of the first photoelectric coupling circuit U7, and the No. 8 pin of the photoelectric coupling chip AQW212 is the second control end of the third photoelectric coupling circuit; the pin 6 and the pin 7 of the photo-coupling chip AQW are connected together to form an output end of the third photo-coupling circuit U9.

The optocoupler chip AQW is configured to output a second source test voltage SO2 at the output end under the action of the second source Control signal control_so2.

The fourth photo-coupling circuit U10 includes a photo-coupling chip AQW212, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12.

Specifically, a first end of the tenth resistor R10 is connected to the fourth sub power supply voltage VDD4, the first end of the tenth resistor R10 is a voltage end of the fourth photo-coupling circuit U10, and a second end of the tenth resistor R10 is connected to pin 1 of the photo-coupling chip AQW 212; the pin 2 of the optocoupler chip AQW is connected to the third source Control signal control_so3 and the first end of the eleventh resistor R11, respectively, and the pin 2 of the optocoupler chip AQW is the first Control end of the fourth optocoupler circuit; the second end of the eleventh resistor R11 is connected with the No. 3 pin of the photocoupling chip AQW 212; pin number 4 of optocoupler chip AQW is grounded. Wherein, the resistance value of the tenth resistor R10 and the eleventh resistor R11 is 500 omega; the twelfth resistor R12 has a resistance value of 0Ω and serves as a backup resistor.

The pin 5 of the photocoupling chip AQW is connected with a Source closing voltage source_off through a twelfth resistor R12, and the pin 5 of the photocoupling chip AQW212 is a third control end of a fourth photocoupling circuit; the No. 8 pin of the photoelectric coupling chip AQW is connected with the output end of the first photoelectric coupling circuit U7, and the No. 8 pin of the photoelectric coupling chip AQW212 is the second control end of the fourth photoelectric coupling circuit; the pin 6 and the pin 7 of the photocoupling chip AQW are connected together to form the output end of the fourth photocoupling circuit U10.

The optocoupler chip AQW is configured to output a third source test voltage SO3 at the output end under the action of a third source Control signal control_so3.

Since all red pixels, green pixels and blue pixels are respectively shorted together in the TFT display panel, all red pixels in the TFT display panel are connected by the first source test voltage SO1, all green pixels in the TFT display panel are controlled by the second source test voltage SO2, and all blue pixels in the TFT display panel are controlled by the third source test voltage control signal SO 3.

It will be appreciated that the above connection is not exclusive, and other connection may be possible, for example, the first source test voltage SO1 is connected to all green pixels in the TFT display panel, the second source test voltage SO2 is connected to all red pixels in the TFT display panel, and the third source test voltage SO3 is connected to all blue pixels in the TFT display panel; for example, the first source test voltage SO1 is connected to all red pixels in the TFT display panel, the second source test voltage SO2 is connected to all blue pixels in the TFT display panel, the third source test voltage SO3 is connected to all green pixels in the TFT display panel, and SO on. The embodiment of the present utility model is not particularly limited, and the following description will be given by taking the example that the first source test voltage SO1 is connected to all red pixels in the TFT display panel, the second source test voltage SO2 is connected to all green pixels in the TFT display panel, and the third source test voltage SO3 is connected to all blue pixels in the TFT display panel.

Fig. 18 is a schematic diagram of a specific structure of a gate test voltage generating circuit according to an embodiment of the present utility model, and as shown in fig. 18, the gate test voltage generating circuit 402 includes a fifth photo-coupling circuit U11 and a sixth photo-coupling circuit U12.

The fifth photo-coupling circuit U11 includes a photo-coupling chip AQW212, a nineteenth resistor R19, a twentieth resistor R20, and a twenty-first resistor R21.

Specifically, a first end of the twentieth resistor R20 is connected to the fourth sub-power supply voltage VDD4, a first end of the twentieth resistor R20 is a voltage end of the fifth optocoupler circuit, and a second end of the twentieth resistor R20 is connected to pin 1 of the optocoupler chip AQW 212; the pin 2 of the optocoupler chip AQW is connected to the first gate Control signal control_tgo and the first end of the nineteenth resistor R19, respectively, and the pin 2 of the optocoupler chip AQW212 is the first Control end of the fifth optocoupler circuit; the second end of the nineteenth resistor R19 is connected with the No. 3 pin of the photocoupling chip AQW212,212; pin number 4 of optocoupler chip AQW is grounded. Wherein, the resistance value of the twentieth resistor R20 and the nineteenth resistor R19 is 500 omega; the twenty-first resistor R21 has a resistance value of 0Ω and serves as a backup resistor.

The No. 5 pin of the photoelectric coupling chip AQW is connected with the grid low voltage VGL, and the No. 5 pin of the photoelectric coupling chip AQW is the third control end of the fifth photoelectric coupling circuit; the No. 8 pin of the photoelectric coupling chip AQW is connected with the gate high voltage VGH through a twenty-first resistor R21, and the No. 8 pin of the photoelectric coupling chip AQW212 is the second control end of the fifth photoelectric coupling circuit; the pin 6 and the pin 7 of the optocoupler chip AQW are connected together to form an output end of the fifth optocoupler circuit together, and output the first gate test voltage TGO.

The optocoupler chip AQW is configured to output a first gate test voltage TGO from the output terminal under the action of a first gate Control signal control_tgo.

The sixth photo-coupling circuit U12 includes a photo-coupling chip AQW212, a seventeenth resistor R17, a sixteenth resistor R16, and an eighteenth resistor R18.

Specifically, a first end of the seventeenth resistor R17 is connected to the fourth sub-power supply voltage VDD4, a first end of the seventeenth resistor R17 is a voltage end of the sixth optocoupler circuit U12, and a second end of the seventeenth resistor R17 is connected to pin 1 of the optocoupler chip AQW 212; the pin 2 of the optocoupler chip AQW is connected to the second gate Control signal control_tge and the first end of the sixteenth resistor R16, respectively, and the pin 2 of the optocoupler chip AQW is the first Control end of the sixth optocoupler circuit U12; the second end of the sixteenth resistor R16 is connected with the No. 3 pin of the photoelectric coupling chip AQW212,212; pin number 4 of optocoupler chip AQW is grounded. Wherein, the resistance value of the seventeenth resistor R17 and the sixteenth resistor R16 is 500 omega; the eighteenth resistor R18 has a resistance value of 0Ω and serves as a backup resistor.

The No. 5 pin of the photoelectric coupling chip AQW is connected with the grid low voltage VGL, and the No. 5 pin of the photoelectric coupling chip AQW is the third control end of the sixth photoelectric coupling circuit U12; the No. 8 pin of the photoelectric coupling chip AQW is connected with the gate high voltage VGH through an eighteenth resistor R18, and the No. 8 pin of the photoelectric coupling chip AQW212 is the second control end of the sixth photoelectric coupling circuit U12; the pin 6 and the pin 7 of the optocoupler chip AQW are connected together to form an output end of the sixth optocoupler circuit together, and output the second gate test voltage TGE.

The optocoupler chip AQW is configured to output a second gate test voltage TGE at the output end under the action of the second gate Control signal control_tge.

Since the gates of all the odd-numbered lines of the driving liquid crystal are shorted together and the gates of all the even-numbered lines of the driving liquid crystal are shorted together in the TFT display panel, the TFT display panel has a total of two lines, a first line (odd-numbered line) and a second line (even-numbered line); controlling the on or off of the driving liquid crystals of all odd rows in the TFT display panel with the first gate test voltage TGO; the second gate test voltage TGE is used to control the on or off of the driving liquid crystals of all even rows in the TFT display panel.

When the levels of the first gate test voltage TGO and the second gate test voltage TGE are the gate high voltage VGH, the driving liquid crystal is turned on, and the source base voltage signal may reach one pole of the liquid crystal through the driving liquid crystal tube, forming a voltage difference with the common voltage Vcom of the TFT display panel. When the levels of the first gate test voltage TGO and the second gate test voltage TGE are the gate low voltage VGL, the driving liquid crystal is turned off, and the source base voltage signal cannot reach the pole of the liquid crystal. The first gate test voltage TGO and the second gate test voltage TGE form a scan sequence, and the first gate test voltage TGO and the second gate test voltage TGE are fixed.

After the first gate test voltage TGO and the second gate test voltage TGE are scanned, the polarity of the driving electrode is inverted, for example, after the first gate test voltage TGO and the second gate test voltage TGE are scanned, the source base voltage signal is inverted, and the liquid crystal is driven to perform frame inversion, so that the frame inversion of the source base voltage signal is realized.

Controlling the on or off of the driving liquid crystals of all odd lines in the TFT display panel with the first gate test voltage TGO includes: after the second basic voltage reaches the odd-numbered lines, the first gate test voltage TGO is inverted to the gate start voltage VGH after the first time Deltat ₁ is delayed, and the driving liquid crystals of all the odd-numbered lines are turned on; after the second base voltage reaches the even-numbered rows, the first gate test voltage TGO is immediately inverted to the gate low voltage VGL, and the driving liquid crystals of all the odd-numbered rows are turned off. With this cycle, the on or off of the driving liquid crystal of all odd rows in the TFT display panel is controlled.

Controlling the on or off of the driving liquid crystals of all even rows in the TFT display panel with the second gate test voltage TGE includes: after the second basic voltage reaches the odd-numbered rows, the second gate test voltage TGE is immediately inverted to the gate low voltage VGL, and the driving liquid crystals of all even-numbered rows are turned off; after the second basic voltage reaches the even-numbered rows, the second gate test voltage TGE is delayed by a second time Δt ₂ and then inverted to the gate-on voltage VGH to turn on all the driving liquid crystals of the even-numbered rows. With this cycle, the on or off of the driving liquid crystal of all even rows in the TFT display panel is controlled.

The implementation of different types of control signals using a software approach is described below in connection with fig. 19.

Fig. 19 is a schematic diagram of the result of generating different types of control signals according to an embodiment of the present utility model, and as shown in fig. 19, an example of generating the Source gray voltage source_gray, the first gate test voltage TGO, and the second human gate test voltage TGE is illustrated.

As shown in fig. 19, the basic square wave generated by the timer (i.e., the crystal oscillator Y1 in the signal control circuit 102) is frequency-adjustable, and can be inverted in the row driving liquid crystal, that is, the basic square wave is inverted from the odd-numbered row to the even-numbered row. The frame frequency is a division by 2 of the basic square wave, i.e. if the frequency of the basic square wave is F, the frame frequency of the liquid crystal display is f=f/2. If the frame frequency needs to be adjusted, the F of the basic square wave is adjusted.

The Source gray voltage source_gray signal is divided by 2 of the basic square wave, that is, the basic square wave is inverted 2 times, and then the Source gray voltage source_gray signal is inverted once. The Source on voltage source_on signal and the Source off voltage source_off signal are generated at the same frequency and phase, but are different in magnitude.

The first gate test voltage TGO is also a frequency division of 2 of the basic square wave, and after the second basic voltage reaches the odd-numbered rows, the first gate test voltage TGO is inverted to the gate-on voltage VGH after a delay of a first time Δt ₁; after the second base voltage reaches the even-numbered rows, the first gate test voltage TGO is immediately inverted to the gate low voltage VGL, and is repeated.

The second gate test voltage TGE is also a frequency division of 2 of the basic square wave, and immediately after the second basic voltage reaches the odd-numbered rows, the second gate test voltage TGE is inverted to the gate low voltage VGL; after the second base voltage reaches the even-numbered rows, the second gate test voltage TGE is delayed by a second time Δt ₂ and then inverted to the gate-on voltage VGH.

According to the test circuit provided by the embodiment of the utility model, each test interface in the test interface module J1 in the test circuit can be connected with the corresponding interface in the TFT display panel, the function detection can be carried out on the TFT display panel which is not bound with COG, and the bad TFT display panel can be screened out, so that the waste of other materials caused by putting defective products into production is reduced.

The schematic structural diagram of the test interface module J1 in the test circuit may continue to refer to fig. 4, where the test interface No. 1 in the test interface module J1 is used for outputting a third power supply voltage, which is the output end TP5 in fig. 6; the test interface No. 2 in the test interface module J1 is configured to output a first gate test voltage TGO, which is an output end of the fifth photoelectric coupling circuit U11 in fig. 18; the test interface No. 3 in the test interface module J1 is configured to output the second gate voltage control signal TGE, which is an output end of the sixth photo-coupling circuit U12 in fig. 18.

The test interface No. 4 in the test interface module J1 is configured to output a first source test voltage SO1, which is an output end of the second photoelectric coupling circuit U8 in fig. 17; the test interface No. 5 in the test interface module J1 is configured to output a second source test voltage SO2, which is an output end of the third photoelectric coupling circuit U9 in fig. 17; the test interface No. 6 in the test interface module J1 is configured to output the third source test voltage SO3, which is an output end of the fourth photo-coupling circuit U10 in fig. 17.

The No. 7 test interface in the test interface module J1 is used for connecting a common voltage end of the TFT display panel and outputting a grounded voltage (namely 0V) to the TFT display panel; the No. 8 test interface in the test interface module J1 is connected with a first power supply and is used for receiving the voltage VDD provided by the first power supply; the test interface No. 9 in the test interface module J1 is grounded.

When the test circuit provided by the embodiment of the utility model is used for testing the basic function of the TFT display panel, the test can be carried out according to the table 1:

TABLE 1

If all of the tests were performed successfully according to Table 1, it was demonstrated that the TFT display panel was excellent in production and could be put into production. Taking a red frame as an example, the first Source test voltage SO1 is a Source on voltage source_on, the second Source test voltage SO2 and the third Source test voltage SO3 are Source off voltages source_off, the first gate test voltage TGO and the second gate test voltage TGE are both kept in a scanning state, and the common voltage VCOM is grounded at 0V.

As a test result of the red frame, reference may be made to fig. 20, and fig. 20 is a schematic diagram of a test result of the red display frame according to an embodiment of the present utility model. As shown in fig. 20, the first test voltage SW is continuously high, and the voltage value of the first test voltage SW is greater than or equal to the gate-on voltage VGH; the common voltage VCOM is grounded for 0V.

The first Source test voltage SO1 is a Source turn-on voltage source_on, taking offset as a central value, wherein the high level of the Source turn-on voltage source_on is source_on high, and the low level of the Source turn-on voltage source_on is source_on low; the second Source test voltage SO2 and the third Source test voltage SO3 are both Source off voltages source_off, the offset is taken as a central value, the high level of the Source off voltage source_off is source_off high, and the low level of the Source off voltage source_off is source_off low.

The first gate test voltage TGO and the second gate test voltage TGE both maintain a scan state. After the second basic signal (i.e., the Source on voltage source_on and the Source off voltage source_off) reaches the odd rows, the first gate test voltage TGO is inverted to the gate on voltage VGH after a delay of a first time Δt ₁; after the second base voltage reaches the even-numbered rows, the first gate test voltage TGO is immediately inverted to the gate low voltage VGL; after the second base voltage reaches the odd rows, the second gate test voltage TGE is immediately inverted to the gate low voltage VGL; after the second base voltage reaches the even-numbered rows, the second gate test voltage TGE is delayed by a second time Δt ₂ and then inverted to the gate-on voltage VGH.

In the description of the present utility model, it should be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.

Furthermore, in the present utility model, unless explicitly specified and limited otherwise, the terms "connected," "coupled," and the like are to be construed broadly and may be, for example, mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, unless otherwise specifically defined, the meaning of the terms in this disclosure is to be understood by those of ordinary skill in the art.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.

Claims

1. A test circuit, comprising: the device comprises a control circuit, a grid base voltage generating circuit, a source base voltage generating circuit and a test voltage generating circuit;

2. The test circuit of claim 1, wherein the control circuit comprises a voltage control circuit and a signal control circuit connected;

The voltage control circuit is respectively connected with a first power supply, the grid base voltage generation circuit and the test voltage generation circuit, and is used for outputting a plurality of voltage signals to the signal control circuit, the grid base voltage generation circuit and the test voltage generation circuit;

the signal control circuit is respectively connected with the grid base voltage generation circuit, the source base voltage generation circuit and the test voltage generation circuit, and is used for outputting a plurality of control signals to the grid base voltage generation circuit, the source base voltage generation circuit and the test voltage generation circuit under the action of the voltage control circuit.

3. The test circuit of claim 2, wherein the gate base voltage generation circuit comprises a second supply voltage generation circuit and a first test voltage generation circuit connected;

the second power supply voltage generation circuit is respectively connected with the voltage control circuit, the signal control circuit and the source base voltage generation circuit; the second power supply voltage generating circuit is used for generating a second power supply voltage under the action of the voltage control circuit and the signal control circuit and outputting the second power supply voltage to the source base voltage generating circuit and the first test voltage generating circuit;

The first test voltage generating circuit is used for generating the first test voltage under the action of the second power supply voltage.

4. The test circuit of claim 3, wherein the gate base voltage generation circuit further comprises a gate high voltage generation circuit and a gate low voltage generation circuit;

The grid high-voltage generating circuit is respectively connected with the voltage control circuit, the signal control circuit and the test voltage generating circuit; the grid high voltage generation circuit is used for generating grid high voltage under the action of the voltage control circuit and the signal control circuit and outputting the grid high voltage to the test voltage generation circuit;

the grid low-voltage generation circuit is respectively connected with the voltage control circuit, the signal control circuit, the source base voltage generation circuit and the test voltage generation circuit; the grid low voltage generation circuit is used for generating grid low voltage under the action of the voltage control circuit and the signal control circuit and outputting the grid low voltage to the source base voltage generation circuit and the test voltage generation circuit.

5. The test circuit of claim 4, wherein the source base voltage generation circuit comprises a source on voltage generation circuit, a source off voltage generation circuit, and a source gray scale voltage generation circuit;

the source electrode opening voltage generating circuit is respectively connected with the grid electrode low voltage generating circuit, the second power supply voltage generating circuit, the signal control circuit and the test voltage generating circuit, and is used for generating a source electrode opening voltage under the action of the grid electrode low voltage generating circuit, the second power supply voltage generating circuit and the signal control circuit and outputting the source electrode opening voltage to the test voltage generating circuit;

The source electrode closing voltage generating circuit is respectively connected with the grid electrode low voltage generating circuit, the second power supply voltage generating circuit, the signal control circuit and the test voltage generating circuit, and is used for generating a source electrode closing voltage under the action of the grid electrode low voltage generating circuit, the second power supply voltage generating circuit and the signal control circuit and outputting the source electrode closing voltage to the test voltage generating circuit;

The source gray voltage generating circuit is respectively connected with the grid low voltage generating circuit, the second power voltage generating circuit, the signal control circuit and the test voltage generating circuit, and is used for generating source gray voltage under the action of the grid low voltage generating circuit, the second power voltage generating circuit and the signal control circuit and outputting the source gray voltage to the test voltage generating circuit.

6. The test circuit of claim 5, wherein the test voltage generation circuit comprises a source test voltage generation circuit and a gate test voltage generation circuit;

The source test voltage generation circuit is respectively connected with the voltage control circuit, the signal control circuit, the source opening voltage generation circuit, the source closing voltage generation circuit and the source gray voltage generation circuit; the source test voltage generating circuit is used for generating a source test voltage under the action of the voltage control circuit, the signal control circuit, the source opening voltage generating circuit, the source closing voltage generating circuit and the source gray scale voltage generating circuit;

The grid test voltage generation circuit is respectively connected with the voltage control circuit, the signal control circuit, the grid high voltage generation circuit and the grid low voltage generation circuit; the grid test voltage generating circuit is used for generating a grid test voltage under the action of the voltage control circuit, the signal control circuit, the grid high voltage generating circuit and the grid low voltage generating circuit; the second test voltage includes the source test voltage and the gate test voltage.

7. The test circuit of claim 4 or 6, wherein the plurality of voltage signals comprises: a first sub power supply voltage, a second sub power supply voltage, and a third sub power supply voltage;

the plurality of control signals includes: a first pulse width modulation signal, a second pulse width modulation signal, and a third pulse width modulation signal;

The gate high voltage generating circuit for generating a gate high voltage under the action of the voltage control circuit and the signal control circuit includes:

the voltage control circuit outputs the first sub-power supply voltage to the grid high-voltage generation circuit, the signal control circuit outputs the first pulse width modulation signal to the grid high-voltage generation circuit, and the grid high-voltage generation circuit is used for generating the grid high voltage under the action of the first sub-power supply voltage and the first pulse width modulation signal;

The gate low voltage generation circuit for generating a gate low voltage under the action of the voltage control circuit and the signal control circuit includes:

The voltage control circuit outputs the second sub-power supply voltage to the grid low-voltage generation circuit, the signal control circuit outputs the second pulse width modulation signal to the grid low-voltage generation circuit, and the grid low-voltage generation circuit is used for generating the grid low voltage under the action of the second sub-power supply voltage and the second pulse width modulation signal;

The second power supply voltage generating circuit is configured to generate a second power supply voltage under the action of the voltage control circuit and the signal control circuit, and includes:

The voltage control circuit outputs the third sub-power supply voltage to the second power supply voltage generation circuit, the signal control circuit outputs the third pulse width modulation signal to the second power supply voltage generation circuit, and the second power supply voltage generation circuit is used for generating the second power supply voltage under the action of the third sub-power supply voltage and the third pulse width modulation signal.

8. The test circuit of claim 7, wherein the plurality of voltage signals further comprises: a fourth sub-power supply voltage;

The signal control circuit is configured to output a plurality of control signals to the gate base voltage generation circuit, the source base voltage generation circuit, and the test voltage generation circuit under the action of the voltage control circuit, and includes:

The voltage control circuit outputs the fourth sub power supply voltage to the signal control circuit, and the signal control circuit is used for outputting a plurality of control signals to the grid base voltage generation circuit, the source base voltage generation circuit and the test voltage generation circuit under the action of the fourth sub power supply voltage.

9. The test circuit of claim 8, wherein the plurality of control signals further comprises: an initial source square wave signal;

The signal control circuit is used for outputting the initial source square wave signal to the source basic voltage generation circuit under the action of the fourth sub-power supply voltage.

10. The test circuit of claim 8 or 9, wherein a plurality of the control signals further comprise: a first source control signal, a second source control signal, a third source control signal, a first gate control signal, a second gate control signal, and a gray control signal;

When the test voltage generating circuit includes a source test voltage generating circuit and a gate test voltage generating circuit, the signal control circuit is configured to output the first source control signal, the second source control signal, the third source control signal, and the gradation control signal to the source test voltage generating circuit, and output the first gate control signal and the second gate control signal to the gate test voltage generating circuit under the action of the fourth sub power supply voltage.