CN220796754U

CN220796754U - SGT MOSFET device with low switching loss

Info

Publication number: CN220796754U
Application number: CN202322436167.XU
Authority: CN
Inventors: 覃源; 高盼盼
Original assignee: Hefei Sipu Semiconductor Technology Co ltd
Current assignee: Hefei Sipu Semiconductor Technology Co ltd
Priority date: 2023-09-07
Filing date: 2023-09-07
Publication date: 2024-04-16
Anticipated expiration: 2033-09-07

Abstract

The utility model belongs to the technical field of semiconductors, and particularly relates to an SGT MOSFET device with low switching loss, which comprises an epitaxial layer; the body region is positioned above the epitaxial layer; a source region located above the body region; and the groove is positioned on the epitaxial layer and extends to pass through the body region and the source region, the middle part in the groove is provided with grid polysilicon, the upper part in the groove is filled with a dielectric isolation part, and the dielectric isolation part is positioned on the grid polysilicon. According to the utility model, the dielectric isolation part is filled above the grid polysilicon, and the rotary injection source region is added below the source region, so that the thickness d of the dielectric isolation layer is increased, the contact area S is reduced, the N+ is injected in a mode of forming a certain angle, the volume of the N+ injection region is controlled to the minimum extent, the capacitance is reduced, and finally the switching loss of the device is reduced.

Description

SGT MOSFET device with low switching loss

Technical Field

The utility model belongs to the technical field of semiconductors, and particularly relates to an SGT MOSFET device with low switching loss.

Background

The SGT (shielded gate Trench type) MOSFET device is a novel power semiconductor device, compared with the traditional Trench MOSFET device, the SGT MOSFET device has deeper Trench, through the shielded gate structure, the overlapping area of capacitance between a gate and a drain is greatly reduced, and the gate-drain capacitance is reduced, so that the gate charge of the SGT MOSFET device is greatly reduced, the switching speed of the device is finally greatly improved, and the switching loss is reduced.

Fig. 1 shows an SGT MOSFET device, which includes an epitaxial layer (Epi) 101, a Trench (Trench) 102 in the epitaxial layer 101, a Source polysilicon (Source Poly) 103, a Gate polysilicon (Gate Poly) 104, an isolation oxide layer (IPO) 105 between the Source polysilicon 103 and the Gate polysilicon 104, a Gate oxide dielectric layer (GOX) 106, a P-type doped region (P-body) 107, an N-type doped region (n+) 108, a connection hole (CT) 109, a dielectric Isolation Layer (ILD) 110, a Metal layer (Metal) 111, and the like.

Due to the design of the gate polysilicon 104 and the N-type doped region 108, the thickness of the dielectric isolation layer 110 is insufficient and the injection volume of the N-type doped region 108 is large, which results in an excessively high input capacitance and a large on-state resistance (Rdson), thereby greatly affecting the switching performance of the device.

Disclosure of Invention

Aiming at the technical problems that the prior SGT MOSFET device still has larger switching loss and affects the switching performance of the device, the utility model aims to provide the SGT MOSFET device with low switching loss.

The low switching loss SGT MOSFET device of the present utility model includes:

an epitaxial layer;

the body region is positioned above the epitaxial layer;

a source region over the body region;

the groove is positioned on the epitaxial layer and extends through the body region and the source region, grid polysilicon is arranged in the middle of the groove, a dielectric isolation part is filled in the upper part of the groove, and the dielectric isolation part is positioned on the grid polysilicon.

Preferably, the source region has a rotation implantation source region toward the body region near the sidewall of the trench, and the rotation implantation source region is sandwiched between the body region and the sidewall of the trench.

Preferably, the groove further has:

the source polycrystalline silicon is positioned at the lower part in the groove;

and the isolating oxide layer is positioned between the grid polycrystalline silicon and the source polycrystalline silicon, and the grid polycrystalline silicon and the source polycrystalline silicon are separated by the isolating oxide layer.

Preferably, the trench further comprises:

the lower part of the gate oxide dielectric layer is positioned between the gate polysilicon and the groove, and the upper part of the gate oxide dielectric layer is positioned between the dielectric isolation part and the groove; and the grid polysilicon and the groove are separated by the grid oxide dielectric layer, and the bottom of the grid oxide dielectric layer is connected with the isolation oxide layer.

Preferably, the trench further comprises:

the source oxide dielectric layer is positioned between the source polycrystalline silicon and the groove, the source polycrystalline silicon and the groove are separated by the source oxide dielectric layer, and the top of the source oxide dielectric layer is connected with the isolation oxide layer.

Preferably, the ratio of the height of the dielectric spacer to the depth of the trench is 0.5 to 1.3:10, preferably 0.7 to 1.1:10, more preferably 0.9:10.

preferably, the ratio of the height of the spin-injection source region to the height of the source region base is 7-10: 10, preferably 8.5 to 10:10, more preferably 10:10.

preferably, the ratio of the width of the spin-injection source region to the height of the source region is 3-5: 10, preferably 3.5 to 4.5:10, more preferably 4:10.

preferably, the body region and the source region are located at an outer upper portion of the trench.

Preferably, the top of the source region is flush with the top of the trench.

Preferably, the isolation oxide layer is located in the middle of the trench.

Preferably, the low switching loss SGT MOSFET device further comprises:

a dielectric isolation layer located above the source region and covering the dielectric isolation portion;

and the metal layer is positioned above the medium isolation layer.

Preferably, the low switching loss SGT MOSFET device further comprises:

the upper end of the connecting hole is connected with the metal layer, and the lower end of the connecting hole sequentially penetrates through the dielectric isolation layer and the source region and extends into the body region;

the trench sequentially penetrates through the source region and the body region from top to bottom and extends into the epitaxial layer.

The utility model has the positive progress effects that:

1) Compared with the existing device, the gate polysilicon is etched back by a certain amount, the isolating medium is filled at the etching back position, namely, an isolating medium part is added between the gate polysilicon and the isolating medium layer, namely, the thickness between capacitors is equivalently increased, the Cgs1 in the Y direction is reduced, the contact area between the gate polysilicon and the silicon is reduced, namely, the capacitance area is equivalently reduced, the Cgs2 between the gate polysilicon in the X direction and the contact hole is reduced, so that the input capacitance is reduced, and the switching loss is optimized.

2) According to the utility model, a rotary injection process with an inclination angle (30 degrees) is used for forming the source region, so that N+ can be injected in a certain angle mode, the rotary injection source region is synchronously formed on the side wall of the groove while the source region is formed, and compared with the prior art, the process cost is not increased additionally; the angled implant reduces the input capacitance while minimizing the control of the N + implant region volume compared to the vertical surface implant, and suppresses the on-state resistance Rdson increase due to the N + implant region increase.

Drawings

FIG. 1 is a schematic cross-sectional view of a prior art SGT MOSFET device;

FIG. 2 is a schematic cross-sectional view of the present utility model;

fig. 3 is a process flow diagram of the present utility model.

Detailed Description

Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which is to be read in light of the specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model.

It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.

In the description of the present utility model, it should be noted that, for the azimuth terms, such as terms "outside," "middle," "inside," "outside," and the like, the azimuth and positional relationships are indicated based on the azimuth or positional relationships shown in the drawings, only for convenience in describing the present utility model and simplifying the description, but not to indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and should not be construed as limiting the specific protection scope of the present utility model.

Referring to fig. 2, the present utility model provides a low switching loss SGT MOSFET device comprising:

epitaxial layer (Epi) 201.

Body region 202, body region 202 is located on epitaxial layer 201.

Source region 203, source region 203 being located on body region 202.

Trench 204, trench 204 is located on epitaxial layer 201.

In some embodiments, referring to fig. 2, body region 202 and source region 203 are located at an outer upper portion of trench 204, with the top of source region 203 being flush with the top of trench 204.

Trenches 204 extend through source region 203 and body region 202 in sequence from top to bottom and into epitaxial layer 201.

The low switching loss SGT MOSFET device also includes Gate polysilicon (Gate Poly) 205, the Gate polysilicon 205 being located in the middle of the trench 204.

The low switching loss SGT MOSFET device also includes dielectric Isolation (ILD) 2081, the dielectric isolation 2081 being located in an upper portion of trench 204, above gate polysilicon 205.

The low switching loss SGT MOSFET device further includes a dielectric Isolation Layer (ILD) 208, the dielectric isolation layer 208 being located over the source region 203 and being integrally formed with the dielectric isolation 2081 overlying the dielectric isolation 2081.

In general, c=εs/4pi kd, the utility model fills isolation medium at the back etching position by making a certain amount of back etching, that is, the dielectric isolation portion 2081 is added above the original gate polysilicon 205, that is, the thickness d is increased, so as to reduce the capacitance, and simultaneously, the contact area S is also reduced, so that the capacitance is reduced, and finally, the switching loss of the device is reduced.

The low switching loss SGT MOSFET device further includes a spin-implant source region 2031, the spin-implant source region 2031 being located adjacent to the sidewalls of the trench 204 toward the body region 202, the spin-implant source region 2031 being sandwiched between the body region 202 and the sidewalls of the trench 204.

In some embodiments, referring to fig. 2, source region 203 and spin-implant source region 2031 are integrally formed on body region 202.

According to the utility model, by adding the rotary injection source region 2031, N+ can be injected in a mode with a certain angle, compared with the vertical surface injection, the volume of the N+ injection region can be controlled to the minimum extent, the on-state resistance increase caused by the increase of the N+ injection region is inhibited, and the switching loss is further effectively reduced.

In some embodiments, referring to fig. 2, line AA represents the up-down thickness of dielectric spacer 2081, line BB represents the depth of center of trench 204, then AA: bb=0.5: 10-1.3:10, preferably AA: bb=0.7: 10-1.1:10, more preferably AA: bb=0.9: 10.

in some embodiments, referring to fig. 2, line CC represents the height of the spin-implant source region 2031, line DD represents the height of the source region 203 itself, and CC: dd=7: 10-10:10, preferably CC: dd=8.5: 10-10:10, more preferably CC: dd=10: 10.

in some embodiments, referring to fig. 2, line segment EE represents the width of the spin-implant source region 2031, line segment DD represents the height of the source region 203 itself, then EE: dd=3: 10-5:10, preferably EE: dd=3.5: 10-4.5:10, more preferably EE: dd=4: 10.

in some embodiments, referring to fig. 2, the low switching loss SGT MOSFET device of the present utility model further comprises:

source Poly 206, source Poly 206 being located in a lower portion of trench 204;

an isolation oxide layer (IPO) 207, the isolation oxide layer 207 being located between the gate polysilicon 205 and the source polysilicon 206, the gate polysilicon 205 and the source polysilicon 206 being separated by the isolation oxide layer 207.

In some embodiments, referring to fig. 2, an isolation oxide layer (IPO) 207 is located in the middle of trench 204.

The low switching loss SGT MOSFET device further includes a gate oxide dielectric layer (GOX) 209, a lower portion of the gate oxide dielectric layer (GOX) 209 being located between the gate polysilicon 205 and the trench 204, an upper portion of the gate oxide dielectric layer 209 being located between the dielectric spacer 2081 and the trench 204; the gate polysilicon 205 is separated from the trench 204 by a gate oxide dielectric layer 209, the bottom of the gate oxide dielectric layer 209 being connected to the isolation oxide layer 207.

The low switching loss SGT MOSFET device further includes a source Oxide dielectric layer (Oxide) 210, the source Oxide dielectric layer (Oxide) 210 being located between the source polysilicon 206 and the trench 204, the source polysilicon 206 being separated from the trench 204 by the source Oxide dielectric layer 210, the top of the source Oxide dielectric layer 210 being connected to the isolation Oxide layer 207.

The low switching loss SGT MOSFET device further includes a Metal layer (Metal) 211, the Metal layer (Metal) 211 being located over the dielectric isolation layer 208, the Metal layer 211 being separated from the source region 203 by the dielectric isolation layer 208.

The low switching loss SGT MOSFET device further includes a connection hole (CT) 212, the upper end of the connection hole (CT) 212 being connected to the metal layer 211, the lower end of the connection hole 212 penetrating the dielectric isolation layer 208 and the source region 203 in sequence and extending into the body region 202.

In some embodiments, body region 202 is a P-doped region (P-body) of P-type doping type and source region 203 is an N-doped region (n+), of N-type doping type.

In some embodiments, referring to FIG. 3, the fabrication of the low switching loss SGT MOSFET device of the present utility model may specifically employ the steps of:

step (1), etching the hard mask layer, etching the groove 204, and growing a source oxide dielectric layer 210 in the groove 204;

step (2), filling source polysilicon 206 in source oxide dielectric layer 210 and etching back;

step (3), removing the sidewall source oxide dielectric layer 210 above the source polysilicon 206, removing the hard mask layer, growing the isolation oxide layer 207 on the source polysilicon 206 and etching back;

step (4), a gate oxide dielectric layer 209 is grown on the sidewall above the source polysilicon 206;

step (5), growing gate polysilicon 205 on isolation oxide layer 207 and etching back a certain amount;

step (6), n+ band angle rotation implantation of the source region 203, and implantation of the body region 202, i.e., P-body;

step (7), depositing an isolation medium so that a medium isolation portion 2081 and a medium isolation layer 208 are formed on the gate polysilicon 205, and at this time, the medium isolation portion 2081 and the medium isolation layer 208 are integrally formed;

step (8), etching and filling the connecting holes 212;

in step (9), a metal layer 211 is grown on the dielectric isolation layer 208.

The present utility model has been described in detail with reference to the embodiments of the drawings, and those skilled in the art can make various modifications to the utility model based on the above description. Accordingly, certain details of the embodiments are not to be interpreted as limiting the utility model, which is defined by the appended claims.

Claims

1. A low switching loss SGT MOSFET device, said low switching loss SGT MOSFET device comprising:

an epitaxial layer;

the body region is positioned above the epitaxial layer;

a source region over the body region;

2. The low switching loss SGT MOSFET device of claim 1, wherein said source region has a spin-implant source region adjacent to a sidewall of said trench toward said body region, said spin-implant source region being sandwiched between said body region and a sidewall of said trench.

3. The low switching loss SGT MOSFET device of claim 2, wherein said trench further has:

4. The low switching loss SGT MOSFET device of claim 3, wherein said trench further comprises:

5. The low switching loss SGT MOSFET device of claim 3, wherein said trench further comprises:

6. The low switching loss SGT MOSFET device of claim 2, wherein the ratio of the height of said dielectric spacer to the depth of said trench is 0.5 to 1.3:10.

7. the low switching loss SGT MOSFET device of claim 2, wherein the ratio of the height of said dielectric spacer to the depth of said trench is from 0.7 to 1.1:10.

8. the low switching loss SGT MOSFET device of claim 2, wherein a ratio of a height of said dielectric spacer to a depth of said trench is 0.9:10.

9. the low switching loss SGT MOSFET device of claim 2, wherein the ratio of the height of said spin-implanted source region to the height of said source region base is from 7 to 10:10.

10. the low switching loss SGT MOSFET device of claim 2, wherein the ratio of the height of said spin-implanted source region to the height of said source region base is from 8.5 to 10:10.

11. the low switching loss SGT MOSFET device of claim 2, wherein the ratio of the height of said spin-implanted source region to the height of said source region base is 10:10.

12. the low switching loss SGT MOSFET device of claim 2, wherein the ratio of the width of said spin-implanted source region to the height of said source region base is from 3 to 5:10.

13. the low switching loss SGT MOSFET device of claim 2, wherein a ratio of a width of said spin-implanted source region to a height of said source region base is 3.5 to 4.5:10.

14. the low switching loss SGT MOSFET device of claim 2, wherein a ratio of a width of said spin-implanted source region to a height of said source region base is 4:10.

15. the low switching loss SGT MOSFET device of claim 1, wherein said body region and said source region are located at an upper outer portion of said trench.

16. The low switching loss SGT MOSFET device of claim 1, wherein a top of said source region is flush with a top of said trench.

17. The low switching loss SGT MOSFET device of claim 3, wherein said isolation oxide layer is located in the middle of said trench.

18. The low switching loss SGT MOSFET device of claim 1, wherein said low switching loss SGT MOSFET device further comprises:

and the metal layer is positioned above the medium isolation layer.

19. The low switching loss SGT MOSFET device of claim 18, wherein said low switching loss SGT MOSFET device further comprises: