CN109461769B - Trench gate IGBT device structure and manufacturing method thereof - Google Patents
Trench gate IGBT device structure and manufacturing method thereof Download PDFInfo
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- CN109461769B CN109461769B CN201811502301.9A CN201811502301A CN109461769B CN 109461769 B CN109461769 B CN 109461769B CN 201811502301 A CN201811502301 A CN 201811502301A CN 109461769 B CN109461769 B CN 109461769B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 210000000746 body region Anatomy 0.000 claims abstract description 33
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000001301 oxygen Substances 0.000 claims abstract description 29
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 25
- 229920005591 polysilicon Polymers 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 34
- 238000000151 deposition Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 9
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 5
- 230000001681 protective effect Effects 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013467 fragmentation Methods 0.000 description 1
- 238000006062 fragmentation reaction Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
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Abstract
The invention belongs to the technical field of manufacturing of semiconductor devices, and relates to a trench gate IGBT device structure, wherein an IGBT device unit comprises a first conductive type substrate, a first conductive type epitaxial layer positioned on the first conductive type substrate and a first conductive type epitaxial layer positioned below the first conductive type substrate, a plurality of gate trenches are arranged in the first conductive type epitaxial layer, the depth of each gate trench is consistent with the junction depth of a second conductive type body region adjacent to the left side and the right side, gate polysilicon and a gate oxide layer positioned outside the gate polysilicon and closely attached to the side wall of the gate trench are filled in each gate trench, an inverted trapezoid thick oxygen trench is arranged below each gate trench, and the inverted trapezoid thick oxygen trench extends into the first conductive type epitaxial layer; according to the invention, the inverted trapezoid thick oxygen groove is arranged at the bottom of the groove, so that the electron injection quantity of the emission region can be enhanced, the conduction voltage drop Vceon is reduced, the conduction loss of the device in operation is improved, the gate-drain capacitance Cgd is reduced, the feedback capacitance Crss is reduced, and the switching loss of the device is reduced.
Description
Technical Field
The invention relates to an IGBT device structure and a manufacturing method thereof, in particular to a trench gate IGBT device structure and a manufacturing method thereof, and belongs to the technical field of manufacturing of semiconductor devices.
Background
Compared with a MOSFET device, the conduction modulation effect of the IGBT drift region can greatly reduce the forward conduction voltage drop Vceon, the static power loss is smaller, and the higher the voltage is, the more remarkable the voltage is. Thus, IGBTs occupy a large market share in medium-high voltage applications. The IGBT mainly comprises three structures of a punch-through PT-IGBT, a non-punch-through NPT-IGBT and a field cut-off FS-IGBT, wherein the main differences among the three structures are different substrate PN junction structures (P+ and Nbuffer) and different drift region (N-EPI) thicknesses. Compared with PT-IGBT and NPT-IGBT, the FS-IGBT has the thinnest thickness of the drift region, the forward conduction voltage drop of the FS-IGBT is obviously reduced, the structure is widely applied to IGBT products, and the structure is shown in a schematic diagram of a cross-section structure of an existing FS-IGBT device unit. However, with the continuous increase of the size of the semiconductor wafer, the continuous improvement of the performance of the IGBT (particularly, the low-voltage IGBT) is limited by the cost, the complex process, the fragmentation rate, etc., and how to further reduce the turn-on voltage drop of the FS-IGBT device without affecting other parameters of the device is an urgent problem to be solved.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a trench gate IGBT device structure and a manufacturing method thereof, and the electron injection quantity of an emission region can be enhanced by arranging an inverted trapezoid thick oxygen groove at the bottom of a trench, so that the conduction voltage drop Vceon is reduced, the conduction loss of the device during operation is improved, and meanwhile, the gate-drain capacitance Cgd is reduced, so that the feedback capacitance Crss is reduced, and the switching loss of the device is reduced.
In order to achieve the technical purpose, the technical scheme of the invention is as follows: the trench gate IGBT device structure is characterized in that a plurality of gate trenches are formed in the first conductive type epitaxial layer, the depth of each gate trench is consistent with the junction depth of a second conductive type body region adjacent to the left side and the right side, gate polysilicon and a gate oxide layer which is positioned on the outer side of the gate polysilicon and clings to the side wall of the gate trench are filled in each gate trench, an inverted trapezoid thick oxygen groove is formed below each gate trench, and the inverted trapezoid thick oxygen groove extends into the first conductive type epitaxial layer.
Further, a first conductive type source region is arranged in the second conductive type body region, the first conductive type source region is adjacent to the gate trench, an insulating medium layer is arranged on the gate trench, source metal is arranged on the insulating medium layer, and the source metal penetrates through the insulating medium layer to be in ohmic contact with the second conductive type body region and the first conductive type source region respectively.
Further, the included angle between the side wall and the bottom of the inverted trapezoid thick oxygen groove is smaller than 80 degrees, and the thickness of the inverted trapezoid thick oxygen groove is 1.8 um-2.2 um.
In order to further achieve the technical purpose, the invention also provides a manufacturing method of the trench gate IGBT device structure, which is characterized by comprising the following steps:
step one: selecting a first conductive type silicon substrate as a first conductive type substrate, adopting an epitaxial process to grow a first conductive type epitaxial layer on the upper surface of the first conductive type substrate, wherein the upper surface of the first conductive type epitaxial layer is a first main surface, and the lower surface of the first conductive type substrate is a second main surface;
injecting ions of a second conductivity type on the first main surface, and then pushing a well to form a second conductivity type body region;
step three, under the shielding of the graphical photoetching mask plate, selectively injecting first-conductivity-type ions into the second-conductivity-type body region to form a first-conductivity-type source region;
etching the first main surface under the shielding of the patterned photoetching mask plate to obtain a plurality of gate trenches adjacent to the first conductive type source region;
continuously etching the epitaxial layer of the first conductivity type, controlling the etching angle, and obtaining an inverted trapezoid groove below the gate groove;
step six, depositing an oxide layer in the inverted trapezoid groove to obtain an inverted trapezoid thick oxygen groove;
continuously depositing an oxide layer and polysilicon in the gate trench above the inverted trapezoid thick oxygen trench, and sequentially etching the polysilicon and the oxide layer to obtain a gate oxide layer positioned on the inner side wall of the gate trench and gate polysilicon surrounded by the gate oxide layer;
depositing an insulating medium layer on the first main surface, and selectively etching the insulating medium layer to obtain a metal contact through hole;
depositing metal on the insulating medium layer and in the metal contact through hole, and etching the metal to obtain source metal in ohmic contact with the first conductive type source region and the second conductive type body region;
step ten, thinning the second main surface, and injecting second conductivity type ions into the second main surface to obtain a first conductivity type buffer layer below the first conductivity type epitaxial layer and a second conductivity type hole injection layer below the first conductivity type buffer layer;
and step eleven, depositing metal below the hole injection layer of the second conductivity type to obtain collector metal.
Further, in the fourth step, the depth of the gate trench is identical to the junction depth of the second conductivity type body region.
Further, in the fifth step, dry etching is adopted in the process of etching the inverted trapezoid groove, and the etching angle and the bottom morphology are controlled by inputting protective gas into the etching equipment to control the etching pressure of the etching equipment and dynamically adjusting the stepwise variable gas protection atmosphere in the etching machine.
Further, in the fifth step, the included angle between the side wall and the bottom of the inverted trapezoid groove obtained by etching is smaller than 80 degrees, and the depth is 1.8 um-2.2 um.
Further, the IGBT device includes an N-type power semiconductor device and a P-type power semiconductor device, for the N-type power semiconductor device, the first conductivity type is N-type, the second conductivity type is P-type, for the P-type semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
Compared with the existing Trench FS-IGBT device, the invention has the following advantages:
1) The invention adopts the gate trench and the inverted trapezoid thick oxygen groove below the gate trench to replace the existing gate trench, so that the width of the N-type epitaxial layer below the P-type body region is increased, the resistance of the region is increased, and when holes injected into the N-type epitaxial layer from the collector flow into the N-type emitter (N-type source region) through the P-type body region, the holes can be accumulated in the N-type epitaxial layer below the P-type body region. According to the principle of conservation of charge, more electrons must be injected into the N-type epitaxial layer by the N-type emitter through the conducting channel, so that the carrier concentration in the region is greatly increased, as shown in fig. 13, the conductivity modulation effect is enhanced due to the increased carrier concentration, and the conduction voltage drop Vceon and the on-state loss are further reduced;
2) Because the inverted trapezoid thick oxygen groove is arranged below the gate groove, compared with the existing structure, the thickness of the oxide layer at the bottom of the gate polysilicon is increased, the capacitance between the gate and the collector is further reduced, and the feedback capacitance Crss of the device is reduced under the condition that the sidewall opening voltage VTH is not influenced;
3) According to the invention, by adjusting the etching inclination angle and thickness of the inverted trapezoid thick oxygen groove below the grid polycrystalline silicon, under the condition of ensuring that Vth and BV are unchanged, the voltage drop Vceon of the Trench FS-IGBT can be further reduced, the conduction loss of the device in operation is improved, the feedback capacitance Crss is reduced, and the switching loss of the device is reduced;
4) The manufacturing method of the invention is compatible with the prior art, and does not need to increase additional development cost.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:
fig. 1 is a schematic structural diagram of a conventional tree FS-IGBT device unit.
Fig. 2 is a schematic structural diagram of a tree FS-IGBT device unit according to embodiment 1 of the present invention.
Fig. 3 is a schematic cross-sectional view of an N-type epitaxial layer formed on an N-type substrate according to embodiment 1 of the present invention.
Fig. 4 is a schematic cross-sectional view of a P-type body region formed according to embodiment 1 of the present invention.
Fig. 5 is a schematic cross-sectional view of an N-type source region formed according to embodiment 1 of the present invention.
Fig. 6 is a schematic cross-sectional view of a gate trench formed in accordance with embodiment 1 of the present invention.
Fig. 7 is a schematic cross-sectional view of the inverted trapezoid groove formed in embodiment 1 of the present invention.
FIG. 8 is a schematic cross-sectional view of an oxygen tank with an inverted trapezoid shape according to embodiment 1 of the present invention.
Fig. 9 is a schematic diagram of a cross-sectional structure of forming a gate oxide layer and gate polysilicon according to embodiment 1 of the present invention.
Fig. 10 is a schematic cross-sectional view of an insulating dielectric layer formed according to embodiment 1 of the present invention.
Fig. 11 is a schematic cross-sectional view of a source metal formation in accordance with embodiment 1 of the present invention.
Fig. 12 is a schematic cross-sectional view of the formation of an N-type buffer layer and a P-type hole injection layer according to embodiment 1 of the present invention.
Fig. 13 is a carrier concentration graph along A-A' of a conventional Trench FS-IGBT device cell and a Trench FS-IGBT device cell according to embodiment 1 of the invention.
Reference numerals illustrate: 1. an N-type substrate; 2. an N-type epitaxial layer; 3. a gate trench; 4. an inverted trapezoid thick oxygen groove; 5. a P-type body region; 6. gate polysilicon; 7. a gate oxide layer; 8. an N-type source region; 9. an insulating dielectric layer; 10. a source metal; 11. inverted trapezoidal grooves; 12. an N buffer layer; 13. a P-type hole injection layer; 14. a collector metal; 001. a first major face; 002. a second major face.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
The present invention is not limited to the following embodiments, and the drawings referred to in the following description are provided so that the content of the present invention can be understood, that is, the present invention is not limited to the device structures exemplified by the drawings;
example 1: as shown in fig. 2, taking an N-type trench gate IGBT device structure as an example, the first conductivity type is N-type, the second conductivity type is P-type, the active region of the N-type trench gate IGBT device structure includes a plurality of IGBT device units, the IGBT device units include an N-type substrate 1 and an N-type epitaxial layer 2 located on the N-type substrate 1, a plurality of gate trenches 3 are provided in the N-type epitaxial layer 2, the depth of the gate trenches 3 is consistent with the junction depth of the P-type body regions 5 adjacent to the left and right, gate polysilicon 6 and a gate oxide layer 7 located outside the gate polysilicon 6 and closely attached to the sidewalls of the gate trenches 3 are filled in the gate trenches 3, an inverted trapezoid thick oxygen trench 4 is provided below the gate trenches 3, and the inverted trapezoid thick oxygen trench 4 is deep into the N-type epitaxial layer 2;
an N-type source region 8 is arranged in the P-type body region 5, the N-type source region 8 is adjacent to the gate trench 3, an insulating dielectric layer 9 is arranged on the gate trench 3, a source metal 10 and a gate metal are arranged on the insulating dielectric layer 9, the source metal 10 passes through the insulating dielectric layer 9 to be in ohmic contact with the P-type body region 5 and the N-type source region 8 respectively, and the gate metal passes through the insulating dielectric layer 9 to be in ohmic contact with the gate polysilicon 6, which is well known to the skilled person, and the gate metal is not marked in the figure.
The manufacturing method of the trench gate IGBT device structure in the embodiment comprises the following steps:
as shown in fig. 3, step one: an N-type silicon substrate is selected as an N-type substrate 1, an epitaxial process is adopted to grow an N-type epitaxial layer 2 on the upper surface of the N-type substrate 1, the upper surface of the N-type epitaxial layer 2 is a first main surface 001, and the lower surface of the N-type substrate 1 is a second main surface 002;
step two, as shown in fig. 4, implanting P-type ions on the first main surface 001, and then pushing the well to form a P-type body region 5;
step three, under the shielding of the patterned photolithography mask, selectively injecting N-type ions into the P-type body region 5 to form an N-type source region 8 positioned in the P-type body region 5, and removing the patterned photolithography mask;
etching the first main surface 001 under the shielding of the patterned photoetching mask plate to obtain a plurality of gate trenches 3 adjacent to the N-type source region 8 between the P-type body regions 5, wherein the depth of the gate trenches 3 is consistent with the junction depth of the P-type body regions 5;
step five, as shown in fig. 7, continuing to etch the N-type epitaxial layer 2, and controlling the etching angle to obtain an inverted trapezoid groove 11 below the gate groove 3; removing the patterned photoetching mask plate;
in the process of etching the inverted trapezoid groove 11, dry etching is adopted, etching pressure of etching equipment is controlled by inputting protective gas into the etching equipment, meanwhile, the gas protective atmosphere which is changed step by step in an etching machine table is dynamically adjusted to control etching angles and bottom morphology, and the included angle between the side wall and the bottom of the inverted trapezoid groove 11 obtained by etching is smaller than 80 degrees and the depth is about.2um;
step six, as shown in fig. 8, depositing an oxide layer in the inverted trapezoid groove 11 and on the first main surface 001, selectively etching the oxide layer, and reserving the oxide layer in the inverted trapezoid groove 11 to obtain an inverted trapezoid thick oxygen groove 4 positioned in the inverted trapezoid groove 11, wherein an included angle between the side wall and the bottom of the inverted trapezoid thick oxygen groove 4 is smaller than 80 degrees, and the thickness is about 2um;
step seven, continuously depositing an oxide layer and polysilicon in the gate groove 3 above the inverted trapezoid thick oxygen groove 4, and sequentially etching the polysilicon and the oxide layer to obtain a gate oxide layer 7 positioned on the inner side wall of the gate groove 3 and a gate polysilicon 6 surrounded by the gate oxide layer 7;
step eight, as shown in fig. 10, depositing an insulating dielectric layer 9 on the first main surface 001, and selectively etching the insulating dielectric layer 9 to obtain a metal contact through hole;
step nine, as shown in fig. 11, depositing metal on the insulating dielectric layer 9 and in the metal contact via hole, and etching the metal to obtain a source metal 10 in ohmic contact with the N-type source region 8 and the P-type body region 5 and a gate metal (not shown here) in ohmic contact with the gate polysilicon 6;
as shown in fig. 12, step ten, the second main surface 002 is thinned, and then P-type ions are implanted to obtain an N-type buffer layer 12 below the N-type epitaxial layer 2 and a P-type hole injection layer 13 below the N-type buffer layer 12;
and step eleven, depositing metal below the P-type hole injection layer 13 to obtain collector metal 14.
For the conventional Trench FS-IGBT device, holes injected into the N-type epitaxial layer 2 from the collector are hardly accumulated in the N-type epitaxial layer 2 below the P-type body region 5, so electrons are injected into the N-type epitaxial layer 2 from the N-type emitter through the conducting channel and hardly pass through the N-type epitaxial layer 2 below the P-type body region 5, and the carrier concentration of the region is not increased, as shown in FIG. 13; the gate trench 3 and the inverted trapezoid thick oxygen groove 4 below the gate trench 3 are adopted to replace the conventional gate trench, so that the width of the N-type epitaxial layer 2 below the P-type body region 5 is increased, the resistance of the region is increased, when holes injected into the N-type epitaxial layer 2 from the collector flow into the N-type emitter (namely the N-type source region 8) through the P-type body region 5, the holes can be accumulated in the N-type epitaxial layer 2 below the P-type body region 5, and according to the principle of conservation of charge, the N-type emitter must inject more electrons into the N-type epitaxial layer 2 through a conducting channel, so that the concentration of carriers in the region is greatly increased, as shown in fig. 13, the concentration of carriers is increased, so that the conductivity modulation effect is enhanced, and the on-voltage drop Vceon and on-state loss are further reduced; meanwhile, as the inverted trapezoid thick oxygen groove 4 is arranged below the gate groove 3, compared with the existing structure, the thickness of the oxide layer at the bottom of the gate polysilicon 6 is increased, and then the capacitance Cgd between the gate and the collector is reduced, and the feedback capacitance Crss of the device is reduced under the condition that the sidewall starting voltage VTH is not influenced;
therefore, by adjusting the etching dip angle and thickness of the inverted trapezoid thick oxygen groove 4 below the grid polysilicon 6, the invention can further reduce the conduction voltage drop Vceon of the Trench FS-IGBT, improve the conduction loss of the device during operation, reduce the feedback capacitance Crss and reduce the switching loss of the device under the condition of ensuring that the Vth and BV are unchanged.
The invention and its embodiments have been described above with no limitation, and the actual construction is not limited to the embodiments of the invention as shown in the drawings. In summary, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical solution should not be creatively devised without departing from the gist of the present invention.
Claims (8)
1. The utility model provides a trench gate IGBT device structure, its active region includes a plurality of IGBT device unit, IGBT device unit includes first conductivity type substrate (1) and is located first conductivity type epitaxial layer (2) on first conductivity type substrate (1), its characterized in that is equipped with a plurality of gate slot (3) in first conductivity type epitaxial layer (2), the degree of depth of gate slot (3) is unanimous with the junction depth of the second conductivity type body district (5) that control borders on, is filled with gate polycrystalline silicon (6) and is located gate polycrystalline silicon (6) outside and hugs closely gate oxide layer (7) of gate slot (3) lateral wall in gate slot (3) intussuseption in gate slot (3) below is equipped with thick oxygen groove (4) of reverse trapezoid, thick oxygen groove (4) of reverse trapezoid are in deep into first conductivity type epitaxial layer (2).
2. The trench gate IGBT device structure according to claim 1, characterized in that a first conductivity type source region (8) is provided in the second conductivity type body region (5), and the first conductivity type source region (8) adjoins the gate trench (3), an insulating dielectric layer (9) is provided on the gate trench (3), a source metal (10) is provided on the insulating dielectric layer (9), and the source metal (10) is in ohmic contact with the second conductivity type body region (5) and the first conductivity type source region (8) respectively through the insulating dielectric layer (9).
3. The trench gate IGBT device structure according to claim 1, wherein an included angle between a side wall and a bottom of the inverted trapezoid thick oxygen trench (4) is smaller than 80 °, and a thickness of the inverted trapezoid thick oxygen trench (4) is 1.8um to 2.2um.
4. The manufacturing method of the trench gate IGBT device structure is characterized by comprising the following steps of
Step one: selecting a first conductive type silicon substrate as a first conductive type substrate (1), adopting an epitaxial process to grow a first conductive type epitaxial layer (2) on the upper surface of the first conductive type substrate (1), wherein the upper surface of the first conductive type epitaxial layer (2) is a first main surface (001), and the lower surface of the first conductive type substrate (1) is a second main surface (002);
injecting ions of a second conductivity type on the first main surface (001), and then pushing a well to form a second conductivity type body region (5);
step three, under the shielding of the graphical photoetching mask plate, selectively injecting first conductivity type ions into the second conductivity type body region (5) to form a first conductivity type source region (8);
etching the first main surface (001) under the shielding of the graphical photoetching mask plate to obtain a plurality of gate grooves (3) adjacent to the first conductive type source region (8);
continuously etching the first conductive type epitaxial layer (2), controlling the etching angle, and obtaining an inverted trapezoid groove (11) below the gate groove (3);
step six, depositing an oxide layer in the inverted trapezoid groove (11) to obtain an inverted trapezoid thick oxygen groove (4);
continuously depositing an oxide layer and polysilicon in the gate groove (3) above the inverted trapezoid thick oxygen groove (4), and sequentially etching the polysilicon and the oxide layer to obtain a gate oxide layer (7) positioned on the inner side wall of the gate groove (3) and gate polysilicon (6) surrounded by the gate oxide layer (7);
depositing an insulating medium layer (9) on the first main surface (001), and selectively etching the insulating medium layer (9) to obtain a metal contact through hole;
step nine, depositing metal on the insulating medium layer (9) and in the metal contact through hole, and etching the metal to obtain source metal (10) in ohmic contact with the first conductive type source region (8) and the second conductive type body region (5);
step ten, thinning the second main surface (002), and injecting second conductivity type ions into the second main surface (002) to obtain a first conductivity type buffer layer (12) below the first conductivity type epitaxial layer (2) and a second conductivity type hole injection layer (13) below the first conductivity type buffer layer (12);
and eleventh, depositing metal below the second conduction type hole injection layer (13) to obtain collector metal (14).
5. The method according to claim 4, wherein in the fourth step, the depth of the gate trench (3) is identical to the junction depth of the second conductivity type body region (5).
6. The method for fabricating a trench gate IGBT device according to claim 4, wherein in the fifth step, during the process of etching the inverted trapezoid trench (11), dry etching is adopted, and the etching angle and the bottom morphology are controlled by inputting a protective gas into the etching equipment, controlling the etching pressure of the etching equipment, and dynamically adjusting the stepwise gas-protecting atmosphere in the etching machine.
7. The method for fabricating a trench gate IGBT device according to claim 4, wherein in the fifth step, an included angle between a sidewall and a bottom of the inverted trapezoid trench (11) obtained by etching is smaller than 80 °, and a depth is 1.8um to 2.2um.
8. The method for fabricating a trench gate IGBT device structure of claim 4 wherein the IGBT device comprises an N-type power semiconductor device and a P-type power semiconductor device, wherein for the N-type power semiconductor device, the first conductivity type is N-type, the second conductivity type is P-type, and for the P-type semiconductor device, the first conductivity type is P-type, and the second conductivity type is N-type.
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