CN220754801U - Time delay device - Google Patents
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- CN220754801U CN220754801U CN202322467552.0U CN202322467552U CN220754801U CN 220754801 U CN220754801 U CN 220754801U CN 202322467552 U CN202322467552 U CN 202322467552U CN 220754801 U CN220754801 U CN 220754801U
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Abstract
The utility model relates to the technical field of integrated circuits, in particular to a time delay device, which comprises a second current source, a control end and a delay circuit, wherein the control end is connected with an external bias signal; the input end of the first current source is connected with the input end of the second current source, and the control end of the first current source is connected with an external bias signal; the input end of the first sub-controller is connected with the output end of the first current source, and the control end of the first sub-controller is connected with the output end of an external signal processing device; the first energy storage unit is connected with the second current source; the second energy storage unit is connected with the first sub-controller; the second sub-controller is connected with the output end of the first sub-controller, and the control end is connected with the output end of the third inverter; the first processing unit is connected with the second energy storage unit at the first input end, the second input end is connected with the output end of the second processing unit, the output end is connected with the control end of the third sub-controller, the input end of the second processing unit is connected with the output end of the frequency divider, and an output signal is formed according to the received input signal to be output.
Description
Technical Field
The utility model relates to the technical field of integrated circuits, in particular to a time delay device.
Background
In chip processing work, delay processing is usually needed to be carried out on signals, more delay circuits are usually arranged in the design process of an integrated circuit for achieving the purpose of delay, and the generated analog signals and digital signals are delayed by the chip through controlling components in the circuit, so that the action time of the circuit is controlled, meanwhile, the stability and reliability of the chip can be guaranteed by the delay circuits, and the interference of noise signals on the chip is avoided.
The delay circuit commonly adopted in the existing design is an RC delay circuit, the design structure of the RC delay circuit is relatively simple in structure, but the defects of low precision, large noise and inconvenient frequency adjustment exist, and the delay output amplitude is not stable enough due to the fact that negative feedback is not available, the delay time is limited, a capacitor with a larger area is needed for obtaining longer delay, and a large amount of area is wasted, so that the cost is increased.
Disclosure of Invention
To the shortcomings of the prior art, the utility model provides a time delay device, in particular:
in one aspect, the present utility model provides a time delay apparatus, wherein: comprising the steps of (a) a step of,
the input end of the second current source is connected with the power end, and the control end of the second current source is connected with an external bias signal;
the input end of the first current source is connected with the input end of the second current source, and the control end of the first current source is connected with an external bias signal;
the input end of the first sub-controller is connected with the output end of the first current source, and the control end of the first sub-controller is connected with the output end of an external signal processing device;
the input end of the first energy storage unit is respectively connected with the output end of the second current source and the input end of the third inverter;
the second energy storage unit is respectively connected with the output end of the first sub-controller and the input end of the frequency divider;
the input end of the second sub-controller is connected with the output end of the first sub-controller, the control end of the second sub-controller is connected with the output end of the third inverter, and the output end of the second sub-controller is grounded;
the first input end of the first processing unit is connected with the second energy storage unit, the second input end of the first processing unit is connected with the output end of the second processing unit, and the output end of the first processing unit is connected with the control end of the third sub-controller;
the input end of the second processing unit is connected with the output end of the frequency divider, and forms an output signal output according to the received input signal.
Preferably, the delay device comprises: the external signal processing device comprises a first inverter, wherein the input end of the first inverter is used for receiving an external input signal, and performing inversion processing on the external input signal and outputting the external input signal.
Preferably, the delay device comprises: the frequency divider is formed by at least one D trigger, and the output end of the D trigger is connected with the input end of the second processing unit.
Preferably, the delay device comprises: the circuit further comprises a first stabilizing unit, wherein the first stabilizing unit is connected between the second energy storage unit and the frequency divider, the first stabilizing unit is formed by a Schmidt trigger and a second inverter, the input end of the Schmidt trigger is connected with the second energy storage unit, the output end of the Schmidt trigger is connected with the input end of the second inverter, and the output end of the second inverter is connected with the frequency divider.
Preferably, the delay device comprises: the second stabilizing unit is formed by a resistor, and the resistor is connected between the second energy storage unit and the control end of the second sub-controller.
Preferably, the delay device comprises: the first processing unit is formed by an or-gate.
Preferably, the delay device comprises: the second processing unit is formed by an and gate.
Preferably, the delay device comprises: the first energy storage unit and/or the second energy storage unit are/is formed by NMOS (N-channel metal oxide semiconductor) tubes.
Preferably, the delay device comprises: the second current source, the first current source or the first sub-controller is formed by a PMOS tube.
Preferably, the delay device comprises: the control end of the fourth sub-controller is connected with the external signal processing device, the input end of the fourth sub-controller is connected with the output end of the first sub-controller, and the output end of the fourth sub-controller is grounded.
Compared with the prior art, the utility model has the beneficial effects that: under the condition of realizing millisecond-level delay, relatively more delay period quantity is established through frequency division of the D trigger, and in addition, the delay time can be finely adjusted by adjusting the capacitance value of the capacitor, so that a large amount of capacitor area is saved compared with a common RC circuit. Furthermore, the circuit can flexibly adjust the delay time by increasing or decreasing the number of the D triggers, and a feedback mechanism (taking the output signal of the second processing unit as the input of the first processing unit) is added in the circuit, so that the delay output amplitude is stable. And the delay circuit also has the advantage of low power consumption.
Drawings
In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of a delay device according to an embodiment of the present utility model;
fig. 2 is a schematic circuit diagram of a delay device according to an embodiment of the present utility model.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
As shown in fig. 1 and 2, in one aspect, the present utility model provides a delay device, where: comprising the steps of (a) a step of,
the input end of the second current source is connected with the power end, and the control end of the second current source is connected with an external bias signal; further, the external bias signal may be an external bias voltage signal VBP1. The power supply end is used for outputting a power supply voltage VDD;
the input end of the first current source is connected with the input end of the second current source, the control end of the first current source is connected with an external bias signal, and the second current source and the first current source are both used for converting the power supply voltage VDD into a current signal under the action of the external bias signal and outputting the current signal to charge the first energy storage unit and the second energy storage unit (under the conduction state of the first sub-controller). Further, the second current source, and/or the first current source may be formed of PMOS transistors. For example, the second current source is formed by the first MOS transistor PM1, and the first current source is formed by the fifth MOS transistor PM 5.
In a state where the external bias voltage signal VBP1 is a low level signal, the first MOS transistor PM1 is operated in a conductive state, and the fifth MOS transistor PM5 is also operated in a conductive state. At this time, the first MOS transistor PM1 and the fifth MOS transistor PM5 form a charging current based on the power supply voltage.
The input end of the first sub-controller is connected with the output end of the second current source, and the control end of the first sub-controller is connected with the output end of an external signal processing device; further, the first sub-controller is intended to form a control switch, and the first sub-controller may be formed by the second MOS tube PM2, and the signal output by the external signal processing device acts on the second MOS tube PM2 to control the working state of the second MOS tube PM 2. When the external signal processing device outputs a low-level signal, the second MOS tube PM2 works in a conducting state. Otherwise, the second MOS transistor PM2 operates in the off state.
The input end of the first energy storage unit is respectively connected with the output end of the first current source, the input ends of the third inverter and the third sub-controller; further, the first energy storage unit may be formed by an NMOS transistor, specifically, a source electrode and a drain electrode of the NMOS transistor are connected, a gate electrode of the NOMS transistor forms an input end of the first energy storage unit, and illustratively, the first energy storage unit is formed by a sixth MOS transistor NM6, and in a state that the first current source works in a conducting state, the low current output by the first current source charges the sixth MOS transistor NM 6;
the input end of the second energy storage unit is respectively connected with the output end of the first sub-controller and the input end of the frequency divider; the second energy storage unit may be formed by an NMOS transistor, specifically, a source electrode and a drain electrode of the NMOS transistor are connected, a gate electrode of the NOMS transistor forms an input end of the second energy storage unit, and illustratively, the second energy storage unit is formed by a ninth MOS transistor NM9, and the low current output by the first current source charges the ninth MOS transistor NM9 when the second current source is operated in a conductive state and the first sub-controller is operated in a conductive state.
The input end of the second sub-controller is connected with the output end of the first sub-controller, and the control end of the second sub-controller is connected with the output end of the third inverter; the output end is grounded; further, the second sub-controller may be formed of an eighth MOS transistor NM8, and in a state in which the third inverter outputs a high level, the eighth MOS transistor NM8 is turned on, and at this time, the ninth MOS transistor NM9 is turned on through the eighth MOS transistor NM8 to perform a discharge process, that is, a gate voltage of the ninth MOS transistor NM9 is reduced.
The first processing unit, the first input end is connected with the second energy storage unit, the second input end is connected with the output end of the second processing unit, the output end is connected with the control end of the third sub-controller, further, the first processing unit can be formed by an OR gate logic circuit, and the third sub-controller is formed by a seventh MOS tube NM 7. In the state that any one of the second energy storage unit and the second processing unit outputs a high level signal, the first processing unit outputs a high level, whereas in the state that both the second energy storage unit and the second processing unit output a low level, the first processing unit outputs a low level. In the state that the first processing unit outputs the high level, the seventh MOS transistor NM7 is operated in the on state, and at this time, the first energy storage unit discharges to the ground through the third sub-controller, that is, the sixth MOS transistor NM6 discharges to the ground through the seventh MOS transistor NM7 (corresponding to the sixth MOS transistor NM6 operating in the discharge state), and in the state that the first processing unit outputs the low level, the seventh MOS transistor NM7 operates in the off state, and at this time, the first energy storage unit is powered by the power supply voltage, that is, the sixth MOS transistor NM6 operates in the charge state.
The input end of the second processing unit is connected with the output end of the frequency divider, and forms an output signal output according to the received input signal. Further, the second processing unit may be formed by an and gate logic circuit, and input ends of the and gate logic circuit are respectively connected with output ends of the frequency divider. When the output of the frequency divider is in a high level signal state, the AND gate logic circuit outputs a high level, otherwise, the AND gate logic circuit outputs a low level. And under the state that the AND gate logic circuit outputs high level, the first processing unit continuously outputs a high level signal according to the high level, namely the third sub-controller is continuously in a conducting state, and the time delay processing is finished.
As a further preferred embodiment, a time delay device as described above, wherein: the external signal processing device comprises a first inverter, wherein the input end of the first inverter is used for receiving an external input signal, and performing inversion processing on the external input signal and outputting the external input signal. Illustratively, in a high state of the external input signal VIN, the first inverter F1 inverts the external input signal VIN to form a low signal output. In the low state of the external input signal VIN, the first inverter F1 forms a high signal output.
As a further preferred embodiment, the delay device is formed by at least one D flip-flop, and an output terminal of the D flip-flop is connected to an input terminal of the second processing unit. Illustratively, the delay time of the second processing unit is increased for each D flip-flop added. For example, when the frequency divider comprises 3D flip-flops, then the second processing unit needs to go through 7 (2 3 -1) a high signal is output only for a charge-discharge period, the second processing unit then needs to go through 15 (2) when the divider comprises four D flip-flops 4 -1) a high level signal is output only after a charge-discharge period. The delay period or delay time can be flexibly adjusted by setting the number of the D triggers.
As a further preferred embodiment, a time delay device as described above, wherein: the circuit further comprises a first stabilizing unit, wherein the first stabilizing unit is connected between the second energy storage unit and the frequency divider, the first stabilizing unit is formed by a Schmitt trigger S1 and a second inverter F2, the input end of the Schmitt trigger is connected with the second energy storage unit, the output end of the Schmitt trigger is connected with the input end of the second inverter, and the output end of the second inverter is connected with the frequency divider. The schmitt trigger is added to generate a rectangular wave with fixed turning points and can play a role in shaping waveforms.
As a further preferred embodiment, a time delay device as described above, wherein: the energy storage device further comprises a second stabilizing unit, wherein the second stabilizing unit is formed by a resistor R1, and the resistor R1 is connected between the second energy storage unit and the control end of the second sub-controller. The resistor R1 is used for limiting the discharge current of the second energy storage unit in a state of discharging to the ground; further, the resistor may be formed by a current mirror, and the current mirror may achieve the same technical effects and technical purposes as the resistor.
As a further preferred embodiment, a time delay device as described above, wherein: the control end of the fourth sub-controller is connected with the external signal processing device, the input end of the fourth sub-controller is connected with the output end of the first sub-controller, and the output end of the fourth sub-controller is grounded. Further, the fourth sub-controller is formed by a third MOS transistor NM 3. In the state that the external input signal VIN changes from high level to low level, the third MOS transistor NM3 is formed to acquire high level, and at this time, the third MOS transistor NM3 is operated in the on state, so that the power consumption in the circuit is relatively small, and only the third MOS transistor NM3 is always in the operating state.
The specific working principle is shown in fig. 2, a delay device is designed to generate a predetermined delay between output and output when the control end of the fifth MOS tube PM5 obtains a voltage signal for driving the fifth MOS tube PM5 to work in a conducting state (when the fifth MOS tube PM5 works in a conducting state, the first MOS tube PM1 also works in a conducting state), a power supply voltage VDD connected to the input end of the fifth MOS tube PM5 is transmitted to the NTE1 node, that is, the voltage of the NTE1 node is VDD, the VDD voltage is a charging process of the sixth MOS tube NM6, when the input signal VIN jumps from a low level to a high level, a high level signal forms a low level signal through the first inverter F1, and the low level signal drives the second MOS tube PM2 to conduct. The voltage of the third node NTE3 charges the ninth MOS tube NM9, when the charging voltage of the ninth MOS tube NM9 is larger than the turning voltage of the Schmitt trigger S1, the Schmitt trigger S1 turns over once, at the moment, the second inverter outputs a low-level signal reversely into a high-level signal to the NET2 node, namely the NET2 node is high-level, the OR gate circuit S2 outputs high-level, the high-level signal drives the seventh MOS tube NM7 to be conducted, the sixth MOS tube NM6 discharges to the ground through the seventh MOS tube NM7, the NTE1 node voltage is pulled down to be low level, the low-level signal reversely processes through the third inverter F3 to form a high-level signal, the high-level signal drives the eighth MOS tube NM8 to be conducted, at the moment, the ninth MOS tube NM9 discharges to the ground through the eighth MOS tube NM8, when the gate voltage of the ninth MOS transistor NM9 drops to the inversion voltage of the schmitt trigger S1, the schmitt trigger S1 is turned over again, and then the second inverter F2 inverts the high-level signal into the low-level signal to output the low-level signal to the NET2 node, that is, the NET2 node is the low-level signal, the or circuit S2 outputs the low-level signal, the seventh MOS transistor NM7 is driven to operate in the off state, the power supply voltage VDD continues to charge the sixth MOS transistor NM6, the NTE1 node voltage becomes the high level, the high-level signal is inverted by the third inverter F3 to form the low-level signal, the low-level signal drives the eighth MOS transistor NM8 to operate in the off state, and the power supply voltage VDD continues to charge the ninth MOS transistor NM9, so that the cycle continues. Because the voltage at the second node NET2 is simultaneously transmitted to the frequency dividers (the frequency dividers are formed by at least one D flip-flop, the D flip-flops are linked with each other, each frequency divider forms a level signal output), the and gate S3 outputs a high level signal in a state that the frequency divider outputs a high level signal, the high level signal is transmitted to the or gate S2, the or gate S2 receives the high level signal and outputs a high level signal, the high level signal drives the NM7 to be in a conducting state, the sixth MOS NM6 discharges to the ground, the NET1 node voltage is pulled down, the third inverter F3 outputs a high level at this time, the eighth MOS NM8 is turned on, the NET3 terminal voltage is continuously pulled down, and the ninth MOS NM9 discharges to the ground. Since the and circuit S3 continuously outputs the high level signal, the cyclic oscillation is terminated at this time, i.e., the delay time is ended.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present utility model. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present utility model is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A time delay device, characterized by: comprising the steps of (a) a step of,
the input end of the second current source is connected with the power end, and the control end of the second current source is connected with an external bias signal;
the input end of the first current source is connected with the input end of the second current source, and the control end of the first current source is connected with an external bias signal;
the input end of the first sub-controller is connected with the output end of the first current source, and the control end of the first sub-controller is connected with the output end of an external signal processing device;
the input end of the first energy storage unit is respectively connected with the output end of the second current source and the input end of the third inverter;
the second energy storage unit is respectively connected with the output end of the first sub-controller and the input end of the frequency divider;
the input end of the second sub-controller is connected with the output end of the first sub-controller, the control end of the second sub-controller is connected with the output end of the third inverter, and the output end of the second sub-controller is grounded;
the first input end of the first processing unit is connected with the second energy storage unit, the second input end of the first processing unit is connected with the output end of the second processing unit, and the output end of the first processing unit is connected with the control end of the third sub-controller;
the input end of the second processing unit is connected with the output end of the frequency divider, and forms an output signal output according to the received input signal.
2. A time delay device as claimed in claim 1, characterized in that: the external signal processing device comprises a first inverter, wherein the input end of the first inverter is used for receiving an external input signal, and performing inversion processing on the external input signal and outputting the external input signal.
3. A time delay device as claimed in claim 1, characterized in that: the frequency divider is formed by at least one D trigger, and the output end of the D trigger is connected with the input end of the second processing unit.
4. A time delay device as claimed in claim 1, characterized in that: the circuit further comprises a first stabilizing unit, wherein the first stabilizing unit is connected between the second energy storage unit and the frequency divider, the first stabilizing unit is formed by a Schmidt trigger and a second inverter, the input end of the Schmidt trigger is connected with the second energy storage unit, the output end of the Schmidt trigger is connected with the input end of the second inverter, and the output end of the second inverter is connected with the frequency divider.
5. A time delay device as claimed in claim 1, characterized in that: the second stabilizing unit is formed by a resistor, and the resistor is connected between the second energy storage unit and the control end of the second sub-controller.
6. A time delay device as claimed in claim 1, characterized in that: the first processing unit is formed by an or-gate.
7. A time delay device as claimed in claim 1, characterized in that: the second processing unit is formed by an and gate.
8. A time delay device as claimed in claim 1, characterized in that: the first energy storage unit and/or the second energy storage unit are/is formed by NMOS (N-channel metal oxide semiconductor) tubes.
9. A time delay device as claimed in claim 1, characterized in that: the second current source, the first current source or the first sub-controller is formed by a PMOS tube.
10. A time delay device as claimed in claim 1, characterized in that: the control end of the fourth sub-controller is connected with the external signal processing device, the input end of the fourth sub-controller is connected with the output end of the first sub-controller, and the output end of the fourth sub-controller is grounded.
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| CN202322467552.0U CN220754801U (en) | 2023-09-12 | 2023-09-12 | Time delay device |
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| CN202322467552.0U CN220754801U (en) | 2023-09-12 | 2023-09-12 | Time delay device |
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