CN114826273A - Current frequency conversion circuit and method based on dual-comparator control - Google Patents
Current frequency conversion circuit and method based on dual-comparator control Download PDFInfo
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- CN114826273A CN114826273A CN202210434533.5A CN202210434533A CN114826273A CN 114826273 A CN114826273 A CN 114826273A CN 202210434533 A CN202210434533 A CN 202210434533A CN 114826273 A CN114826273 A CN 114826273A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/60—Analogue/digital converters with intermediate conversion to frequency of pulses
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
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Abstract
The invention discloses a current frequency conversion circuit and a method based on dual comparator control, wherein the current frequency conversion circuit comprises: the circuit comprises an integrator, a main comparator, an auxiliary comparator, a ring oscillator, an RS latch, a D trigger, an AND gate, a NOT gate and a reset switch. The invention uses the auxiliary comparator to turn over in advance and controls the main high-frequency dynamic comparator to work in part of time in the period, thereby not only effectively reducing the power consumption of the system, but also improving the precision and the linearity of current frequency conversion.
Description
Technical Field
The invention belongs to the field of integrated circuits, and particularly relates to a current frequency conversion circuit and a method based on dual comparator control.
Background
In the application of current detection, a current frequency conversion circuit is applied. The current frequency conversion circuit converts the current signal into a frequency signal, and measures the magnitude of the current signal indirectly by measuring the frequency of the output signal. The current frequency conversion circuit has the advantages of simple structure, easy realization, low cost and high conversion resolution.
Fig. 1 is a schematic structural diagram of a conventional current-to-frequency conversion circuit, which mainly includes an integrator 700, a comparator 750, a monostable trigger circuit 760, and a reset switch. Wherein the integrator 700 is formed by an operational amplifier 705 and a feedback capacitor 710. In thatIn the working process of the circuit, when the output voltage 730 of the integrator 700 is greater than the reference voltage 740 of the comparator 750, the output voltage 755 of the comparator 750 is inverted, and then the monostable circuit 760 is triggered to generate a pulse signal 800 to control the closing of the reset switch, so as to realize the discharging operation of the feedback capacitor 710. As shown in fig. 2, in the structure of the conventional current-frequency conversion circuit, a transconductance amplifier (OTA) is generally used as a comparator, which is a continuous-time comparator, and such a comparator does not generally have a loop with positive feedback like a dynamic comparator. Since the current-frequency conversion circuit always compares the output voltage 730 of the integrator 700 with the reference voltage 740 of the comparator during operation, the current of the comparator 750 is not reasonably utilized due to the continuous operation of the comparator, which increases the power consumption of the current-frequency conversion circuit. In addition, the general OTA-based comparator is slow and generates a delay T according to the process, power voltage, and temperature variation (PVT) d As shown in fig. 3. Therefore, the delay generated by the comparator may cause the zero crossing point to be detected inaccurately, and as a result, the output frequency of the current frequency conversion circuit has an error, which affects the linearity and precision of the current frequency conversion circuit.
In summary, the conventional current-frequency conversion circuit has the problems of large power consumption, low linearity and low precision.
Disclosure of Invention
In order to solve the technical problems mentioned in the background art, the present invention provides a current frequency conversion circuit based on dual comparator control.
In order to achieve the technical purpose, the technical scheme of the invention is as follows:
a current frequency conversion circuit based on dual comparator control comprises an integrator, a reset switch, a main comparator, an auxiliary comparator, a first D trigger, a ring oscillator, an RS latch, a second D trigger, an AND gate and a NOT gate, wherein an external power supply to be tested is connected to the reverse input end of the integrator, the reverse input end of the integrator is connected to the output end of the integrator after being connected to the reset switch, the forward input end of the integrator is grounded, the output end of the integrator is connected to the forward input ends of the main comparator and the auxiliary comparator, the reverse input end of the main comparator is connected to a reference potential A, the reverse input end of the auxiliary comparator is connected to a reference potential B, and the output end of the main comparator is connected to the clock input end of the first D trigger, the input end of the NOT gate and the second input end of the AND gate, the reverse output end of the first D trigger is connected with the input end of the ring oscillator, the output end of the ring oscillator is connected with the clock input end of the auxiliary comparator, the forward output end of the auxiliary comparator is connected with the S input end of the RS latch, the reverse output end of the auxiliary comparator is connected with the R input end of the RS latch, the output end of the RS latch is connected with the clock input end of the second D trigger, the output end of the NOT gate is connected with the reset end of the second D trigger, the forward output end of the second D trigger is connected with the first input end of the AND gate, and the output end of the AND gate is connected with the reset switch and is connected with the reset end of the first D trigger.
Preferably, the master comparator is a continuous time comparator.
Preferably, the auxiliary comparator is a clocked dynamic comparator.
Preferably, the reference potential a is smaller than the reference potential B.
Preferably, the ring oscillator includes a field effect transistor and n phase inverters sequentially connected end to end, n is an odd number, the reverse output end of the first D flip-flop is connected to the gate of the field effect transistor, the source of the field effect transistor is grounded, the drain of the field effect transistor is connected to the timing input end of each phase inverter, and the output end of the nth phase inverter is connected to the clock input end of the auxiliary comparator.
Preferably, the ring oscillator includes an NMOS transistor and n phase inverters sequentially connected end to end, where n is an odd number, the forward output end of the first D flip-flop is connected to the gate of the NMOS transistor, the source of the NMOS transistor is grounded, the drain of the NMOS transistor is connected to the timing input end of each phase inverter, and the output end of the nth phase inverter is connected to the clock input end of the auxiliary comparator.
A current frequency conversion method of a current frequency conversion circuit based on dual comparator control comprises the following steps:
(1) the current source to be measured flows into the integrator, and the voltage of the output end of the integrator is gradually increased;
(2) in the process that the voltage of the output end of the integrator is gradually increased, when the voltage of the output end of the integrator is higher than a reference potential A, the main comparator starts to turn over, the ring oscillator is controlled by the first D trigger to generate a clock signal, the ring oscillator sends a trigger signal to the auxiliary comparator, and the auxiliary comparator starts to operate after receiving the trigger signal;
(3) when a signal at the positive input end of the auxiliary comparator is higher than a reference potential B, the output of the auxiliary comparator is overturned, and an RS latch is triggered to output and overturn;
(4) the switching of the output of the RS latch triggers the conduction of a reset switch by controlling a second D trigger and an AND gate, a feedback capacitor in the integrator discharges, and the output voltage of the integrator drops; meanwhile, an AND gate output signal controls the ring oscillator to stop oscillating through the first D trigger, and the auxiliary comparator stops working;
(5) when the output voltage of the integrator is reduced to the reference potential A, the output of the main comparator is inverted, and the reset switch is disconnected through the AND gate; and starting a new round of charge and discharge process.
Adopt the beneficial effect that above-mentioned technical scheme brought:
1. the main comparator is used for reversing in advance to generate an enable signal to control the auxiliary comparator to work. Because the power consumption of the main comparator is very low, the auxiliary comparator is started only in part of the time in the period, and the purpose of reducing the power consumption of the system is achieved.
2. The auxiliary comparator adopts a high-frequency dynamic comparator, so that zero crossing point detection can be more accurately realized, and the linearity and the precision of the system are improved.
3. The auxiliary dynamic comparator turns off the input clock signal through the feedback signal immediately after detecting that the input signal reaches the reference voltage of the auxiliary dynamic comparator, so that the auxiliary comparator stops working in time, and the power consumption of the system is further reduced.
Drawings
Fig. 1 is a conventional current-frequency conversion circuit diagram;
the circuit includes a current source to be measured 720, an integrator 700, a feedback capacitor 710, an operational amplifier 705, a comparator 750, a monostable trigger circuit 760, an integrator 730, a comparator 740, a comparator 755, a monostable trigger circuit 755, and a monostable circuit 800.
FIG. 2 is a circuit diagram of an OTA-based continuous-time comparator;
FIG. 3 is the delay T of an OTA-based continuous-time comparator d A waveform diagram;
FIG. 4 is a circuit diagram of a ring oscillator enable using PMOS and NMOS, respectively;
FIG. 5 is a circuit diagram of a dual comparator based current-to-frequency conversion circuit according to the present disclosure;
wherein 120 is a current source to be tested, 100 is an integrator, 110 is a feedback capacitor in the integrator, 105 is an operational amplifier in the integrator, 200 is a main comparator, 220 is a D flip-flop, 300 is a ring oscillator, 305 is an enabling MOS (metal oxide semiconductor) transistor of the ring oscillator, 330-1 to 330-n are odd number of inverters which are sequentially connected end to end in the ring oscillator, 400 is an auxiliary comparator, 430 is an RS latch, 520 is a NOT gate, 505 is the D flip-flop, 530 is an AND gate, 130 is an output signal of the integrator and is a forward input signal of the main comparator and the auxiliary comparator at the same time, 205 is an inverted input signal of the main comparator, 405 is an inverted input signal of the auxiliary comparator, 210 is an output signal of the comparison main comparator and is an input clock signal of the D flip-flop 220 at the same time, 225 is an inverted output signal of the D flip-flop 220 and is a signal connected to a grid electrode of the enabling transistor in the ring oscillator at the same time, the output signal of 320 is the ring oscillator and is also the input clock signal of the auxiliary comparator, 410 and 415 are the forward and reverse output signals of the auxiliary comparator, 410 and 415 are the set end and reset end signals of the RS latch, 435 is the forward output signal of the RS latch and is also the input clock signal of the D flip-flop 505, 210 is the input signal of the not gate 520, 515 is the output signal of the not gate 520 and is also the reset end signal of the D flip-flop 505, 525 is the output signal of the D flip-flop 505 and is also the input signal of the and gate, 210 is the other input signal of the and gate, and 600 is the reset signal.
FIG. 6 is a waveform diagram of a current to frequency conversion circuit;
fig. 7 is a circuit diagram of an auxiliary comparator.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
The invention discloses a current frequency conversion circuit based on dual comparator control, which comprises an integrator 100, a main comparator 200, a ring oscillator 300, an auxiliary comparator 400, an RS latch 430, a D trigger 220, a D trigger 505, a NOT gate 520, an AND gate 530 and a reset switch.
Wherein the integrator 100 comprises an operational amplifier 105 and a feedback capacitor 110;
the ring oscillator 300 includes a MOS transistor 305 and an odd number of inverters 330-1-330-n connected end to end. The MOS transistors in the ring oscillator may be PMOS or NMOS, and the specific connection is shown in fig. 4, where the PMOS transistor is taken as an example.
The working structure of the whole current-frequency conversion circuit is shown in fig. 5, and the working process of the circuit can be divided into two stages: a charging phase and a discharging phase.
In the first stage charge phase, the current source 120 under test inputs current into the integrator 100. The integrator output voltage 130 is connected to the positive inputs of the main comparator 200 and the auxiliary comparator 400, respectively. The inverting input of the main comparator is connected to a reference potential 205 and the inverting input of the auxiliary comparator is connected to a reference potential 405. Reference voltage 205 is slightly smaller in magnitude than reference voltage 405. When the output voltage 130 of the integrator 100 continuously rises, the main comparator will flip before the auxiliary comparator, and the output voltage 210 of the main comparator 200 will flip from low level to high level, and 210 is connected to the clock input terminal of the D flip-flop 220 triggered by the rising edge, and the data input terminal of the flip-flop 220 is connected to high level. The toggling of the output voltage 210 of the main comparator 200 causes the inverted output signal 225 of the flip-flop 220 to toggle from a high level to a low level. Signal 225 is coupled to the gate of PMOS enable 305 of ring oscillator 300 so that PMOS enable 305 is turned on, ring oscillator 300 begins oscillating after a short attack time. The output signal 320 of the ring oscillator 300 is used as a clock input signal for the auxiliary comparator 400 to control the auxiliary comparator 400 to start operating. Since the integrator 100 output voltage 130 is now lower than the reference voltage 405 of the auxiliary comparator 400, the negative side output signal 415 of the auxiliary comparator 400 is a series of short pulse signals and the positive side output signal 410 of the auxiliary comparator 400 remains low. When the output voltage 130 of the integrator 100 rises to the reference voltage 405 of the auxiliary comparator 400, as shown at time t2 in fig. 6, the output signal 415 of the negative terminal of the auxiliary comparator 400 is at a low level, the output signal 410 of the positive terminal is at a high level, and since the signal 410 is connected to the set terminal of the RS latch, the output signal 435 of the positive terminal of the RS latch is inverted from the low level to the high level, the signal 435 is connected to the clock input terminal of the D flip-flop 505 triggered by the rising edge, and the data input terminal of the D flip-flop 505 is connected to the high level, so the forward output signal 525 of the DFF2 is inverted from the low level to the high level. Since 130 is already high, the post output signal 600 of 525 and 210 through the AND gate is high.
In the second stage, after the signal 600 is at a high level, the second stage is used to control the closing of the reset switch, so that the feedback capacitor 110 starts to discharge, and on the other hand, the signal 600 is input to the reset terminal of the flip-flop 220, so that the signal 225 output by the negative terminal of the flip-flop 220 is inverted from a low level to a high level. When the signal 225 goes high and the gate of the PMOS enable transistor 305 is connected, the PMOS enable transistor 305 is disconnected, the ring oscillator 300 stops oscillating and the output clock signal 320 remains low. Due to the closing of the reset switch, the output voltage 130 of the integrator drops sharply, and when the voltage 130 drops to the reference voltage 405 of the auxiliary comparator 400, i.e. at time t3 in fig. 6, since the ring oscillator 300 has stopped oscillating at this time, the auxiliary comparator 400 stops working and is in a reset state, so that both output signals 410 and 415 of the auxiliary comparator 400 are at a low level. The value of 435 remains high because the output signal 435 remains unchanged when both the set and reset terminals of the RS latch 430 are low. The output voltage 130 of the integrator 100 continues to drop and the main comparator 200 output signal 210 flips from high to low when 130 drops to the reference voltage 205 of the main comparator 200, i.e., at time t4 in fig. 6. Since 210 is connected to the input of the and gate 530, the output signal 600 of the and gate 530 is inverted from high to low, which causes the reset switch to be turned off, the discharging process is completed, and the whole signal cycle is completed. Meanwhile, 130 is inputted to the reset terminal of the D flip-flop 505 after passing through the inverter 520, which causes the output signal 525 of the D flip-flop 505 to be inverted from high level to low level. The reset operation of the D flip-flop 505 is necessary, otherwise, the output signal 525 is always high, and during the next charging process, due to the effect of the and gate 530, as long as the output signal 210 of the main comparator 200 is high, the output signal 600 of the and gate 530 will be inverted from low to high, which is not in accordance with the original design.
The main comparator 200 is designed as a continuous-time comparator, and as shown in fig. 3, the input stage adopts a basic transconductance amplifier structure, and the output stage adopts push-pull output.
The auxiliary comparator 400 is designed as a clocked dynamic comparator as shown in fig. 7. Wherein, M3 and M4, M5 and M6 respectively form inverters, and then two inverters are connected end to form a positive feedback latch structure, so as to improve the performance of the comparator. M7, M8, M tail Is a MOS tube controlled by a clock. When the clock signal CLK is at low level, the auxiliary comparator is in reset state, and output signals Voutp and Voutn are both at low level; the auxiliary comparator starts to operate when the clock signal CLK is high, and performs comparison.
A zero temperature coefficient current is generated by a bandgap reference circuit, and then the current is divided by a resistor to generate an input signal 205 of the main comparator 200 and an input signal 405 of the auxiliary comparator, and the control 205 is slightly smaller than 405, so that the main comparator is inverted before the auxiliary comparator.
The embodiments are only for illustrating the technical idea of the present invention, and the technical idea of the present invention is not limited thereto, and any modifications made on the basis of the technical scheme according to the technical idea of the present invention fall within the scope of the present invention.
Claims (7)
1. A current frequency conversion circuit based on dual comparator control is characterized by comprising an integrator, a reset switch, a main comparator, an auxiliary comparator, a first D trigger, a ring oscillator, an RS latch, a second D trigger, an AND gate and a NOT gate, wherein an external power supply to be tested is connected to the reverse input end of the integrator, the reverse input end of the integrator is connected to the output end of the integrator after being connected with the reset switch, the forward input end of the integrator is grounded, the output end of the integrator is connected to the forward input ends of the main comparator and the auxiliary comparator, the reverse input end of the main comparator is connected to a reference potential A, the reverse input end of the auxiliary comparator is connected to a reference potential B, and the output end of the main comparator is connected to the clock input end of the first D trigger, the input end of the NOT gate and the second input end of the AND gate, the output end of the first D trigger is connected with the input end of the ring oscillator, the output end of the ring oscillator is connected with the clock input end of the auxiliary comparator, the forward output end of the auxiliary comparator is connected with the S input end of the RS latch, the reverse output end of the auxiliary comparator is connected with the R input end of the RS latch, the output end of the RS latch is connected with the clock input end of the second D trigger, the output end of the NOT gate is connected with the reset end of the second D trigger, the forward output end of the second D trigger is connected with the first input end of the AND gate, and the output end of the AND gate is connected with the reset switch and is connected with the reset end of the first D trigger.
2. The dual comparator control-based current-to-frequency conversion circuit of claim 1, wherein the main comparator is a continuous-time comparator.
3. The dual comparator control-based current-to-frequency conversion circuit of claim 1, wherein the auxiliary comparator is a clocked dynamic comparator.
4. The circuit according to claim 1, wherein the reference potential A is smaller than the reference potential B.
5. The current-frequency conversion circuit based on the dual-comparator control as claimed in claim 1, wherein the ring oscillator includes a PMOS transistor and n inverters sequentially connected end to end, n is an odd number, the inverted output terminal of the first D flip-flop is connected to the gate of the PMOS transistor, the source of the PMOS transistor is connected to the power voltage, the drain of the field effect transistor is connected to the timing input terminal of each inverter, and the output terminal of the nth inverter is connected to the clock input terminal of the auxiliary comparator.
6. The current-frequency conversion circuit based on the dual-comparator control as claimed in claim 1, wherein the ring oscillator includes an NMOS transistor and n inverters sequentially connected end to end, n is an odd number, the forward output terminal of the first D flip-flop is connected to the gate of the NMOS transistor, the source of the NMOS transistor is grounded, the drain of the NMOS transistor is connected to the timing input terminal of each inverter, and the output terminal of the nth inverter is connected to the clock input terminal of the auxiliary comparator.
7. The method for converting current frequency of the current frequency conversion circuit based on the dual comparator control as claimed in any one of claims 1 to 6, comprising:
(1) the current source to be measured flows into the integrator, and the voltage of the output end of the integrator is gradually increased;
(2) in the process that the voltage of the output end of the integrator is gradually increased, when the voltage of the output end of the integrator is higher than a reference potential A, the main comparator starts to turn over, the ring oscillator is controlled by the first D trigger to generate a clock signal, the ring oscillator sends a trigger signal to the auxiliary comparator, and the auxiliary comparator starts to operate after receiving the trigger signal;
(3) when a signal at the positive input end of the auxiliary comparator is higher than a reference potential B, the output of the auxiliary comparator is overturned, and an RS latch is triggered to output and overturn;
(4) the switching of the output of the RS latch triggers the conduction of a reset switch by controlling a second D trigger and an AND gate, a feedback capacitor in the integrator discharges, and the output voltage of the integrator drops; meanwhile, an AND gate output signal controls the ring oscillator to stop oscillating through the first D trigger, and the auxiliary comparator stops working;
(5) when the output voltage of the integrator is reduced to the reference potential A, the output of the main comparator is inverted, and the reset switch is disconnected through the AND gate; and starting a new round of charge and discharge process.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114665879A (en) * | 2022-04-14 | 2022-06-24 | 南京邮电大学 | Current-frequency conversion circuit and working method thereof |
| CN116527019A (en) * | 2023-07-03 | 2023-08-01 | 成都芯翼科技有限公司 | On-chip oscillator circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114665879A (en) * | 2022-04-14 | 2022-06-24 | 南京邮电大学 | Current-frequency conversion circuit and working method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114665879A (en) * | 2022-04-14 | 2022-06-24 | 南京邮电大学 | Current-frequency conversion circuit and working method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114665879A (en) * | 2022-04-14 | 2022-06-24 | 南京邮电大学 | Current-frequency conversion circuit and working method thereof |
| CN114665879B (en) * | 2022-04-14 | 2024-06-07 | 南京邮电大学 | Current-frequency conversion circuit and working method thereof |
| CN116527019A (en) * | 2023-07-03 | 2023-08-01 | 成都芯翼科技有限公司 | On-chip oscillator circuit |
| CN116527019B (en) * | 2023-07-03 | 2023-12-05 | 成都芯翼科技有限公司 | On-chip oscillator circuit |
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