CN220603633U

CN220603633U - Chip testing machine and chip testing system

Info

Publication number: CN220603633U
Application number: CN202321460623.8U
Authority: CN
Inventors: 王晓斌; 马彦斌; 李鑫; 王亮; 朱旋虎
Original assignee: Hangzhou Changchuan Technology Co Ltd
Current assignee: Hangzhou Changchuan Technology Co Ltd
Priority date: 2023-06-08
Filing date: 2023-06-08
Publication date: 2024-03-15
Anticipated expiration: 2033-06-08

Abstract

The application relates to the field of semiconductor automation testing, in particular to a chip testing machine and a chip testing system, wherein the chip testing machine comprises an upper computer and a plurality of testing heads, each testing head is connected to a universal meter, the universal meter is connected with the upper computer, and the upper computer comprises: the controller comprises a plurality of first communication ports which are respectively connected with the second communication ports of the test heads and used for controlling the corresponding test heads to output calibration signals to the universal meter through the first communication ports; the controller is also connected with the universal meter to acquire measurement signals of the universal meter on each calibration signal; and the processor is connected with the universal meter and the controller and is used for acquiring the measurement signals so as to calibrate the test heads. According to the utility model, the test heads can be calibrated by only one universal meter, so that the wiring is simpler, the utilization rate of peripheral resources and the calibration efficiency are improved, and the calibration cost is reduced.

Description

Chip testing machine and chip testing system

Technical Field

The present disclosure relates to the field of automated semiconductor testing, and more particularly, to a chip tester and a chip testing system.

Background

The chip tester comprises an upper computer and a plurality of test heads, and test signals of the test heads are obtained through the upper computer so as to test the chip to be tested.

Before the chip tester tests the chip to be tested, calibration needs to be performed on each test head. In the prior art, each test head is respectively connected with a universal meter, and an upper computer is connected with a plurality of universal meters to acquire calibration signals of each universal meter so as to calibrate each test head. The calibration mode of the test head is complex in wiring, and the utilization rate of peripheral resources is low, so that the calibration cost of the test machine is high.

Disclosure of Invention

Accordingly, it is desirable to provide a chip tester and a chip testing system for solving the above-mentioned problems.

In a first aspect, an embodiment of the present utility model provides a chip testing machine, including an upper computer and a plurality of test heads, each of the test heads is connected to a multimeter, and the multimeter is connected to the upper computer, where the upper computer includes:

the controller comprises a plurality of first communication ports which are respectively connected with the second communication ports of the test heads and used for controlling the corresponding test heads to output calibration signals to the universal meter through the first communication ports; the controller is also connected with the universal meter to acquire measurement signals of the universal meter on each calibration signal;

and the processor is connected with the universal meter and the controller and is used for acquiring the measurement signals so as to calibrate the test heads.

In one embodiment, the processor comprises:

a plurality of third communication ports respectively connected with the fourth communication ports of the test heads;

and the processor acquires test signals of the test heads through the third communication ports so as to test a plurality of chips to be tested.

In an embodiment, the third communication port and the fourth communication port communicate through a GPRC network or an ethernet network.

In one embodiment, the chip tester further comprises:

the controllable switches are respectively connected between each test head and the universal meter;

the controller controls the on or off of each controllable switch so as to control the connection between each test head and the universal meter.

In an embodiment, the upper computer further includes:

the communication board card is connected with the universal meter and the controller;

the controller controls the communication between the communication board card and the universal meter, and obtains the measurement signal of the universal meter through the communication board card and transmits the measurement signal to the processor.

In an embodiment, the communication board card includes a plurality of external ports respectively connected with the multimeter, the sorter and the plurality of probe stations.

In one embodiment, the communication board is a GPIB communication board.

In an embodiment, each test head includes a test carrier board and a plurality of test cards inserted into the test carrier board, and the test carrier board is connected to the fourth communication port.

In a second aspect, an embodiment of the present utility model provides a chip testing system, including the chip testing machine according to the first aspect and a multimeter connected to the chip testing machine.

In an embodiment, the chip testing system further comprises a sorter and a plurality of probe stations, the chip testing machine comprises a plurality of external ports, and the plurality of external ports are connected with the multimeter, the sorter and the plurality of probe stations.

Compared with the prior art, the technical scheme has the following technical effects:

1. the controller is provided with a plurality of first communication ports, and the plurality of test heads are connected in parallel through the second communication ports of the test heads. The controller controls each test head to output a calibration signal to the universal meter through the first communication port so as to obtain each measurement signal measured by the universal meter. The processor acquires each measurement signal to calibrate each test head. Compared with the prior art, in the technical scheme, the test heads can be calibrated only by one universal meter, and the calibration cost is reduced. As only one multimeter is adopted, the wiring is simpler, the utilization rate of peripheral resources is improved, the calibration cost is reduced, and the calibration efficiency is improved.

2. The communication board card comprises a plurality of external ports, can interact with the universal meter, the sorting machine and the probe stations, and can realize the testing work of the chips to be tested in various scenes.

Drawings

FIG. 1 is a schematic diagram illustrating connection of a chip tester according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram illustrating connection of a chip tester according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram illustrating connection of a chip tester according to an embodiment of the present utility model;

FIG. 4 is a schematic diagram illustrating connection of a chip tester according to an embodiment of the present utility model;

fig. 5 is a schematic connection diagram of a chip test system according to an embodiment of the utility model.

1, a chip testing machine; 10. an upper computer; 101. a controller; 1011. a first communication port; 102. a processor; 1021. a third communication port; 103. a communication board card; 1031. an external port; 20. a test head; 201. a second communication port; 202. a fourth communication port; 30. a controllable switch; 2. a multimeter; 3. a separator; 4. a probe station.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is possible for those of ordinary skill in the art to apply the present application to other similar situations according to these drawings without inventive effort. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the embodiments described herein can be combined with other embodiments without conflict.

Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar terms herein do not denote a limitation of quantity, but rather denote the singular or plural. The terms "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein refers to two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The terms "first," "second," "third," and the like, as used herein, are merely distinguishing between similar objects and not representing a particular ordering of objects.

As shown in fig. 1, the present embodiment provides a chip tester 1, which includes a host computer 10 and a plurality of test heads 20, wherein each test head 20 is connected to a multimeter 2, the multimeter 2 is connected to the host computer 10, and the host computer 10 includes: the controller 101 includes a plurality of first communication ports 1011, respectively connected to the second communication ports 201 of the test heads 20, for controlling the corresponding test heads 20 to output calibration signals to the multimeter 2 through the respective first communication ports 1011; the controller 101 is also connected with the universal meter 2 to acquire measurement signals of the universal meter 2 for each calibration signal; processor 102, coupled to multimeter 2 and to controller 101, is configured to obtain measurement signals for calibrating test heads 20.

In the present embodiment, the controller 101 is provided with a plurality of first communication ports 1011, and a plurality of test heads 20 are connected in parallel through the second communication ports 201 of the respective test heads 20. The controller 101 controls each test head 20 to output a calibration signal to the multimeter 2 through the first communication port 1011 to obtain each measurement signal measured by the multimeter 2. Processor 102 obtains measurement signals to calibrate each test head 20. Compared with the prior art, in the technical scheme, the test heads can be calibrated only by one universal meter, and the calibration cost is reduced. As only one multimeter is adopted, the wiring is simpler, the utilization rate of peripheral resources is improved, the calibration cost is reduced, and the calibration efficiency is improved.

It should be noted that, it is prior art that the controller 101 controls each test head 20 to output a calibration signal to the multimeter 2 through the first communication port 1011. For example, the controller 101 sequentially transmits a control instruction for controlling the test heads 20 to output a calibration signal to each of the test heads 20 through the first communication port 1011.

It should be further noted that it is also known in the art that the processor 102 obtains each measurement signal to calibrate each test head 20. For example, after acquiring each measurement signal, the processor 102 compares the measurement signal with a standard signal to obtain a calibration value of each test head 20, so as to calibrate each test head 20.

In one embodiment, as shown in FIG. 2, the processor 102 includes: the plurality of third communication ports 1021 are connected to the fourth communication ports 202 of the respective test heads 20. The processor 102 obtains the test signals of each test head 20 through each third communication port 1021 to test a plurality of chips to be tested.

In this embodiment, the processor 102 is connected in parallel with the plurality of test heads 20, so as to test a plurality of chips under test simultaneously by acquiring the test signals of each test head 20, thereby improving the test efficiency of the chips under test.

Specifically, communication between the third communication port 1021 and the fourth communication port 202 is implemented through a GPRC network, an ethernet network, or other networks.

Specifically, each test head 20 includes a test carrier board and a plurality of test cards inserted into the test carrier board, and the test carrier board is connected to the fourth communication port 202. Each test card sequentially outputs corresponding test signals to the processor 102 through the fourth communication port 202; the test carrier may be a backing plate.

As an example, the test cards may include, but are not limited to, a main control board card and a service board card, including, but not limited to, a digital board card, a power board card, a radio frequency board card, or an analog hybrid board card, among others.

In one embodiment, as shown in fig. 3, the chip tester 1 further includes: a plurality of controllable switches 30 respectively connected between each test head 20 and multimeter 2; controller 101 controls the turning on or off of each controllable switch 30 to control the connection of each test head 20 to multimeter 2.

When the test head 20 needs to be calibrated, the controller 101 controls the corresponding controllable switch 30 to be turned on, and after the calibration of the test head 20 is completed, the controller 101 controls the corresponding controllable switch 30 to be turned off, so as to avoid electric leakage of the test head 20 and ensure the safety of the chip tester 1. Next, after the switch is turned on, the test head 20 applies for the use condition of a certain peripheral to the controller 101, and after obtaining the use right, an operation command can be initiated to the external devices such as the multimeter 2, the sorter 3, and the plurality of probe stations 4 to complete the test work.

The controllable switch 30 is, for example, a controllable switch 30 element such as a MOS transistor, a triode, a relay, etc.

In one embodiment, as shown in fig. 4, the upper computer 10 further includes: a communication board 103 connected to the multimeter 2 and the controller 101; the controller 101 controls communication between the communication board 103 and the multimeter 2, and obtains measurement signals of the multimeter 2 through the communication board 103 and transmits the measurement signals to the processor 102.

As an example, the communication board 103 is, for example, a GPIB communication board 103.

Further, the communication board 103 includes a plurality of external ports 1031, which are respectively connected to the multimeter 2, the sorter 3, and the plurality of probe stations 4.

The sorter 3 is used for automatically transmitting the chips to be tested to the testing station one by one, and the chip tester 1 applies testing signals to the chips to be tested and collects feedback signals to judge whether the functions and performances of the chips to be tested meet the design specification requirements. The test results are transmitted to the sorter 3 through the communication board 103, and the sorter 3 marks, sorts, receives or braids the chips to be tested accordingly.

The probe station 4 is used for automatically conveying the chip to be tested to a testing position, and is connected with the chip testing machine 1 through a probe and a special connecting wire, the chip testing machine 1 applies a testing signal to the chip to be tested and collects a feedback signal, and whether the function and the performance of the chip to be tested meet the design specification requirements is judged. The test results are transmitted to the probe station 4 through the communication board 103, and the probe station 4 marks the chip to be tested according to the test results.

Because the communication board card 103 in the embodiment includes a plurality of external ports 1031, interaction with the multimeter 2, the sorter 3 and the plurality of probe platforms 4 can be realized, and testing work of a plurality of chips to be tested under various scenes can be realized.

The embodiment of the utility model also provides a testing system, as shown in fig. 5, which comprises the chip testing machine 1 and the universal meter 2 connected with the chip testing machine 1.

Further, the chip testing system further comprises a sorter 3 and a plurality of probe platforms 4, the chip testing machine 1 comprises a plurality of external ports 1031, and the external ports 1031 are connected with the multimeter 2, the sorter 3 and the probe platforms 4.

It should be noted that, the chip tester 1 has been described in detail in the above embodiments, and thus, the description thereof is omitted in this embodiment. Since the test system includes the chip tester 1 in the above-described embodiment, the same technical effects are obtained.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. The utility model provides a chip testing machine which characterized in that, includes host computer and a plurality of test head, each test head is connected to the universal meter, the universal meter with the host computer is connected, wherein, the host computer includes:

2. The chip tester of claim 1, wherein the processor comprises:

3. The chip tester according to claim 2, wherein the third communication port and the fourth communication port communicate with each other through a GPRC network or an ethernet network.

4. The chip tester according to claim 1, further comprising:

5. The chip tester according to claim 1, wherein the host computer further comprises:

6. The chip tester according to claim 5, wherein the communication board includes a plurality of external ports respectively connected to the multimeter, the sorter, and the plurality of probe stations.

7. The chip tester according to claim 6, wherein the communication board is a GPIB communication board.

8. The chip tester according to claim 2, wherein each of the test heads includes a test carrier and a plurality of test cards inserted into the test carrier, the test carrier being connected to the fourth communication port.

9. A chip testing system comprising a chip tester according to any one of claims 1-8 and a multimeter connected to the chip tester.

10. The chip testing system of claim 9, further comprising a sorter and a plurality of probe stations, the chip tester comprising a plurality of external ports, the plurality of external ports being connected to the multimeter, the sorter, and the plurality of probe stations.