CN220510994U - DC bus voltage self-balancing circuit of three-level power module - Google Patents
DC bus voltage self-balancing circuit of three-level power module Download PDFInfo
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- CN220510994U CN220510994U CN202321864125.XU CN202321864125U CN220510994U CN 220510994 U CN220510994 U CN 220510994U CN 202321864125 U CN202321864125 U CN 202321864125U CN 220510994 U CN220510994 U CN 220510994U
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Abstract
The utility model provides a direct current bus voltage self-balancing circuit of a three-level power module, which aims to solve the problem that the existing three-level midpoint voltage balance control technology has defects. The circuit comprises a direct current bus circuit and a hysteresis circuit, wherein the direct current bus circuit is connected with the hysteresis circuit, and the direct current bus circuit and the hysteresis circuit are both connected with a bus voltage source. The control mode is as follows: the values of R3, R4 and R5 are set to determine the voltage of V-A, V-B, the midpoint potential (V Neutral) is higher than V-A (C2 voltage is high), Q2 is conducted, the midpoint potential (V Neutral) is lower than V-B (C1 voltage is high), and Q1 is conducted. The corresponding level of the triode output of the three-level bridge is controlled to be conducted and closed, the current of the parallel branch of the capacitor is dynamically changed, the voltage balance of the direct current bus of the three-level power module is realized, and the purpose of self-balancing of the bus capacitor voltage with different voltage resistance capacities is achieved by changing the size of the average piezoresistance value.
Description
Technical Field
The utility model relates to the field of converters, in particular to a direct current bus voltage self-balancing circuit of a three-level power module.
Background
The three-level converter generates three levels by connecting two capacitors in series on a direct current bus, and the problem of uneven voltage division of the two capacitors, namely the problem of midpoint balance, can be generated due to the inconsistency of the characteristics of the switching devices and the participation of midpoint potential in energy transmission during energy conversion of the converter. The neutral point voltage imbalance of the direct current bus greatly affects the operation of the three-level converter.
If the neutral point potential is unbalanced, low-order harmonic waves are generated at the alternating current output end, so that the output efficiency of the converter is low, and meanwhile, the harmonic waves can generate pulsating torque to the motor, so that the speed regulation performance of the motor is affected;
in addition, the voltage born by certain switching tubes of the current transformer is increased, and the reliability of the system is reduced.
The current method for solving the problem of neutral point voltage balance of the bus of the three-level converter is generally divided into two main types: hardware add balancing circuit processing and software algorithm processing.
The software algorithm is widely used, and the existing software algorithm comprises a small vector adjustment method in space vector modulation and a zero sequence voltage injection method.
The bus voltage balance effect of the software algorithm processing on the three-level converter with low power factor output is poor, the application range is small, and the software algorithm processing cannot be applied to all three-level converters.
Therefore, the utility model provides a direct current bus self-balancing circuit of a three-level module for adjusting a hysteresis zone through a voltage equalizing resistor, so as to solve the circuit balancing problem.
Disclosure of Invention
In order to solve the defect of the existing three-level neutral point voltage balance control technology, a direct current bus voltage self-balancing circuit of a three-level power module is provided.
The technical problems of the utility model are mainly solved by the following technical proposal: the direct current bus voltage self-balancing circuit comprises a direct current bus circuit and a hysteresis circuit, wherein the direct current bus circuit is connected with the hysteresis circuit, both the direct current bus circuit and the hysteresis circuit are connected with a bus voltage source, and the circuit comprises a positive bus voltage source DC-P, a negative bus voltage source DC-N, a positive bus capacitor C1, a positive bus capacitor C2, a triode Q1, a triode Q2, current limiting resistors R1 and R2 and equalizing resistors R3, R4 and R5. When the two ends of the two bus capacitors are not balanced, the self-balancing circuit enters a working state. The average current injected into the middle point of the bus is changed through a hysteresis circuit formed by the middle point of the capacitor, the triode Q1, the triode Q2 and the resistor, and the voltage difference of two sides of the capacitor is regulated.
Further, the direct current bus circuit comprises a positive bus capacitor C1 and a positive bus capacitor C2, wherein the positive electrode of the positive bus capacitor C1 is connected with the collector of the triode Q1 and the positive bus voltage source DC-P, the negative electrode of the positive bus capacitor C1 is connected with the positive electrode of the positive bus capacitor C2 in series and is connected between the positive bus voltage source DC-P and the negative bus voltage source DC-N, and the negative electrode of the positive bus capacitor C2 is connected with the collector of the triode Q2 and the negative bus voltage source DC-N. When the direct current bus voltage self-balancing circuit works, the two bus capacitors are charged and discharged. When the two ends of the two bus capacitors are not balanced, the self-balancing circuit enters a working state.
Further, the hysteresis circuit comprises a current-limiting resistor R1, a voltage-sharing resistor R3, a voltage-sharing resistor R4, a voltage-sharing resistor R5, a current-limiting resistor R2, a triode Q2 and a triode Q1, wherein one end of the current-limiting resistor R1 is connected with a collector of the triode Q1, the other end of the R1 is connected with the voltage-sharing resistor R3, one end of the current-limiting resistor R2 is connected with a collector of the triode Q2, the other end of the R2 is connected with the voltage-sharing resistor R5, one end of the R3 is connected with one end of the R3, the other end of the R3 is respectively connected with one end of the Q2 and one end of the R4, the other end of the R4 is respectively connected with one end of the Q1 and one end of the R5, one end of the C2 and a negative bus power DC-N, the Q2, the R4 and the R5, the current flow of the midpoint voltage booster circuit passes through the R1, the R3, the R4 and the Q1, and the current flow of the midpoint voltage booster circuit passes through the Q2, the R4, the R5 and the R2.
Further, the direct current bus circuit is connected in parallel with the hysteresis circuit, R1 and Q1 in the hysteresis circuit are connected in parallel with a positive bus capacitor C1 in the direct current bus circuit, and Q2 and R2 in the hysteresis circuit are connected in parallel with a positive bus capacitor C2 in the direct current bus circuit, and the hysteresis circuit is used for adjusting voltages on two sides of the positive bus capacitor so that the bus capacitor voltage reaches balance.
Further, the hysteresis circuit triode Q1 is an NPN triode, the triode Q2 is a PNP triode, when the hysteresis circuit works, current in the Q1 flows from a base to an emitter, or current in the Q2 flows from the base to the emitter, so that the midpoint voltage of the bus capacitor is changed.
Further, the emitters of the triode Q1 and the triode Q2 are connected with the positive bus capacitor C1 and the positive bus capacitor C2, wherein voltages V Neutral between the positive bus capacitor C1 and the positive bus capacitor C2, voltages V-A between the positive bus capacitor R3 and the negative bus capacitor R4 and voltages V-B between the positive bus capacitor R4 and the negative bus capacitor R5 are respectively set. The midpoint potential (V Neutral) is higher than V-A (C2 voltage is high), the triode Q2 is conducted, the midpoint potential (V Neutral) is lowered, the midpoint potential (V Neutral) is lower than V-B (C1 voltage is high), the triode Q1 is conducted, and the midpoint potential (V Neutral) is raised.
The corresponding level of the triode output of the three-level bridge is controlled to be conducted and closed, the current of the parallel branch of the capacitor is dynamically changed, the voltage balance of the direct current bus of the three-level power module is realized, and the purpose of bus self-balancing is achieved.
The technical scheme provided by the utility model has the beneficial effects that:
the novel circuit that draws of this experiment exists a hysteresis interval, only does not even voltage to a certain extent triode just can switch on when the generating line. The hysteresis interval can be freely set through R3, R4 and R5, the interval can be adjusted, the hysteresis interval can be set according to the voltage withstand capability of the capacitor, and the loss is greatly reduced.
The circuit is applicable to three-level power modules, has no limitation on the power factor of the three-level power modules, and has good popularization and application prospects.
Drawings
Fig. 1 is a topology diagram of a three-level converter of a dc bus voltage self-balancing circuit of a three-level power module according to the present utility model.
Fig. 2 is a BUS circuit BUS1 of a dc BUS voltage self-balancing circuit of a three-level power module according to the present utility model.
FIG. 3 shows a voltage equalizing resistance hysteresis circuit BUS2 connected with a DC BUS voltage self-balancing circuit of a three-level power module.
Fig. 4 is a voltage equalizing resistance hysteresis circuit BUS3 connected with a dc BUS voltage self-balancing circuit of a three-level power module according to the present utility model.
Fig. 5 is a voltage waveform diagram of a dc bus voltage self-balancing circuit of a three-level power module according to the present utility model.
Detailed Description
The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model.
The embodiment provides a bus voltage self-balancing circuit, which comprises a bus circuit and a hysteresis circuit. In a topological diagram of the current transformer, as shown in fig. 1, a bus circuit is composed of a positive bus voltage source DC-P, a negative bus voltage source DC-N, a positive bus capacitor C1 and a positive bus capacitor C2, and when the direct current bus capacitor works, the condition that voltages at two ends of the capacitor C1 and the capacitor C2 are uneven due to different charging and discharging efficiencies is generated, and at the moment, the direct current bus capacitor needs to be regulated by a hysteresis circuit with an inverter bridge.
The hysteresis circuit comprises a current-limiting resistor R1, a voltage-sharing resistor R3, a voltage-sharing resistor R4, a voltage-sharing resistor R5, a current-limiting resistor R2, a triode Q2 and a triode Q1, wherein one end of the current-limiting resistor R1 is connected with a collector of the triode Q1, the other end of the current-limiting resistor R1 is connected with the voltage-sharing resistor R3, one end of the current-limiting resistor R2 is connected with a collector of the triode Q2, the other end of the current-limiting resistor R2 is connected with the voltage-sharing resistor R5, the other end of the voltage-sharing resistor R3 is respectively connected with a base of the triode Q2 and one end of the voltage-sharing resistor R4, the other end of the voltage-sharing resistor R4 is respectively connected with a base of the Q1, one end of the voltage-sharing resistor R5, and the other end of the voltage-sharing resistor R5 is respectively connected with the other end of the current-limiting resistor R2, a negative electrode of a bus capacitor C2 and a negative bus power supply DC-N. The hysteresis circuit can compare the magnitude relation between the voltage V-A between the resistor R3 and the resistor R4 and the midpoint voltage V Neutral of the capacitor, when VN Neutral is larger than the voltage V-A, current flows through the triode Q2 from the midpoint 3 to the point V-A, the voltage at the point V-A is reduced, and the voltage at the point V-A is improved; similarly, the voltage V-B between the resistor R4 and the resistor R5 can be compared with the voltage V Neutral at the midpoint of the capacitor, when the voltage V Neutral is smaller than the voltage V-B, current flows through the triode Q1 from the point V-B to the midpoint 3, the voltage at the point V Neutral is increased, and the voltage at the point V-A is reduced.
By controlling the conduction relation of triodes in the three-level circuit, the effect of adjusting the capacitor voltage and realizing quick voltage equalizing is achieved.
In order to intuitively feel the voltage equalizing effect of the bus voltage self-balancing circuit, the self-equalizing effect of the circuit and the effect after adding the hysteresis circuit are described through a second embodiment, and the voltage equalizing effect is observed.
When the voltage equalizing means is not adopted, the circuit is self-equalized by the capacitor, and the circuit diagram is shown in figure 2.
When the bus voltage self-balancing circuit provided by the technology is adopted, the voltage equalizing regulating resistor is 8K, the circuit diagram is shown in fig. 3, the resistors R8, R9 and R11 are connected in series between the collector and the base of the triode Q3, the resistors R11, R13 and R14 are connected in series between the collector and the base of the triode Q4, the triode Q3 is connected with the emitting electrode of the triode Q4, the midpoint is connected with the midpoint connection part of the bus capacitor C3 and the bus capacitor C4, the conducting state of the triode Q3 and the triode Q4 is judged according to the midpoint voltage, and then the upper bus voltage and the lower bus voltage are regulated.
When the bus voltage self-balancing circuit provided by the technology is adopted, the voltage equalizing regulating resistor is 1K, the circuit diagram is shown in fig. 4, the resistors R8, R9 and R11 are connected in series between the collector and the base of the triode Q3, the resistors R11, R13 and R14 are connected in series between the collector and the base of the triode Q4, the triode Q3 is connected with the emitting electrode of the triode Q4, the midpoint is connected with the midpoint connection part of the bus capacitor C3 and the bus capacitor C4, the conducting state of the triode Q3 and the triode Q4 is judged according to the midpoint voltage, and then the upper bus voltage and the lower bus voltage are regulated.
After the circuit voltage is subjected to disturbance treatment, the BUS1 does not adopt a voltage equalizing means and uses a capacitor to automatically equalize voltage, the waveforms of the upper BUS voltage and the lower BUS voltage are shown as the BUS1 waveform in the figure 5, the positive BUS voltage and the negative BUS voltage are greatly different, and the unequal voltage degree is high;
the BUS2 adopts the voltage equalizing means described in the patent, the voltage equalizing regulating resistor adopts 8K, the voltages of an upper BUS and a lower BUS are shown in the waveform of the BUS2 in fig. 5, the voltage difference between the positive BUS and the negative BUS is reduced, and the voltage equalizing trend is realized;
the BUS3 adopts the voltage equalizing means described in the patent, the voltage equalizing regulating resistor selects 1K, the upper BUS and the lower BUS are used for voltage equalizing, the voltage difference between the positive BUS and the negative BUS is smaller, the voltage equalizing trend is realized, and the purpose of equalizing voltage is achieved.
In this embodiment, the resistance of the equalizing resistor may be set according to the withstand voltage capability of the capacitor, and when the voltage between the equalizing resistors R3 and R4 is lower than the midpoint potential of the capacitor, the triode Q2 is turned on, and the current flows from between C1 and C2 to the V-Sup>A point, and the midpoint potential is reduced; when the voltage between the equalizing resistors R4 and R5 is higher than the midpoint potential, current flows from the V-B point to the C1 and C2, the midpoint potential rises, and the interval of the hysteresis circuit is adjusted, so that the equalizing performance of the circuit is improved, and the loss is greatly reduced.
It will be apparent that the described embodiments are only some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
Claims (6)
1. The direct current bus voltage self-balancing circuit of the three-level power module is characterized by comprising a direct current bus circuit and a hysteresis circuit, wherein the direct current bus circuit is connected with the hysteresis circuit, and the direct current bus circuit and the hysteresis circuit are both connected with a bus voltage source.
2. The direct current bus voltage self-balancing circuit of the three-level power module according to claim 1, wherein the direct current bus circuit comprises a positive bus capacitor C1 and a positive bus capacitor C2, the positive electrode of the positive bus capacitor C1 is connected with the collector of the triode Q1 and a positive bus voltage source DC-P, the negative electrode of the positive bus capacitor C1 is connected with the positive electrode of the positive bus capacitor C2 in series and is connected between the positive bus voltage source DC-P and a negative bus voltage source DC-N, and the negative electrode of the positive bus capacitor C2 is connected with the collector of the triode Q2 and the negative bus voltage source DC-N.
3. The self-balancing circuit for DC bus voltage of three-level power module according to claim 1, wherein the hysteresis circuit comprises a current limiting resistor R1, a voltage equalizing resistor R3, a voltage equalizing resistor R4, a voltage equalizing resistor R5, a current limiting resistor R2, a triode Q2 and a triode Q1, one end of the current limiting resistor R1 is connected with a collector of the triode Q1, the other end of the current limiting resistor R1 is connected with the voltage equalizing resistor R3, one end of the current limiting resistor R2 is connected with a collector of the triode Q2, the other end of the current limiting resistor R2 is connected with the voltage equalizing resistor R5, one end of the voltage equalizing resistor R3 is connected with the other end of the current limiting resistor R1, the other end of the voltage equalizing resistor R3 is respectively connected with a base of the triode Q2 and one end of the voltage equalizing resistor R4, the other end of the voltage equalizing resistor R5 is respectively connected with the other end of the current limiting resistor R2, the negative electrode of the busbar capacitor C2 and the negative busbar power DC-N.
4. A dc bus voltage self-balancing circuit of a three-level power module according to claim 2 or 3, wherein the dc bus circuit is connected in parallel with a hysteresis circuit, R1 and Q1 in the hysteresis circuit are connected in parallel with a positive bus capacitor C1 in the dc bus circuit, and Q2 and R2 in the hysteresis circuit are connected in parallel with a positive bus capacitor C2 in the dc bus circuit.
5. A dc bus voltage self-balancing circuit of a three-level power module according to claim 1 or 3, wherein said hysteresis circuit transistor Q1 is an NPN transistor and said transistor Q2 is a PNP transistor.
6. The dc bus voltage self-balancing circuit of a three-level power module according to claim 2, wherein the emitters of the transistor Q1 and the transistor Q2 are connected to the positive bus capacitor C1 and the positive bus capacitor C2.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321864125.XU CN220510994U (en) | 2023-07-14 | 2023-07-14 | DC bus voltage self-balancing circuit of three-level power module |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321864125.XU CN220510994U (en) | 2023-07-14 | 2023-07-14 | DC bus voltage self-balancing circuit of three-level power module |
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