CN220509314U

CN220509314U - Reliable switch circuit of economical interconnected riding instrument

Info

Publication number: CN220509314U
Application number: CN202321976116.XU
Authority: CN
Inventors: 刘少华; 陶俊杰; 叶磊
Original assignee: Wuhan Bluestar Technology Co Ltd
Current assignee: Wuhan Bluestar Technology Co Ltd
Priority date: 2023-07-25
Filing date: 2023-07-25
Publication date: 2024-02-20
Anticipated expiration: 2033-07-25

Abstract

The utility model relates to a reliable on-off circuit of an economical interconnected riding instrument, which comprises the following components: the system comprises a power supply control integrated logic circuit, an ACC power-on control circuit, a system processor SOC and ACC power-off holding circuit and a key long-press time delay multiplexing control circuit; the power supply control integrated logic circuit comprises three input ends and an output end, wherein the three input ends are respectively and electrically connected with the output ends of the ACC power-on control circuit, the system processor SOC, the ACC power-off holding circuit and the key long-press time delay multiplexing control circuit; the output end of the power control integrated logic circuit is electrically connected with the instrument power enabling end. The ACC power-on and power-off maintenance, delayed data storage and shutdown and long-time key-press reset restarting are realized through the power control integrated logic circuit. The utility model eliminates the mode of realizing the on-off logic of the special controller, realizes normal ACC power-on and power-off, meets the system time sequence, and has a simpler control mode under the condition of effectively storing the system data.

Description

Reliable switch circuit of economical interconnected riding instrument

Technical Field

The utility model relates to the technical field of electronic circuits, in particular to a reliable switching circuit of an economical interconnected riding instrument.

Background

Compared with the traditional combination instrument or mechanical instrument, the interconnected video riding liquid crystal instrument has the advantages that besides basic automobile body signal processing and display, more interconnected and other relevant data with expanded functions are required to be stored and processed, such as recorded audio and video data. Because of the additional data storage requirement, besides the basic working voltage range requirement, the requirement of complete data storage and proper control of time sequence is also met when the vehicle is started and shut down, the conventional processing mode is to adopt a double-processor structure, namely, one MCU processes the vehicle body signal and simultaneously gives consideration to power control to realize the starting and shutting down logic, and the other system processor SOC runs an operating system to realize the functions of system resource management, interconnection and the like. Voltage range control relies on a controller (MCU) to detect body voltage through AD sampling to determine if the system is operating. On one hand, whether the current voltage of the system exceeds the normal range or not is detected, the power supply and the controller can be in an over-voltage working state, and the over-voltage working risk exists; on the other hand, the system cost is increased obviously by realizing the power logic by specially adopting an MCU controller.

Disclosure of Invention

Aiming at the technical problems existing in the prior art, the utility model provides a reliable on-off circuit of an economical interconnected riding instrument, and in the economical interconnected instrument with only a system processor, the reliable on-off logic of a system is realized through hardware circuit design.

The technical scheme for solving the technical problems is as follows: a reliable on-off circuit of an economical interconnected riding meter, comprising: the system comprises a power supply control integrated logic circuit, an ACC power-on control circuit, a system processor SOC and ACC power-off holding circuit and a key long-press time delay multiplexing control circuit;

the power supply control integrated logic circuit comprises three input ends and an output end, wherein the three input ends are respectively and electrically connected with the output ends of the ACC power-on control circuit, the system processor SOC, the ACC power-off holding circuit and the key long-press time delay multiplexing control circuit; the output end of the power control integrated logic circuit is electrically connected with the instrument power enabling end;

the power supply control integrated logic circuit is composed of diodes D5, D6 and D7 and resistors R9, R10, R11 and R12, wherein: the anode of the diode D5 is used as one input end of the power supply control integrated logic circuit and is connected with the output ends of the system processor SOC and the ACC power failure holding circuit, and the cathode of the diode D5 is connected with one end of the resistor R10; the anode of the diode D6 is used as one input end of the power supply control integrated logic circuit to be connected with the output end of the ACC power-on control circuit, and the cathode of the diode D6 is connected with one end of the resistor R11; the cathode of the diode D7 is used as one input end of the power supply control integrated logic circuit and is connected with the output end of the key long-press time delay multiplexing control circuit, and the anode of the diode D7 is connected with one end of the resistor R12; the other ends of the resistors R10, R11 and R12 are connected together and then connected to the power supply enabling end of the instrument, and the resistor R9 is used as a common node of the pull-down resistor connected with the resistors R10, R11 and R12; the three diodes D5, D6 and D7 form a logical operation of 'early or late AND', so that the enabling control of the system power supply is realized.

Further, the ACC power-on control circuit comprises a working range lower limit voltage detection circuit, a working range upper limit voltage detection circuit and a working range limiting logic circuit, wherein,

the operating range defining logic circuit includes: NMOS transistors Q4, Q5, diodes D3, D4; the source electrode of the NMOS tube Q4 is electrically connected with the drain electrode of the NMOS tube Q5, and the source electrode of the NMOS tube Q5 is electrically connected with the anode of the diode D6 as the output end of the ACC power-on control circuit; the cathode of the diode D3 is connected with the grid electrode of the NMOS tube Q4, and the anode of the diode D is used as one input end of the working range limiting logic circuit and is connected with the output end of the working range lower limit voltage detection circuit; the cathode of the diode D4 is connected with the grid electrode of the NMOS tube Q5, and the anode of the diode D is used as the other input end of the working range limiting logic circuit and is connected with the output end of the working range upper limit voltage detection circuit;

the operating range lower limit voltage detection circuit includes: NMOS tube Q1, PMOS tube Q2, resistor R1 and R2; the drain electrode of the PMOS tube Q2 is used as the output end of the working range lower limit voltage detection circuit to be electrically connected with the anode of the diode D3, the grid electrode of the PMOS tube Q2 is electrically connected with the drain electrode of the NMOS tube Q1, and the source electrode of the PMOS tube Q2 is connected with the working voltage VCC; the grid electrode of the NMOS tube Q1 is connected with the working voltage ACC through a resistor R1, the source electrode of the NMOS tube Q1 is grounded, and two ends of a resistor R2 are respectively connected with the grid electrode and the source electrode of the NMOS tube Q1;

the working range upper limit voltage detection circuit comprises: NMOS tube Q3, resistors R3 and R4; the grid electrode of the NMOS tube Q3 is connected with the working voltage ACC through a resistor R3, the source electrode of the NMOS tube Q is grounded, the drain electrode of the NMOS tube Q is connected with the working voltage VCC and is used as the output end of the working range upper limit voltage detection circuit to be electrically connected with the anode of the diode D4; two ends of the resistor R4 are respectively connected with the grid electrode and the source electrode of the NMOS tube Q3.

Further, the system processor SOC and the ACC power-down holding circuit comprise an ACC detection circuit and a system processor SOC;

the system processor SOC comprises one path of input end and one path of output end which are realized based on the IO port;

the ACC detection circuit comprises an NMOS tube Q6, a diode D8, resistors R7 and R8; the cathode of the diode D8 is connected with the working voltage ACC through a resistor R7, and the anode of the diode D8 is connected with the grid electrode of the NMOS tube Q6 and is grounded through the resistor R8; the source electrode of the NMOS tube Q6 is grounded, and the drain electrode is connected with the working voltage VCC and used as the output end of the ACC detection circuit to be connected with the input end of the system processor SOC; the output end of the system processor SOC is connected with the anode of the diode D5.

Further, the key long-press time delay multiplexing control circuit comprises a mechanical key SW, diodes D9 and D10, resistors R5 and R6, a capacitor C6 and an NMOS tube Q7;

one end of the mechanical key SW is connected with 5V voltage, and the other end of the mechanical key SW is electrically connected with anodes of the diodes D9 and D10 respectively;

the cathode of the diode D9 is connected with one end of a resistor R5, and the other end of the resistor R5 is electrically connected with one end of an RC circuit formed by a resistor R6 and a capacitor C6 and the grid electrode of an NMOS tube Q7;

the other end of the RC circuit formed by the resistor R6 and the capacitor C6 is grounded;

the drain electrode of the NMOS tube Q7 is connected with the working voltage VCC and is electrically connected with the cathode of the diode D7 as the output end of the key long-time-delay multiplexing control circuit, and the source electrode of the NMOS tube Q7 is grounded.

The beneficial effects of the utility model are as follows: 1. the utility model omits the mode of realizing the on-off logic of the special controller, realizes normal ACC power-on and power-off, meets the system time sequence, and has simpler control mode and better cost under the condition of effectively storing the system data;

2. the utility model uses the hardware logic circuit to replace the controller AD detection to realize the undervoltage shutdown and overvoltage protection, and saves MCU controller and AD resources; the system can not work in an overvoltage range;

in addition, the utility model multiplexes the existing keys through a hardware circuit, and increases a prevention mechanism which can not restore the system abnormality; the long-press and short-press functions of the key are judged by detecting the continuous time of the level by the controller, but if the system is dead, the controller cannot identify the press time of the key; the utility model multiplexes the keys through the hardware circuit, does not influence the normal short key pressing function, and can also prevent the irrecoverable caused by non-response under the condition of system crash. When the system is abnormal and does not respond to an external signal, the power supply can be forced to reset by pressing a key for a long time, so that the whole system is reset, and the system is restarted along with the power supply.

Drawings

FIG. 1 is a block diagram of a reliable on-off logic implementation module of an economical interconnected riding instrument provided by an embodiment of the utility model;

fig. 2 is a specific implementation diagram of a reliable on-off logic implementation scheme of an economical interconnected riding instrument provided by an embodiment of the utility model.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the description of the present application, the term "for example" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "for example" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the utility model. In the following description, details are set forth for purposes of explanation. It will be apparent to one of ordinary skill in the art that the present utility model may be practiced without these specific details. In other instances, well-known structures and processes have not been described in detail so as not to obscure the description of the utility model with unnecessary detail. Thus, the present utility model is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

As shown in fig. 1 and 2, the present embodiment provides a reliable on-off circuit of an economical interconnected riding meter, including: the system comprises a power supply control integrated logic circuit, an ACC power-on control circuit, a system processor SOC and ACC power-off holding circuit and a key long-press time delay multiplexing control circuit.

The power supply control integrated logic circuit comprises three input ends and an output end, wherein the three input ends are respectively and electrically connected with the output ends of the ACC power-on control circuit, the system processor SOC, the ACC power-off holding circuit and the key long-press time delay multiplexing control circuit; the output end of the power control integrated logic circuit is electrically connected with the instrument power enabling end.

The power supply control integrated logic circuit comprises three input ends, namely, 5VEN_ACC_CTRL (output end of an ACC power-on control circuit), 5VEN_CTRL (output end of an ACC power-off holding circuit) and an enable input end serving as a power supply circuit. In order to meet the requirements that when the ACC is powered on, the system is reliably powered on, the ACC power-down system is powered off in a delayed manner to save data and reliably shut down, and forced reset shutdown is adopted when the system is abnormal, namely, a long-time-DELAY power-down signal DELAY_RST has a first control priority, an ACC power-on control signal 5VEN_ACC_CTRL and an ACC power-down maintaining signal 5VEN_CTRL have the same control priority, the following logic is adopted to realize: 5v_en= (5ven_ctrl|5ven_acc_ctrl) & (delay_rst).

The power supply control integrated logic circuit is matched with the ACC power-on control circuit, and whether the power supply is enabled or not is determined through voltage logic judgment of the ACC, so that the system is ensured to work in a set working voltage range, and the power supply is not output beyond the range and is not operated in the range of 9-16V of a 12V system for example; the logic control is performed through a hardware circuit, and whether the system works or not is judged without firstly enabling an internal power supply of the instrument to work and then sampling a specific voltage value of a vehicle body battery through an MCU.

The power supply control integrated logic circuit is matched with the system processor SOC and the ACC power-down maintaining circuit to realize ACC power-down detection and system delay power-down, so that system data are ensured to be reliably stored and reliably powered off before power-down.

The power supply control integrated logic circuit is matched with the key long-press time delay multiplexing control circuit, the key function is multiplexed through the hardware circuit to realize long-press shutdown without affecting the original function of the key, and the multiplexing realizes long-press and short-press judgment without detecting the continuous time of the level by means of an MCU; even if the abnormal operation of the system processor does not respond to external signals, the system can be reset and restarted by long-time pressing of forced system power failure, and the system processor is used as an emergency treatment mechanism for preventing the abnormal condition of the system.

Specifically, the ACC power-on control circuit comprises a working range lower limit voltage detection circuit, a working range upper limit voltage detection circuit and a working range limiting logic circuit. The ACC power-on control circuit comprises an input end ACC and an output end 5VEN_ACC_CTRL.

The operating range lower limit voltage detection circuit, for example, sets a lower limit operating voltage acc=9v, i.e., the system is operated at vl_acc >9V, and vl_acc <9V is not operated. It comprises the following steps: NMOS tube Q1, PMOS tube Q2, resistor R1 and R2; the drain electrode of the PMOS tube Q2 is used as the output end of the working range lower limit voltage detection circuit to be electrically connected with the anode of the diode D3, the grid electrode of the PMOS tube Q2 is electrically connected with the drain electrode of the NMOS tube Q1, and the source electrode of the PMOS tube Q2 is connected with the working voltage VCC; the grid electrode of the NMOS tube Q1 is connected with the working voltage ACC through a resistor R1, the source electrode of the NMOS tube Q1 is grounded, and two ends of the resistor R2 are respectively connected with the grid electrode and the source electrode of the NMOS tube Q1.

The NMOS turn-on voltage V (T) =2v is selected, the R1, R2 parameters are set to satisfy Vgs (Q1) = [ R2/(r1+r2) ] = [ r2/(r1+r2) ] = [ 9v=v (T), for example, vgs (Q1) =36K/(36k+120k) ×9v=2.07, or Vgs (Q1) =18k/(18k+62k) ×9v=2.02v, vcc is normally-charged, when vl_acc <9V, Q1 is turned off, Q2 is turned off, vl_en=0 (or L, i.e., low level); when vl_acc >9V, Q1 is on, Q2 is on, vl_en=1 (or H, i.e., high level).

The operating range upper limit voltage detection circuit, for example, sets an upper limit operating voltage acc=16v, i.e., the system operates below 16V, and the system will not operate beyond 16V. It comprises the following steps: NMOS tube Q3, resistors R3 and R4; the grid electrode of the NMOS tube Q3 is connected with the working voltage ACC through a resistor R3, the source electrode of the NMOS tube Q is grounded, the drain electrode of the NMOS tube Q is connected with the working voltage VCC and is used as the output end of the working range upper limit voltage detection circuit to be electrically connected with the anode of the diode D4; two ends of the resistor R4 are respectively connected with the grid electrode and the source electrode of the NMOS tube Q3.

The selected NMOS on voltage V (T) =2v, setting R3, R4 parameters to satisfy Vgs (Q3) = [ R4/(r3+r4) ], 16 v=v (T), for example, vgs (Q3) =27k/(27k+180k) ×16v=2.08v, vcc is normally-charged, when vh_acc >16V, Q3 is on, vh_en=0 (or L, i.e., low level); when vh_acc <16V, Q3 is off, vh_en=1 (or H, i.e., high level).

The operating range defining logic circuit includes: NMOS transistors Q4, Q5, diodes D3, D4; the source electrode of the NMOS tube Q4 is electrically connected with the drain electrode of the NMOS tube Q5, and the source electrode of the NMOS tube Q5 is electrically connected with the anode of the diode D6 as the output end of the ACC power-on control circuit; the cathode of the diode D3 is connected with the grid electrode of the NMOS tube Q4, and the anode of the diode D is used as one input end of the working range limiting logic circuit and is connected with the output end of the working range lower limit voltage detection circuit; the cathode of the diode D4 is connected with the grid electrode of the NMOS tube Q5, and the anode of the diode D is used as the other input end of the working range limiting logic circuit and is connected with the output end of the working range upper limit voltage detection circuit.

Only when vl_en, vh_en are both high, 5ven_acc_ctrl is high, i.e. 5ven_acc_ctrl=vl_en & vh_en. Under the action of the working range lower limit voltage detection circuit and the working range upper limit voltage detection circuit: when ACC <9V, vl_en=0, 5ven_acc_ctrl=vl_en & vh_en=0;

when ACC >16V, vh_en=0, 5ven_acc_ctrl=vl_en & vh_en=0;

when 9v < acc <16v, vl_en=1, vh_en=1, 5ven_acc_ctrl=vl_en & vh_en=1.

That is, only when 9v < acc <16v, vl_en, vh_en are both high, 5ven_acc_ctrl is high; as can be seen from fig. 2, the delay_rst defaults to a high level, and at this time, 5v_en= (5ven_ctrl|5ven_acc_ctrl)/(delay_rst) =1, i.e. a high level, the system power is enabled, and the system is powered on to operate, so as to limit the power-on operating voltage between 9 and 16V.

Further, the system processor SOC and the ACC power-down holding circuit comprise an ACC detection circuit and a system processor SOC; the basic starting point is that the interconnected instrument continuously generates data in the working process, such as video data generated by the recorder function of the instrument, and the interconnected instrument has enough time to process and store the data in the shutdown process through ACC power failure detection and power delay, otherwise, the data is lost or the format is damaged. The shortest time required for processing and storing related data in the shutdown process of the system is denoted as T (shutdown).

The on voltage V (T) =2v of the selected NMOS transistor Q6, R7, R8, D8 parameters are set so as to satisfy Vgs (Q6) = (ACC-3.3V) [ R8/(r7+r8) ]= (9V-3.3V) [ R8/(r7+r8) ]=v (T). In the actual operation process of the circuit:

when ACC is normally powered on, 9v < ACC <16V, vgs (Q6) = (ACC-3.3V) [ R8/(r7+r8) ] > V (T), Q6 is on, acc_det is low, and it is noted that acc_det=0 (or L, i.e., low), SOC maintains an output high state at the IO port output network 5ven_ctrl, i.e., 5ven_ctrl=1 (or H, i.e., high); as can be seen from the drawing, the delay_rst defaults to a high level, and at this time, 5v_en= (5ven_ctrl|5ven_acc_ctrl) & (delay_rst) =1, i.e. a high level, the system power is enabled, and the system operates normally.

When the power is turned off, the ACC starts to be powered off and finally falls to 0V, in the power-off process, when the ACC is smaller than 9V, vgs (Q6) = (ACC-3.3V) [ R8/(R7+R 8) ] < V (T), Q6 is cut off, ACC_DET=1 (or H, namely high level), namely the IO level of an SOC detection port is high, and at the moment, the IO output of the SOC at a control port is kept high (namely 5 VEN_CTRL=1) for a period of time T (delay), and T (delay) > T (shat); the system stores data within the time delay period, and after t (delay) is finished, the SOC outputs a low level at a control port IO, namely, 5VEN_CTRL=0 (or L, namely, a low level); at this time, the working range limiting logic circuit can know that 5ven_acc_ctrl=0, and then 5v_en= (5ven_ctrl|5ven_acc_ctrl) & (delay_rst) =0, the power supply enable end fails, the power supply has no output, and the system is powered down and turned off.

In summary, the system processor SOC and ACC power down hold circuit function in two stages during actual operation.

In the first stage, when ACC is powered on normally, the ACC detection circuit detects acc_det=0 and the IO control port of the soc outputs a high level, i.e. 5ven_ctrl=1. At this time, 9v < acc <16v, 5ven_ctrl=1 (or H, high level), 5ven_acc_ctrl=1 (or H, high level), delay_rst=1 (or H, high level), and then 5v_en= (5ven_ctrl|5ven_acc_ctrl) & (delay_rst) =1, the power source operates normally, and the system operates;

and in the second stage, ACC power-down process. Actually, the method comprises two steps, in the first step, when the ACC is powered down, the ACC detection circuit detects acc_det=1, the SOC detects that the ACC is powered down, the output of the IO control port of the SOC is kept to be 5 ven_ctrl=1 for a delay T (delay), and T (delay) > T (shutdown). At this time, ACC <9v, 5ven_ctrl=1 (or H, high level), 5ven_acc_ctrl=0 (or L, low level), delay_rst=1 (or H, high level), and then 5v_en= (5ven_ctrl|5ven_acc_ctrl) & (delay_rst) =1, i.e. power EN is high, power is normally operated, and the system continues to operate, during which the system completes data saving; and secondly, after t (delay) is finished, the system starts a shutdown process. The IO control port of the SOC outputs a low level, i.e., 5ven_ctrl=0. At this time, ACC <9v, 5ven_ctrl=0 (or L, low level), 5ven_acc_ctrl=0 (or L, low level), and thus 5v_en= (5ven_ctrl|5ven_acc_ctrl) & (delay_rst) =0, no power is output, and the system is powered down and turned off.

Further, the key long-press time delay multiplexing control circuit is expanded from an original key circuit of the instrument and comprises a mechanical key SW, diodes D9 and D10, resistors R5 and R6, a capacitor C6 and an NMOS tube Q7;

The output end delay_RST of the key long-time-DELAY multiplexing control circuit defaults to a high-level state. The selected NMOS on voltage V (T) =2v. And realizing the multiplexing of key functions through the setting of parameters of the D9 and the D10 and the delay circuit. Regarding long presses, the parameters are set to delay T (K_delay) as needed, such as 3-8 s or longer. When the key is pressed, the RC circuit starts to charge, the gate voltage of Q7 is gradually increased, and when the charging time T (K) =T (K_delay), vgs (Q7) =V (T).

When the key is not pressed or pressed for time T (K) < T (k_delay), vgs (Q7) < V (T), Q7 is turned off, the delay_rst output level state is consistent with the circuit default state, namely, delay_rst=1 is kept high, and as known from 5v_en= (5ven_ctrl.sub.5ven_acc_ctrl) & (delay_rst), normal power-on and power-off logic is not affected; and in the period D10 is conducted, KEY_DET detects a high level, and the original definition function of the KEY is realized.

When the key is pressed for time T (K) > T (k_delay), vgs (Q7) > V (T), Q7 is turned on, the delay_rst output level state is inverted to be low, namely, delay_rst=0, and then 5v_en= (5ven_ctrl|5ven_acc_ctrl) & (delay_rst) =0, at this time, the system power is forcibly reset, the system is turned off, and 5ven_ctrl=0; after the key is released, D9 is turned off, C6 is gradually discharged, finally, the low level is recovered, vgs (Q7) < V (T), Q7 is turned off, delay_rst outputs high level, namely delay_rst=1, and when ACC is not manually powered down, 5ven_acc_ctrl=1 is excluded, so that 5v_en= (5ven_ctrl|5ven_acc_ctrl) & (delay_rst) =1, the system power supply is enabled again, and the system is powered up again. The function is used as a beneficial supplement for stable operation of the system so as to prevent the problem that the system is irrecoverable when abnormal caused by complex environment or limit operation possibly occurs.

While preferred embodiments of the present utility model have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the utility model.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present utility model without departing from the spirit or scope of the utility model. Thus, it is intended that the present utility model also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A reliable on-off circuit of an economical interconnected riding meter, comprising: the system comprises a power supply control integrated logic circuit, an ACC power-on control circuit, a system processor SOC and ACC power-off holding circuit and a key long-press time delay multiplexing control circuit;

2. The reliable switching circuit as set forth in claim 1, wherein the ACC power-on control circuit includes an operating range lower limit voltage detection circuit, an operating range upper limit voltage detection circuit, an operating range limit logic circuit, wherein,

3. The reliable switching circuit as recited in claim 1 wherein the system processor SOC and ACC power-down hold circuit comprises an ACC detection circuit and a system processor SOC;

4. The reliable switching circuit as claimed in claim 1, wherein the key long-press time-delay multiplexing control circuit comprises a mechanical key SW, diodes D9, D10, resistors R5, R6, a capacitor C6, and an NMOS transistor Q7;