CN108767946B - Wake-up circuit and battery management system - Google Patents

Wake-up circuit and battery management system Download PDF

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Publication number
CN108767946B
CN108767946B CN201810974231.0A CN201810974231A CN108767946B CN 108767946 B CN108767946 B CN 108767946B CN 201810974231 A CN201810974231 A CN 201810974231A CN 108767946 B CN108767946 B CN 108767946B
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circuit
wake
charge
voltage
resistor
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CN108767946A (en
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秦威
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Shenzhen Autel Intelligent Aviation Technology Co Ltd
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Shenzhen Autel Intelligent Aviation Technology Co Ltd
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Priority to CN201810974231.0A priority Critical patent/CN108767946B/en
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Priority to PCT/CN2019/101798 priority patent/WO2020038406A1/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
    • H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Charge And Discharge Circuits For Batteries Or The Like (AREA)
  • Secondary Cells (AREA)

Abstract

The invention relates to the technical field of batteries and discloses a wake-up circuit and a battery management system. The wake-up circuit comprises a switch circuit, a switch circuit and a wake-up circuit, wherein the switch circuit comprises a switch input end and a switch output end; the signal conditioning circuit comprises a signal input end and a signal output end, wherein the signal input end of the signal conditioning circuit is connected with the switch output end of the switch circuit, and when an external power supply is applied to the switch input end of the switch circuit, the switch circuit works in a conducting state, so that the external power supply is applied to the signal input end of the signal conditioning circuit, and the signal conditioning circuit converts the external power supply into a level trigger signal; and the charge-discharge circuit is connected with the signal output end of the signal conditioning circuit, and enters an awakening state after receiving the level trigger signal. The wake-up circuit and the battery management system provided by the embodiment of the invention can reduce potential safety hazards, thereby prolonging the service life of the battery pack.

Description

Wake-up circuit and battery management system
Technical Field
The present invention relates to the field of battery technologies, and in particular, to a wake-up circuit and a battery management system.
Background
The battery management system (Battery Management System, BMS) is a system for managing a battery or a battery pack, and generally has functions of measuring a voltage of the battery pack, managing charge and discharge of the battery pack, preventing or avoiding occurrence of abnormal conditions (overdischarge, overcharge, over-temperature, etc.). When the battery pack is in a non-use or non-working state, in order to reduce power consumption, and to reduce power consumption of the battery pack, particularly to avoid overdischarge damage to the battery pack when the remaining capacity of the battery pack is small, the battery management system generally enters a low power consumption state, such as a sleep state. Sometimes the battery management system may even go into a deep sleep state. When the battery management system enters a sleep state, a charge and discharge circuit or module for managing the battery pack in the battery management system is also in the sleep state. After the charge-discharge circuit is in a dormant state, if the battery pack needs to be normally used, such as the battery pack supplies power to external equipment or the external equipment charges the battery pack, the charge-discharge circuit or module for managing the battery pack must be awakened first, otherwise, the charge-discharge circuit or module is always in the dormant state, so that the battery cannot normally work.
In the current general wake-up method, a charge-discharge circuit or module is woken up by detecting a current to charge and discharge a battery pack. For example, taking charging a battery pack as an example, when the presence of a charging current is detected, a charge-discharge circuit is awakened to charge the battery pack; when no charging current is detected, the charging and discharging circuit maintains a dormant state until the charging current is detected, and the charging and discharging circuit is awakened so as to charge the battery pack.
In the process of implementing the present invention, the inventor finds that at least the following problems exist in the related art: in the method of waking up the charge-discharge circuit by detecting the current, it is necessary to ensure that the path through which the current detected by the battery management system flows is conductive when the battery management system is dormant, and the conduction causes problems such as potential safety hazard when the battery management system is dormant. For example, the conduction during the sleep may cause the battery pack to be reversely discharged and damaged when the battery pack is charged.
Disclosure of Invention
The embodiment of the invention aims to provide a wake-up circuit and a battery management system, which can reduce potential safety hazards and further prolong the service life of a battery pack.
In order to solve the technical problems, the embodiment of the invention provides the following technical scheme:
in a first aspect, an embodiment of the present invention provides a wake-up circuit, including:
the switching circuit comprises a switching input end and a switching output end;
the signal conditioning circuit comprises a signal input end and a signal output end, wherein the signal input end of the signal conditioning circuit is connected with the switch output end of the switch circuit, and when an external power supply is applied to the switch input end of the switch circuit, the switch circuit works in a conducting state, so that the external power supply is applied to the signal input end of the signal conditioning circuit, and the signal conditioning circuit converts the external power supply into a level trigger signal;
and the charge-discharge circuit is connected with the signal output end of the signal conditioning circuit, and enters an awakening state after receiving the level trigger signal.
In some embodiments, the level trigger signal is a high level signal.
In some embodiments, the signal conditioning circuit includes a first voltage dividing circuit including a first voltage dividing input connected to the switch output and a first voltage dividing output connected to the charge-discharge circuit;
the first voltage dividing circuit is used for dividing the voltage of an external power supply applied to a signal input end of the signal conditioning circuit so as to convert the external power supply into a level trigger signal.
In some embodiments, the first voltage divider circuit includes a first resistor and a second resistor;
one end of the first resistor is used as the first voltage division input end to be connected with the switch output end, the other end of the first resistor is connected with one end of the second resistor, and the other end of the first resistor and one end of the second resistor are used as the first voltage division output end to be connected with the charge-discharge circuit;
the other end of the second resistor is grounded.
In some embodiments, the first voltage dividing circuit further includes a first voltage stabilizing tube, a cathode of the first voltage stabilizing tube is connected to a first voltage dividing output end of the first voltage dividing circuit, and an anode of the first voltage stabilizing tube is grounded.
In some embodiments, the charge-discharge circuit includes:
the analog front end comprises an analog input end and an analog output end, and the analog input end is connected with the signal output end of the signal conditioning circuit;
the charge-discharge control circuit comprises a charge-discharge input end and a charge-discharge output end, wherein the charge-discharge input end is connected with the analog output end, and the charge-discharge output end is used for being connected with the battery pack;
when the level trigger signal is input to the analog front end, the analog front end enters an awake state, and the analog front end controls the charge and discharge of the battery pack by driving the charge and discharge control circuit.
In some embodiments, the charge-discharge control circuit comprises a discharge control circuit and a charge control circuit, the discharge control circuit comprises a discharge input control end, the charge control circuit comprises a charge input control end, and the discharge input control end and the charge input control end are both connected with an analog output end of the analog front end;
the discharge control circuit and the charge control circuit are connected in series between the total negative terminal of the battery pack and the output negative terminal of the battery pack.
In some embodiments, the analog output of the analog front end includes a first drive output and a second drive output;
the discharging control circuit comprises a first MOS tube, and the charging control circuit comprises a second MOS tube;
the grid electrode of the first MOS tube is connected with the first driving output end, the source electrode of the first MOS tube is connected with the total negative end of the battery pack through a detection resistor, the source electrode of the first MOS tube is grounded through the detection resistor, the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the second driving output end, and the source electrode of the second MOS tube is connected with the output negative electrode of the battery pack;
when the analog front end enters an awake state, the first MOS tube and the second MOS tube are conducted so that the battery pack enters a charging state.
In some embodiments, the switch circuit includes a second voltage divider circuit, a third MOS transistor, and a fourth MOS transistor;
the second voltage dividing circuit comprises a second voltage dividing input end, a second voltage dividing output end and a voltage dividing input control end, wherein the second voltage dividing input end is used for being connected with an output positive electrode of the battery pack;
the grid electrode of the third MOS tube is grounded through a third resistor, the source electrode of the third MOS tube is connected with the output cathode of the battery pack, and the drain electrode of the third MOS tube is connected with the second voltage division output end;
the grid electrode of the fourth MOS tube is connected with the voltage division input control end, the source electrode of the fourth MOS tube is connected with the second voltage division input end, and the drain electrode of the fourth MOS tube is connected with the signal input end of the signal conditioning circuit;
when an external power supply is applied to the switch input end of the switch circuit, the third MOS tube and the fourth MOS tube are conducted.
In some embodiments, the second voltage divider circuit includes a fourth resistor and a fifth resistor,
one end of the fourth resistor is used as the second voltage division input end to be connected with the source electrode of the fourth MOS tube, the other end of the fourth resistor is connected with one end of the fifth resistor, and the other end of the fourth resistor and one end of the fifth resistor are used as the voltage division input control end to be connected with the grid electrode of the fourth MOS tube;
the other end of the fifth resistor is used as the second voltage division output end and is connected with the drain electrode of the third MOS tube.
In some embodiments, the switching circuit further includes a second voltage regulator, a cathode of the second voltage regulator is connected to a gate of the third MOS transistor, and an anode of the second voltage regulator is connected to a source of the third MOS transistor.
In some embodiments, the switching circuit further includes a third voltage regulator, a cathode of the third voltage regulator is connected to a source of the fourth MOS transistor, and an anode of the third voltage regulator is connected to a gate of the fourth MOS transistor.
In a second aspect, an embodiment of the present invention provides a battery management system comprising a wake-up circuit as described above.
In various embodiments of the present invention, when an external power is applied to a switch input end of a switch circuit, the switch circuit is in a conductive state, so that the external power is applied to a signal input end of a signal conditioning circuit, and the signal conditioning circuit converts the external power into a level trigger signal and sends the level trigger signal to a charge-discharge circuit, and after the charge-discharge circuit receives the level trigger signal, the charge-discharge circuit can enter a wake-up state without waking up the charge-discharge circuit by detecting current, thereby reducing potential safety hazards and improving the service life of a battery pack.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
Fig. 1 is a schematic circuit diagram of a wake-up circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a specific circuit structure of a wake-up circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a wake-up circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the signal conditioning circuit of FIG. 1;
FIG. 5 is a schematic diagram of the charge-discharge circuit of FIG. 1;
FIG. 6 is a schematic diagram of the switching circuit of FIG. 1;
fig. 7 is a schematic diagram of a battery management system according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only and are not meant to be the only embodiment.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Fig. 1 is a schematic diagram of a wake-up circuit according to an embodiment of the present invention. Wherein the wake-up circuit 100 comprises: comprises a signal conditioning circuit 10, a charge-discharge circuit 20 and a switch circuit 30. The switching circuit 30 is connected to the signal conditioning circuit 10, and the signal conditioning circuit 10 is connected to the charge/discharge circuit 20.
Specifically, the switching circuit 30 includes a switching input terminal 301 and a switching output terminal 302; the signal conditioning circuit 10 includes a signal input 101 and a signal output 102. The signal input terminal 101 of the signal conditioning circuit 10 is connected to the switch output terminal 302 of the switch circuit 30, and the signal output terminal 102 of the signal conditioning circuit 10 is connected to the charge/discharge circuit 20.
When the external power is applied to the switch input 301 of the switch circuit 30, the switch circuit 30 is in a conductive state, so that the external power is applied to the signal input 101 of the signal conditioning circuit 10, the signal conditioning circuit 10 converts the external power into a level trigger signal and sends the level trigger signal to the charge and discharge circuit 20, and the charge and discharge circuit 20 enters a wake-up state after receiving the level trigger signal, so that the charge and discharge of the battery pack can be performed.
The external power supply may be an external power supply voltage or an external power supply current, or the like. Also, the external power supply may be applied to the switch input 301 of the switch circuit 30 by switching in an external device, for example, in the case of charging the battery pack, the external power supply may be applied to the switch input 301 of the switch circuit 30 by switching in a charger.
In the embodiment of the invention, the charge and discharge circuit is not required to be awakened by detecting the current, so that the potential safety hazard can be reduced, and the service life of the battery pack can be prolonged.
The wake-up circuit 100 and the signal conditioning circuit 10, the charge-discharge circuit 20 and the switch circuit 30 in the wake-up circuit 100 according to the embodiments of the present invention are described in detail below with reference to fig. 2 to 6. Fig. 2 is a schematic diagram of a specific structure of a wake-up circuit according to an embodiment of the present invention; FIG. 3 is a schematic diagram of a wake-up circuit according to an embodiment of the present invention; FIG. 4 is a schematic diagram of a signal conditioning circuit; FIG. 5 is a schematic diagram of a charge-discharge circuit; fig. 6 is a schematic diagram of a switching circuit.
Referring to fig. 2-4, the signal conditioning circuit 10 includes a first voltage divider 103. The first voltage dividing circuit 103 includes a first voltage dividing input terminal 1031 and a first voltage dividing output terminal 1032. The first voltage dividing input terminal 1031 of the first voltage dividing circuit 103 is connected to the switch output terminal 302 of the switch circuit 30. The first voltage division output 1032 of the first voltage division circuit 103 is connected to the charge/discharge circuit 20. For example, the first voltage division output 1032 of the first voltage division circuit 103 is connected to the input terminal of the charge/discharge circuit 20.
The first voltage dividing circuit 103 is used for dividing the external power applied to the signal input terminal 101 of the signal conditioning circuit 10 to convert the external power into a level trigger signal.
In some implementations, the first voltage divider circuit 103 includes a first resistor R1 and a second resistor R2. Wherein the first resistor R1 and the second resistor R2 are connected in series.
Specifically, one end of the first resistor R1 is connected to the switch output 302 of the switch circuit 30 as the first voltage division input 1031, and the other end of the first resistor R1 is connected to one end of the second resistor R2. The other end of the first resistor R1 and one end of the second resistor R2 are connected to the charge/discharge circuit 20 as a first voltage division output 1032. The other end of the second resistor R2 is grounded GND.
In some other embodiments, the first voltage dividing circuit 103 may be any other suitable voltage dividing circuit, so long as the function of dividing the external power applied to the signal input terminal 101 of the signal conditioning circuit 10 and converting the external power into the level trigger signal can be achieved. For example, three or more resistors are connected in series to form a voltage divider circuit.
In addition, the external power source applied to the signal input terminal 101 of the signal conditioning circuit 10 may be a high level signal after being divided by the first voltage dividing circuit 103 and converted into a level trigger signal. The high level signal refers to a level signal of logic "1". The charge-discharge circuit 20 can be triggered to enter the awake state by the high level signal.
In some implementations, the signal conditioning circuit 10 further includes a first voltage regulator tube D1. The cathode of the first voltage stabilizing tube D1 is connected to the first voltage dividing output 1032 of the first voltage dividing circuit 103, and the anode of the first voltage stabilizing tube D1 is grounded GND.
The first voltage stabilizing tube D1 is used for stabilizing voltage to ensure stability of the level trigger signal input to the charge-discharge circuit 20. The first zener diode D1 may be a zener diode or the like. The voltage stabilizing value of the first voltage stabilizing tube D1 is slightly larger than the voltage dividing value of the first resistor R1 and the second resistor R2 and does not exceed the voltage withstanding value of the input end of the charge-discharge circuit 20.
Referring to fig. 2, 3 and 5, the charge/discharge circuit 20 includes: an analog front end 203 and a charge-discharge control circuit 204. The analog front end 203 is connected to a charge/discharge control circuit 204.
The analog front end 203 includes an analog input 2031 and an analog output 2032. The charge/discharge control circuit 204 includes a charge/discharge input terminal 2041 and a charge/discharge output terminal 2042.
Wherein the analog input 2031 of the analog front end 203 is connected to the signal output 102 of the signal conditioning circuit 10. The analog output terminal 2032 of the analog front end 203 is connected to the charge/discharge input terminal 2041 of the charge/discharge control circuit 204. The analog front end 203 is used to control the charge-discharge control circuit 204.
For the battery management system, the analog front end 203 may be any suitable battery management chip, for example, the analog front end 203 may be a BQ769X0 series (e.g., BQ76920, BQ76930, BQ76940, etc.) battery management chip. The external power supply is divided by the first voltage dividing circuit 103 and then combined with the voltage stabilization of the first voltage stabilizing tube D1, so that the input end (TS 1 port) of the BQ769X0 chip can receive a high-level signal of 3.3V, thereby waking up the BQ769X0 chip. Wherein, in order to protect BQ769X0 chip, the voltage stabilizing value of first voltage stabilizing tube D1 does not exceed the withstand voltage value of TS1 port of BQ769X0 chip.
The charge/discharge input end 2041 of the charge/discharge control circuit 204 is connected to the analog output end 2032 of the analog front end 203, and the charge/discharge output end 2042 of the charge/discharge control circuit 204 is used for connecting a battery pack to control charge/discharge of the battery pack. The battery pack may be composed of a plurality of cells connected in series.
When the signal conditioning circuit 10 inputs a level trigger signal to the analog front end 203, the analog front end 203 enters an awake state. After the analog front end 203 enters the awake state, the analog front end 203 controls the charge and discharge of the battery pack by driving the charge and discharge control circuit 204.
In the embodiment of the present invention, the analog front end 203 enters the wake-up state by directly receiving the level trigger signal sent by the signal conditioning circuit 10, so as to drive the charge-discharge control circuit 204, and then the charge-discharge circuit 20 enters the wake-up state, so that the wake-up circuit 100 provided by the embodiment of the present invention can avoid the problem that the microprocessor cannot wake-up due to the program run, crash, latch-up and other faults, compared with the general mode that the microprocessor (such as MCU) sends a control command to wake up the analog front end and then wake up the charge-discharge circuit.
It should be noted that, in some other embodiments, the wake-up circuit 100 or the charge-discharge circuit 20 in the wake-up circuit 100 may also include a microprocessor (not shown). When the wake-up circuit 100 or the charge-discharge circuit 20 in the wake-up circuit 100 includes a microprocessor, an input end of the microprocessor is connected with the signal output end 102 of the signal conditioning circuit 10 to receive a level trigger signal sent by the signal conditioning circuit 10; and, the output end of the microprocessor is connected to the analog input end 2031 of the analog front end 203, and after receiving the level trigger signal, the microprocessor sends a control command to the analog front end 203, so as to control the analog front end 203 to enter an awake state, and then, the analog front end 203 drives the charge and discharge control circuit 204 to perform charge and discharge control on the battery pack.
In some implementations, the charge-discharge control circuit 204 includes a discharge control circuit 2043 and a charge control circuit 2044. The discharging control circuit 2043 includes a discharging input control terminal 20431, and the charging control circuit 2044 includes a charging input control terminal 20441. The discharging input control terminal 20431 and the charging input control terminal 20441 are connected to the analog output terminal 2032 of the analog front end 203.
The analog output 2032 of the analog front end 203 may include a first driving output 20321 or a second driving output 20322, to be connected to a corresponding discharge input control terminal 20431 or a corresponding charge input control terminal 20441, respectively.
Specifically, the first driving output terminal 20321 is connected to the discharging input control terminal 20431, and the second driving output terminal 20322 is connected to the charging input control terminal 20441. For example, the analog front end 203 is exemplified by a BQ769X0 chip, the first drive output 20321 is specifically a DSG pin of the BQ769X0 chip, and the second drive output 20322 is specifically a CHG pin of the BQ769X0 chip.
The discharge control circuit 2043 and the charge control circuit 2044 are connected in series between the total negative terminal of the battery pack and the output negative terminal of the battery pack. Taking fig. 2 as an example, the battery PACK includes a total positive terminal b+, a total negative terminal B-, an output positive pole pack+, and an output negative pole PACK-. The total positive end B+ of the battery PACK is the highest voltage end of the battery PACK, the total negative end B-of the battery PACK is the lowest voltage end of the battery PACK, the output positive pole PACK+ of the battery PACK is the positive pole output end of the battery PACK, and the output negative pole PACK-of the battery PACK is the negative pole output end of the battery PACK. The output positive pole pack+ of the battery PACK is also the positive pole charging port of the battery PACK, and the output negative pole PACK of the battery PACK is also the negative pole charging port of the battery PACK.
In some other embodiments, the discharge control circuit 2043 and the charge control circuit 2044 may also be connected in series between the total positive terminal b+ of the battery PACK and the output positive terminal pack+ of the battery PACK.
Since the battery PACK is composed of a plurality of batteries connected in series, the voltage of the battery PACK is generally high, and therefore, the charge/discharge of the battery PACK is easier to control in the former manner in which the discharge control circuit 2043 and the charge control circuit 2044 are connected in series between the total negative terminal B-of the battery PACK and the output negative electrode PACK-of the battery PACK, as compared with the manner in which the discharge control circuit 2043 and the charge control circuit 2044 are connected in series between the total positive terminal b+ of the battery PACK and the output positive electrode pack+ of the battery PACK.
In some other embodiments, the discharge control circuit 2043 and the charge control circuit 2044 may also be connected in parallel. In addition, when the battery pack is charged or discharged, the power consumed by the discharge control circuit 2043 and the charge control circuit 2044 is smaller than those consumed by the series connection.
For example, if the discharge control circuit 2043 and the charge control circuit 2044 are connected in series, current flows through the discharge control circuit 2043 and the charge control circuit 2044 during charging or discharging of the battery pack, and power consumption is relatively large; if the discharging control circuit 2043 is connected in parallel with the charging control circuit 2044, the charging current does not flow through the discharging control circuit 2043 when the battery pack is charged, and the discharging current does not flow through the charging control circuit 2044 when the battery pack is discharged, so that the power consumption is greatly reduced, and the effect of saving the cost is achieved.
In some implementations, the discharge control circuit 2043 includes a first MOS transistor Q1 and the charge control circuit 2044 includes a second MOS transistor Q2. The first MOS transistor Q1 is connected to the first driving output 20321 of the analog front end 203, and the second MOS transistor Q2 is connected to the second driving output 20322 of the analog front end 203.
Specifically, the gate of the first MOS transistor Q1 is connected to the first driving output end 20321, the source of the first MOS transistor Q1 is connected to the total negative terminal B-of the battery PACK through the detection resistor RSENSE, the source of the first MOS transistor Q1 is further connected to the ground GND through the detection resistor RSENSE, the drain of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2, the gate of the second MOS transistor Q2 is connected to the second driving output end 20322, and the source of the second MOS transistor Q2 is connected to the output negative electrode PACK-of the battery PACK. Wherein, the grid electrode is denoted by G, the source electrode is denoted by S, and the drain electrode is denoted by D.
After the analog front end 203 enters the wake-up state, the first MOS transistor Q1 and the second MOS transistor Q2 are turned on, so that the battery pack enters the charge state. For example, when the first MOS transistor Q1 and the second MOS transistor Q2 are turned on, the charger connected to the output positive pole PACK+ and the output negative pole PACK+ of the battery PACK can charge the battery PACK.
Referring to fig. 2, 3 and 6, the switching circuit 30 includes: the second voltage dividing circuit 303, the third MOS transistor Q3, and the fourth MOS transistor Q4. The second voltage divider 303 is connected to the third MOS transistor Q3 and the fourth MOS transistor Q4, respectively.
Specifically, the second voltage dividing circuit 303 includes a second voltage dividing input terminal 3031, a second voltage dividing output terminal 3032, and a voltage dividing input control terminal 3033. The second voltage division input end 3031 is used for being connected with an output positive pole PACK+ of the battery PACK; the grid electrode of the third MOS tube Q3 is grounded GND through a third resistor R3, the source electrode of the third MOS tube Q3 is connected with the output negative pole PACK-of the battery PACK, and the drain electrode of the third MOS tube Q3 is connected with the second voltage division output end 3032 of the second voltage division circuit 303; the gate of the fourth MOS transistor Q4 is connected to the voltage division input control end 3033 of the second voltage division circuit 303, the source of the fourth MOS transistor Q4 is connected to the second voltage division input end 3031 of the second voltage division circuit 303, and the drain of the fourth MOS transistor Q4 is connected to the signal input end 101 of the signal conditioning circuit 10.
The third MOS transistor Q3 may be an N-channel MOS transistor, and the fourth MOS transistor Q4 may be a P-channel MOS transistor.
When an external power is applied to the switch input 301 of the switch circuit 30, the third MOS transistor Q3 and the fourth MOS transistor Q4 are turned on. After the third MOS transistor Q3 and the fourth MOS transistor Q4 are turned on, an external power source may be applied to the signal input terminal 101 of the signal conditioning circuit 10, so as to wake up the charge-discharge circuit 20.
In some implementations, the second voltage divider circuit 303 includes a fourth resistor R4 and a fifth resistor R5. Wherein the fourth resistor R4 and the fifth resistor R5 are connected in series.
Specifically, one end of the fourth resistor R4 is connected to the source of the fourth MOS transistor Q4 as the second voltage division input terminal 3031, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5, and the other end of the fourth resistor R4 and one end of the fifth resistor R5 are connected to the gate of the fourth MOS transistor Q4 as the voltage division input control terminal 3033. The other end of the fifth resistor R4 is connected to the drain of the third MOS transistor Q3 as the second voltage division output terminal 3032.
In some other embodiments, the second voltage divider circuit 303 can be other suitable voltage divider circuits. For example, three or more resistors are connected in series to form a voltage divider circuit.
In some implementations, the switching circuit 30 further includes a second regulator tube D2. The cathode of the second voltage stabilizing tube D2 is connected with the grid electrode of the third MOS tube Q3, and the anode of the second voltage stabilizing tube D2 is connected with the source electrode of the third MOS tube Q3. The second zener diode D2 may be a zener diode or the like. The voltage stabilizing value of the second voltage stabilizing tube D2 does not exceed the gate-source voltage withstanding value of the third MOS tube Q3.
In some implementations, the switching circuit 30 further includes a third regulator tube D3. The cathode of the third voltage stabilizing tube D3 is connected with the source electrode of the fourth MOS tube Q4, and the anode of the third voltage stabilizing tube D3 is connected with the grid electrode of the fourth MOS tube Q4. The third zener diode D3 may be a zener diode or the like. The voltage stabilizing value of the third voltage stabilizing tube D3 does not exceed the gate-source voltage withstanding value of the fourth MOS tube Q4.
The following is the working principle of the wake-up circuit 100 provided in the embodiment of the present invention:
referring to fig. 2 and 3, when the battery management system enters a sleep state, the DSG and CHG pins in the BQ769X0 chip output low-level signals, so that the charge-discharge circuit 20 is in the sleep state, i.e. the first MOS transistor Q1 and the second MOS transistor Q2 are disconnected. At this time, the output cathode PACK of the battery PACK is in a suspended state (no current flows), and the gate of the third MOS transistor Q3 is grounded GND through the third resistor R3, so that the source of the third MOS transistor Q3 is connected to the output cathode PACK of the battery PACK, and the third MOS transistor Q3 is disconnected, so that the gate and the source of the fourth MOS transistor Q4 are at equal potential, the fourth MOS transistor Q4 is disconnected, and finally no voltage is input to the TS1 port of the BQ769X0 chip, and because the second resistor R2 is grounded GND, the input signal of the TS1 port is a low level signal at this time, so that the BQ769X0 chip is in a dormant state, that is, the charge-discharge circuit 20 is in a dormant state.
When an external power supply is applied while the battery management system is in a sleep state, such as a charger is connected between the output positive pole pack+ and the output negative pole PACK-of the battery PACK, since the third MOS transistor Q3 and the fourth MOS transistor Q4 are both disconnected, the output negative pole PACK-of the battery PACK is at a low potential with respect to the ground GND, that is, there is a potential difference between the output negative pole PACK-of the battery PACK and the ground, which is equal to the output voltage of the charger.
Because of the existence of the potential difference, the grid electrode of the third MOS tube Q3 is grounded GND through the third resistor R3, and the source electrode of the third MOS tube Q3 is connected with the output negative pole PACK-of the battery PACK, so that the voltage difference exists between the grid electrode of the third MOS tube Q3 and the source electrode of the third MOS tube Q3, and the third MOS tube Q3 can be conducted as long as the voltage difference is larger than the starting voltage of the third MOS tube Q3.
When the third MOS transistor Q3 is turned on, with the output negative pole PACK-connection of the battery PACK as a reference, the gate voltage of the fourth MOS transistor Q4 is a voltage division between the fourth resistor R4 and the fifth resistor R5 applied to the external power supply voltage of the output positive pole pack+ of the battery PACK, and the source voltage of the fourth MOS transistor Q4 is the external power supply voltage, so long as the gate-source voltage of the third MOS transistor Q3 is greater than the turn-on voltage of the fourth MOS transistor Q4, the fourth MOS transistor Q4 is turned on.
When the fourth MOS transistor Q4 is turned on, the voltage applied to the output positive pole pack+ of the battery PACK is divided by the fourth resistor R4 and the fifth resistor R5 and then input to the first voltage division input terminal 1031 of the first voltage division circuit 103, that is, one end of the first resistor R1, and then the voltage division is performed by the first resistor R1 and the second resistor R2 to obtain a high level signal, and the high level signal is input to the TS1 pin of the BQ769X0 chip, so that the BQ769X0 chip is in the wake-up state.
When the BQ769X0 chip is in the wake-up state, the DSG and CHG pins in the BQ769X0 chip output high-level signals, so that the charge-discharge circuit 20 is in the wake-up state, that is, the first MOS transistor Q1 and the second MOS transistor Q2 are turned on, and the charger starts to charge the battery pack.
Through the above procedure, the wake-up function of the wake-up circuit 100 can be realized.
It should be noted that, in some other embodiments, the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4 may be replaced by other devices that can implement the functions of the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4, for example, a triode may be used to replace each of the MOS transistors.
According to the wake-up circuit 100 provided by the embodiment of the invention, when the external power is applied to the switch input end 301 of the switch circuit 30, the switch circuit 30 is in a conducting state, so that the external power is applied to the signal input end 101 of the signal conditioning circuit 10, and the signal conditioning circuit 10 converts the external power into a level trigger signal to be sent to the charge-discharge circuit 20, after the charge-discharge circuit 20 receives the level trigger signal, the charge-discharge circuit 20 can enter a wake-up state without waking up the charge-discharge circuit by detecting current, thereby reducing potential safety hazards, for example, the potential safety hazards can be the situation that the battery pack is reversely discharged to damage the battery pack when the battery pack is charged originally due to the conduction of the path through which the current detected during dormancy, so as to prolong the service life of the battery pack.
Referring to fig. 7, a battery management system according to an embodiment of the invention is provided. The battery management system 200 is used to manage various battery packs, such as lithium batteries, nickel cadmium batteries, or other storage batteries. The battery pack may be used to provide power to various electronic devices, such as aircraft, automobiles, terminal equipment, wearable devices, and the like. The battery pack may also be charged by various devices, such as by a charger. The battery management system 200 is used to manage the charge and discharge of the battery pack. The battery management system includes the wake-up circuit 100 described above. The wake-up circuit 100 can reduce potential safety hazards, thereby prolonging the service life of the battery pack.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the invention, the steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims (13)

1. A wake-up circuit, excluding a microprocessor, comprising:
the switching circuit comprises a switching input end and a switching output end;
the signal conditioning circuit comprises a signal input end and a signal output end, wherein the signal input end of the signal conditioning circuit is connected with the switch output end of the switch circuit, and when an external power supply is applied to the switch input end of the switch circuit, the switch circuit works in a conducting state, so that the external power supply is applied to the signal input end of the signal conditioning circuit, and the signal conditioning circuit converts the external power supply into a level trigger signal;
and the charge-discharge circuit is connected with the signal output end of the signal conditioning circuit, and enters an awakening state after receiving the level trigger signal sent by the signal conditioning circuit.
2. The wake-up circuit of claim 1, wherein the level trigger signal is a high level signal.
3. The wake-up circuit of claim 1 or 2, wherein the signal conditioning circuit comprises a first voltage dividing circuit comprising a first voltage dividing input and a first voltage dividing output, the first voltage dividing input being connected to the switch output, the first voltage dividing output being connected to the charge-discharge circuit;
the first voltage dividing circuit is used for dividing the voltage of an external power supply applied to a signal input end of the signal conditioning circuit so as to convert the external power supply into a level trigger signal.
4. The wake-up circuit of claim 3, wherein the first voltage divider circuit comprises a first resistor and a second resistor;
one end of the first resistor is used as the first voltage division input end to be connected with the switch output end, the other end of the first resistor is connected with one end of the second resistor, and the other end of the first resistor and one end of the second resistor are used as the first voltage division output end to be connected with the charge-discharge circuit;
the other end of the second resistor is grounded.
5. The wake-up circuit of claim 3, wherein the first voltage divider circuit further comprises a first voltage regulator tube, a cathode of the first voltage regulator tube is connected to a first voltage division output terminal of the first voltage divider circuit, and an anode of the first voltage regulator tube is grounded.
6. The wake-up circuit of any of claims 1-5, wherein the charge-discharge circuit comprises:
the analog front end comprises an analog input end and an analog output end, and the analog input end is connected with the signal output end of the signal conditioning circuit;
the charge-discharge control circuit comprises a charge-discharge input end and a charge-discharge output end, wherein the charge-discharge input end is connected with the analog output end, and the charge-discharge output end is used for being connected with the battery pack;
when the level trigger signal is input to the analog front end, the analog front end enters an awake state, and the analog front end controls the charge and discharge of the battery pack by driving the charge and discharge control circuit.
7. The wake-up circuit of claim 6, wherein the charge-discharge control circuit comprises a discharge control circuit and a charge control circuit, the discharge control circuit comprises a discharge input control terminal, the charge control circuit comprises a charge input control terminal, and the discharge input control terminal and the charge input control terminal are both connected with an analog output terminal of the analog front end;
the discharge control circuit and the charge control circuit are connected in series between the total negative terminal of the battery pack and the output negative terminal of the battery pack.
8. The wake-up circuit of claim 7, wherein the analog output of the analog front end comprises a first drive output and a second drive output;
the discharging control circuit comprises a first MOS tube, and the charging control circuit comprises a second MOS tube;
the grid electrode of the first MOS tube is connected with the first driving output end, the source electrode of the first MOS tube is connected with the total negative end of the battery pack through a detection resistor, the source electrode of the first MOS tube is grounded through the detection resistor, the drain electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the second driving output end, and the source electrode of the second MOS tube is connected with the output negative electrode of the battery pack;
when the analog front end enters an awake state, the first MOS tube and the second MOS tube are conducted so that the battery pack enters a charging state.
9. The wake-up circuit of any of claims 1-8, wherein the switching circuit comprises a second voltage divider circuit, a third MOS transistor, and a fourth MOS transistor;
the second voltage dividing circuit comprises a second voltage dividing input end, a second voltage dividing output end and a voltage dividing input control end, wherein the second voltage dividing input end is used for being connected with an output positive electrode of the battery pack;
the grid electrode of the third MOS tube is grounded through a third resistor, the source electrode of the third MOS tube is connected with the output cathode of the battery pack, and the drain electrode of the third MOS tube is connected with the second voltage division output end;
the grid electrode of the fourth MOS tube is connected with the voltage division input control end, the source electrode of the fourth MOS tube is connected with the second voltage division input end, and the drain electrode of the fourth MOS tube is connected with the signal input end of the signal conditioning circuit;
when an external power supply is applied to the switch input end of the switch circuit, the third MOS tube and the fourth MOS tube are conducted.
10. The wake-up circuit of claim 9 wherein the wake-up circuit is configured to wake up the wake-up circuit,
the second voltage dividing circuit includes a fourth resistor and a fifth resistor,
one end of the fourth resistor is used as the second voltage division input end to be connected with the source electrode of the fourth MOS tube, the other end of the fourth resistor is connected with one end of the fifth resistor, and the other end of the fourth resistor and one end of the fifth resistor are used as the voltage division input control end to be connected with the grid electrode of the fourth MOS tube;
the other end of the fifth resistor is used as the second voltage division output end and is connected with the drain electrode of the third MOS tube.
11. The wake-up circuit of claim 9 wherein the wake-up circuit is configured to wake up the wake-up circuit,
the switching circuit further comprises a second voltage stabilizing tube, wherein the cathode of the second voltage stabilizing tube is connected with the grid electrode of the third MOS tube, and the anode of the second voltage stabilizing tube is connected with the source electrode of the third MOS tube.
12. The wake-up circuit of claim 9 wherein the wake-up circuit is configured to wake up the wake-up circuit,
the switching circuit further comprises a third voltage stabilizing tube, wherein the cathode of the third voltage stabilizing tube is connected with the source electrode of the fourth MOS tube, and the anode of the third voltage stabilizing tube is connected with the grid electrode of the fourth MOS tube.
13. A battery management system comprising a wake-up circuit as claimed in any one of claims 1 to 12.
CN201810974231.0A 2018-08-24 2018-08-24 Wake-up circuit and battery management system Active CN108767946B (en)

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CN110764446B (en) * 2019-10-23 2022-10-04 重庆梅安森科技股份有限公司 Chip peripheral circuit of integrated on-off control circuit
CN112895924A (en) * 2019-12-03 2021-06-04 恒大新能源技术(深圳)有限公司 Charging detection and wake-up circuit and battery management system

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