CN220438930U

CN220438930U - Interface expanding device

Info

Publication number: CN220438930U
Application number: CN202322044623.6U
Authority: CN
Inventors: 黄振华; 张艳平
Original assignee: Zhuhai Shininda Technology Co ltd
Current assignee: Zhuhai Shininda Technology Co ltd
Priority date: 2023-07-31
Filing date: 2023-07-31
Publication date: 2024-02-02
Anticipated expiration: 2033-07-31

Abstract

The embodiment of the utility model discloses an interface expansion device, which at least comprises a PCIE connector, a clock control module and a plurality of M.2 connectors, wherein the PCIE connector is respectively connected with the plurality of M.2 connectors through the clock control module; the data lines of the PCIE connectors are respectively connected with a plurality of M.2 connectors; the PCIE connector clock signal is connected with the input clock signal of the clock control module; the multiple output clock signals of the clock control module are respectively connected with the multiple M.2 connectors, and the PCIE bridge is not used in the embodiment of the utility model, so that the slot of one PCIE X8 can be converted into the slots of two M.2 (PCIE X4), and the utility model has the advantages of simple structure, low cost, high expansibility and high density design.

Description

Interface expanding device

Technical Field

The present utility model relates to the field of communications technologies, and in particular, to an interface expansion device.

Background

For computers, the common extensible interface is a PCIE slot, while the m.2 interface is limited by the number of computer boards that are in space, typically no more than two. The utilization of the computer chassis by the m.2 devices is much higher than that of PCIE devices. In some cases, the expansion of the m.2 device requires a switching device that uses PCIE to m.2.

As shown in fig. 1, which is a schematic diagram of an interface expansion circuit in the prior art, a PCIE bridge is used to connect a PCIE interface with an m.2, the PCIE bridge is a PCIE expansion chip, one input network port may output multiple network ports, for example, an input of one X4 is then turned out of two X4 interfaces, and all PCIE expansion is performed through the PCIE bridge; under the condition that a PCIE bridge is not used, a slot of one PCIE X8 can be converted into a slot of one M.2 (PCIE X4), and then resources of one PCIE X4 are wasted, and when the PCIE bridge is used for converting into slots of two M.2 (PCIE X4), the implementation is complex, and a lot of cost is increased, so that the expansion of an interface can be realized, the cost can be saved, and the problem which needs to be solved urgently at present is solved.

Disclosure of Invention

Aiming at the technical problems, the embodiment of the utility model provides an interface expansion device.

The embodiment of the utility model provides an interface expansion device, which at least comprises a PCIE connector, a clock control module and a plurality of M.2 connectors, wherein the PCIE connector is respectively connected with the plurality of M.2 connectors through the clock control module;

the data lines of the PCIE connectors are respectively connected with the M.2 connectors;

the PCIE connector clock signal is connected with the input clock signal of the clock control module; and a plurality of output clock signals of the clock control module are respectively connected with the M.2 connectors.

Optionally, the number of m.2 connectors is two.

Optionally, the first data line, the second data line, the third data line and the fourth data line of the PCIE connector are respectively connected to the first m.2 connector.

Optionally, the fourth data line, the fifth data line, the sixth data line and the seventh data line of the PCIE connector are respectively connected to the second m.2 connector.

Optionally, the clock control module includes four output clock signals.

Optionally, the first output clock signal of the clock control module is connected to the first m.2 connector.

Optionally, a second output clock signal of the clock control module is connected to a second m.2 connector.

Optionally, the clock control module is a CLB53156 chip.

Optionally, the clock control module is an SI53156 chip.

Optionally, the interface expansion device further comprises a power supply interface, and the power supply interface is used for being connected with a power supply circuit.

In the technical scheme provided by the embodiment of the utility model, the interface expansion device at least comprises a PCIE connector, a clock control module and a plurality of M.2 connectors, wherein the PCIE connector is respectively connected with the plurality of M.2 connectors through the clock control module; the data lines of the PCIE connectors are respectively connected with a plurality of M.2 connectors; the PCIE connector clock signal is connected with the input clock signal of the clock control module; the multiple output clock signals of the clock control module are respectively connected with the multiple M.2 connectors, and the PCIE bridge is not used in the embodiment of the utility model, so that the slot of one PCIE X8 can be converted into the slots of two M.2 (PCIE X4), and the utility model has the advantages of simple structure, low cost, high expansibility and high density design.

Drawings

FIG. 1 is a prior art interface expansion circuit schematic;

FIG. 2 is a schematic structural diagram of an interface expansion device according to an embodiment of the present utility model;

fig. 3 is a schematic structural diagram of another interface expansion device according to an embodiment of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to fall within the scope of the utility model.

Referring to fig. 2, a schematic structural diagram of an interface expansion device according to an embodiment of the present utility model is shown, where the interface expansion device at least includes a PCIE connector 101, a clock control module 102, and a plurality of m.2 connectors 103, where the PCIE connector 101 is connected to the plurality of m.2 connectors 103 through the clock control module 102 respectively;

the data lines of the PCIE connector 101 are respectively connected to the m.2 connectors 103;

the clock signal of the PCIE connector 101 is connected to the input clock signal of the clock control module 102;

the plurality of output clock signals of the clock control module 102 are respectively connected to a plurality of m.2 connectors 103.

The number of the m.2 connectors may be two or three or more.

PCIe has many improvements over previous standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical size, better bus device performance scaling, more detailed error detection and reporting mechanisms (advanced error reporting, AER) and native hot plug functionality. Newer versions of the PCIe standard provide hardware support for I/O virtualization.

PCI Express electrical interfaces are also used in a variety of other standards, most notably ExpressCard, which is a notebook expansion card interface, and SATA Express, which is a computer storage interface.

The PCI Express 2.0 specification has been significantly upgraded mainly in data transmission speed from the previous 2.5GT/s bus frequency doubling to 5GT/s, that is, the previous PCI Express 2.0x16 interface can double to a surprisingly 8GB/s bus bandwidth (1 GB/s=8 Gbps).

The PCI Express bus frequency is improved, namely the data transmission rate of each serial line is doubled from 2.5Gbps to 5Gbps, and the bandwidth is doubled. The PCI Express power supply system can better support future high-end display cards, and even if the power consumption reaches 225W or 300W, only PCI Express is needed to supply power independently. PCI Express bus is a high-speed serial replacement for older PCI/PCI-X buses. One of the main differences between the PCI Express bus and the old PCI is the bus topology. PCI uses a shared parallel bus architecture in which the PCI host and all devices share a common set of address, data, and control lines. In contrast, PCI Express is based on a point-to-point topology, with a separate serial link connecting each device to the root system (host). Due to its shared bus topology, the PCI bus in a single direction can be arbitrated (in the case of multiple hosts) and limited to one host at a time. In addition, the old PCI clock scheme limits the bus clock to the slowest peripherals on the bus (regardless of the devices involved in the bus transaction). In contrast, a PCI Express bus link supports full duplex communication between any two endpoints, while concurrent access across multiple endpoints is not inherently limited.

In terms of bus protocol, PCI Express communications are encapsulated in data packets. The task of packing and unpacking data and status message traffic is handled by the transaction layer of the PCI Express port, and the fundamental differences in electrical signals and bus protocols require the use of different mechanical form factors and expansion connectors (thus, new motherboard and new adapter boards are required); the PCI slots and PCI Express slots are not interchangeable. At the software level, PCI Express retains backward compatibility with PCI; conventional PCI system software can detect and configure newer PCI Express devices without explicit support of the PCI Express standard, but the new PCI Express functions are not accessible. The PCI Express link between two devices may consist of 1 to 32 lanes. In a multi-lane link, packet data is striped across lanes, and peak data throughput is proportional to the overall link width. The channel count is auto-negotiated during device initialization and may be limited by either endpoint. For example, a single channel PCI Express (x 1) card may be inserted into a multi-channel slot (x 4, ×8, etc.), and an initialization period auto-negotiates the highest number of channels supported by each other. The link may dynamically auto-configure itself to provide fault tolerance in the presence of bad or unreliable channels using fewer channels. The PCI Express standard defines a number of widths of slots and connectors:. Times.1,. Times.4,. Times.8,. Times.12,. Times.16, and. Times.32. This allows the PCI Express bus to serve cost-sensitive applications that do not require high throughput, as well as applications that are critical to performance such as 3D graphics, networking (tera Ethernet or multiport gigabit Ethernet), and enterprise-level storage (SAS or fibre channel).

According to the interface types, the M.2 interfaces can be divided into Socket 2 and Socket 3;

socket 2 may also be called B key, supporting sata, pcie x2;

socket 3 may also be called M key, supporting sata, pcie x4.

Fig. 3 is a schematic structural diagram of an interface expansion device according to an embodiment of the present utility model, as shown in fig. 2, in which the number of m.2 connectors is two.

The first data line, the second data line, the third data line and the fourth data line of the PCIE connector are respectively connected with the first m.2 connector, and the fourth data line, the fifth data line, the sixth data line and the seventh data line of the PCIE connector are respectively connected with the second m.2 connector.

Optionally, the clock control module includes four output clock signals, and a first output clock signal of the clock control module is connected to the first m.2 connector; the second output clock signal of the clock control module is connected with the second M.2 connector.

The number of the output clock signals of the clock control module is not limited in the embodiment of the utility model, and can be set according to the attribute of the chip or the requirement of a user.

Optionally, the clock control module is a CLB53156 chip.

Clock generator CLG52147 PCIe can provide 9 paths of 100MHz independent LP-HCSL Clock outputs with RMS Jitter typically only 10fs under PCIe Gen 5.0Common Clock architecture; the Clock Buffer CLB53156 can provide 6-way PCIe 5.0 compatible output, and the additional jitter is only 6fs under the PCIe Gen 5.0Common Clock architecture; clock Buffer CLBs 53302/53305 may provide up to 10 arbitrary forms of differential or 20 arbitrary forms of single ended outputs and two independent sets of 1/2/4 divided frequencies, with 100MHz input clocks, two independent sets (each set of 5 differential or 10 single ended) of 100MHz, 50MHz or 25MHz clocks may be output.

Optionally, the clock control module is an SI53156 chip.

The voltage is 3.135V-3.465V.

Optionally, the interface expansion device further comprises a power supply interface, and the power supply interface is used for connecting with a power supply circuit.

Through comparison, the utility model does not need PCIE bridge and requires less CLK resources. The X8 signal from the PCIE slot is split into two PCIE X4 signals that are directly connected to the m.2 connector. The CLK signal input by the PCIE slot then outputs two CLK signals through one CLK BUFFER, which are connected to two m.2 respectively.

In the case of using one m.2, the installation to any slot does not affect the use of the device.

In the case of using two m.2, in order to ensure that the two m.2 can operate normally, the PCIE slot needs to be set to the two X4 modes under the BIOS. This limitation is not already a problem for current computers, and the BIOS typically has this option for the user to configure.

The PCIE bridge, the peripheral matched power supply circuit and the heat dissipation cost of the PCIE bridge can be saved in the material cost. Space occupied by the materials can be saved on the PCB, and the utilization rate of the whole PCB is improved. The design of the whole board card can find that only a clock buffer and a power supply circuit are arranged on the board card, so that the board card is relatively simple.

Compared with the scheme of converting one PCIE X8 slot into one M.2, the method only increases the cost of one CLK BUFFER, but obtains 2 expansion slots of the M.2, thereby realizing higher expansion and space utilization rate of one PCIE X8.

In the technical scheme provided by the embodiment of the utility model, the interface expansion device at least comprises a PCIE connector, a clock control module and a plurality of M.2 connectors, wherein the PCIE connector is respectively connected with the plurality of M.2 connectors through the clock control module; the data lines of the PCIE connectors are respectively connected with a plurality of M.2 connectors; the PCIE connector clock signal is connected with the input clock signal of the clock control module; the multiple output clock signals of the clock control module are respectively connected with the multiple M.2 connectors, and the embodiment of the utility model realizes that the slot of one PCIE X8 can be converted into the slots of two M.2 (PCIE X4) without using PCIE bridges, and the two slots are connected togetherSimple structure, low cost, high expansibility and high density design _。

The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.

Claims

1. An interface expansion device, characterized in that: the interface expansion device at least comprises a PCIE connector, a clock control module and a plurality of M.2 connectors, wherein the PCIE connector is respectively connected with the plurality of M.2 connectors through the clock control module;

the PCIE connector clock signal is connected with the input clock signal of the clock control module;

and a plurality of output clock signals of the clock control module are respectively connected with the M.2 connectors.

2. The interface extension device of claim 1, wherein the number of m.2 connectors is two.

3. The interface expansion device of claim 2, wherein the first data line, the second data line, the third data line, and the fourth data line of the PCIE connector are respectively connected to the first m.2 connector.

4. The interface expansion device of claim 3, wherein the fourth data line, the fifth data line, the sixth data line, and the seventh data line of the PCIE connector are respectively connected to the second m.2 connector.

5. The interface expansion device of claim 4, wherein the clock control module comprises four output clock signals.

6. The interface expansion device of claim 5, wherein the first output clock signal of the clock control module is coupled to a first m.2 connector.

7. The interface expansion device of claim 6, wherein the second output clock signal of the clock control module is coupled to a second m.2 connector.

8. The interface expansion device of claim 1, wherein the clock control module is a CLB53156 chip.

9. The interface expansion device of claim 1, wherein the clock control module is an SI53156 chip.

10. The interface extension device of claim 1, further comprising a power interface for connecting to a power circuit.