CN220138302U - Power bridge stack with high heat dissipation performance - Google Patents
Power bridge stack with high heat dissipation performance Download PDFInfo
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- CN220138302U CN220138302U CN202321638500.9U CN202321638500U CN220138302U CN 220138302 U CN220138302 U CN 220138302U CN 202321638500 U CN202321638500 U CN 202321638500U CN 220138302 U CN220138302 U CN 220138302U
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- chip
- chip carrier
- alternating current
- carrier plate
- heat dissipation
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- 230000017525 heat dissipation Effects 0.000 title claims abstract description 36
- 239000004593 Epoxy Substances 0.000 claims abstract description 27
- 238000004806 packaging method and process Methods 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 18
- 239000000741 silica gel Substances 0.000 claims abstract description 18
- 229910002027 silica gel Inorganic materials 0.000 claims abstract description 18
- 230000035882 stress Effects 0.000 description 10
- 230000007774 longterm Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 4
- 238000012858 packaging process Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The power bridge stack with high heat dissipation performance comprises an epoxy packaging body, a first chip, a second chip, a third chip, a fourth chip, a fifth chip and a sixth chip, an anode chip carrier, a cathode chip carrier, a first alternating current chip carrier, a second alternating current chip carrier and a third alternating current chip carrier; the first chip, the second chip and the third chip are arranged on the positive electrode chip carrier plate, the fourth chip is arranged on the first alternating current chip carrier plate, the fifth chip is arranged on the second alternating current chip carrier plate, and the sixth chip is arranged on the third alternating current chip carrier plate; the epoxy packaging body also comprises a heat-conducting silica gel sheet and a metal radiating fin, the lower surface of each chip carrier plate is in contact fit with the upper surface of the heat-conducting silica gel sheet, the lower surface of the heat-conducting silica gel sheet is in contact fit with the upper surface of the metal radiating fin, and the lower surface of the metal radiating fin is partially or completely exposed to the outside. The bridge pile has high heat dissipation performance.
Description
Technical Field
The utility model relates to the field of semiconductor equipment, in particular to a power bridge stack with high heat dissipation performance.
Background
On one hand, the product needs to bear large current for a long time to work, and is one of main heating elements on a device board card, so that good heat radiation performance is one of main technical indexes; on the other hand, the high-power bridge stack product needs to package a large-size chip, and the stress of a package structure is an important factor causing the product to fail, and the stress born by the chip comprises the cold and hot impact in the process and the internal stress generated by long-term use of the terminal product under the high-temperature/low-temperature condition.
Therefore, the problems faced by the existing bridge pile products have two points, firstly, the heat dissipation performance of the products is not ideal enough, the heat dissipation performance of the whole machine is improved by adopting larger heat dissipation fins or stronger convection conditions of a chassis in a whole machine factory, and the heat dissipation problem is more prominent when the equipment works under severe high-temperature conditions; secondly, the product packaging structure has large stress, and thermal stress and mechanical stress in the packaging process have the risk of causing potential damage to the chip, so that the product failure is more likely to occur in the later stage under severe use conditions.
In view of the foregoing, it is desirable to provide a power bridge stack having high heat dissipation and reduced structural stresses.
Disclosure of Invention
The utility model aims to provide a power bridge stack with high heat dissipation performance.
The technical scheme adopted by the utility model is as follows: a power bridge stack with high heat dissipation performance comprises an epoxy packaging body, a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip and a plurality of chip carrier plates for bearing chips, wherein the first chip, the second chip, the third chip, the fourth chip, the fifth chip and the sixth chip are coated in the epoxy packaging body;
the chip carrier comprises a positive electrode chip carrier, a negative electrode chip carrier, a first alternating current chip carrier, a second alternating current chip carrier and a third alternating current chip carrier;
the first chip, the second chip and the third chip are all arranged on the positive electrode chip carrier plate, and the negative electrode surfaces of the three chips are electrically connected with the upper surface of the positive electrode chip carrier plate; the fourth chip is arranged on the first alternating current chip carrier plate, and the negative electrode surface of the fourth chip is electrically connected with the upper surface of the first alternating current chip carrier plate; the fifth chip is arranged on the second alternating current chip carrier plate, and the negative electrode surface of the fifth chip is electrically connected with the upper surface of the second alternating current chip carrier plate; the sixth chip is arranged on the third alternating current chip carrier plate, and the negative electrode surface of the sixth chip is electrically connected with the upper surface of the third alternating current chip carrier plate;
the positive electrode surface of the first chip is electrically connected with the upper surface of the first alternating current chip carrier plate through a connecting sheet, the positive electrode surface of the second chip is electrically connected with the upper surface of the second alternating current chip carrier plate through a connecting sheet, the positive electrode surface of the third chip is electrically connected with the upper surface of the third alternating current chip carrier plate through a connecting sheet, and the positive electrode surfaces of the fourth chip, the fifth chip and the sixth chip are respectively electrically connected with the upper surface of the negative electrode chip carrier plate through a connecting sheet;
the epoxy packaging body further comprises a heat-conducting silica gel sheet and metal radiating fins, the lower surface of each chip carrier plate is in contact fit with the upper surface of the heat-conducting silica gel sheet, the lower surface of the heat-conducting silica gel sheet is in contact fit with the upper surface of the metal radiating fins, and the lower surface of the metal radiating fins is exposed to the outside.
According to a further technical scheme, the first alternating current chip carrier plate, the second alternating current chip carrier plate and the third alternating current chip carrier plate are sequentially arranged at intervals along the length direction of the epoxy packaging body, and the negative electrode chip carrier plate is arranged between the positive electrode chip carrier plate and each alternating current chip carrier plate.
According to a further technical scheme, the first chip, the second chip and the third chip are arranged on the positive electrode chip carrier plate at intervals along the length direction of the epoxy packaging body.
According to a further technical scheme, the positive electrode chip carrier plate comprises a main body part used for connecting the first chip, the second chip and the third chip, and further comprises an extension part which extends outwards from the epoxy packaging body to serve as a positive electrode pin.
According to a further technical scheme, the negative electrode chip carrier plate comprises a main body part and an extension part, wherein the main body part is arranged between the positive electrode chip carrier plate and each alternating current chip carrier plate and is used for connecting the connecting sheet, and the extension part extends outwards from the epoxy packaging body to serve as a negative electrode pin.
According to a further technical scheme, the first alternating current chip carrier plate, the second alternating current chip carrier plate and the third alternating current chip carrier plate all comprise a main body part and an extension part which extends outwards from the epoxy packaging body to serve as an alternating current end pin.
According to a further technical scheme, the thickness of the heat-conducting silica gel sheet is 0.1mm to 0.3mm.
According to a further technical scheme, the thickness of the metal radiating fin is 0.4mm to 0.8mm.
The utility model has the beneficial effects that: the power bridge stack with high heat dissipation performance can avoid the problem of unsmooth heat dissipation caused by the concentration of the heating positions of a plurality of chips in the prior art by the distributed design of the chip carrier plate and the arrangement of the heat conducting silica gel sheet and the metal heat dissipation sheet on the basis of realizing high power, and improves the heat dissipation speed and the heat dissipation performance of the whole product; meanwhile, through arrangement and arrangement of the chip, the carrier plate and other structures, structural stress generated in the packaging process and the long-term use process of the product is reduced, and the stability of the product in the long-term use process is improved.
Drawings
FIG. 1 is a schematic diagram of an embodiment of the present utility model;
fig. 2 is a side view of an embodiment of the present utility model.
In the above figures: 1. an epoxy encapsulation; 21. a first chip; 22. a second chip; 23. a third chip; 24. a fourth chip; 25. a fifth chip; 26. a sixth chip; 3. a positive electrode chip carrier plate; 41. a first alternating current chip carrier plate; 42. the second alternating current chip carrier plate; 43. a third alternating current chip carrier plate; 5. a negative electrode chip carrier plate; 6. a connecting sheet; 71. a positive electrode pin; 72. a negative electrode pin; 73. an alternating current end pin; 8. a thermally conductive silicone sheet; 9. a metal heat sink.
Description of the embodiments
The utility model is further described below with reference to the accompanying drawings and examples:
the present utility model will be described in detail with reference to the drawings, wherein modifications and variations are possible in light of the teachings of the present utility model, without departing from the spirit and scope of the present utility model, as will be apparent to those of skill in the art upon understanding the embodiments of the present utility model.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. Singular forms such as "a," "an," "the," and "the" are intended to include the plural forms as well, as used herein.
The terms "first," "second," and the like, as used herein, do not denote a particular order or sequence, nor are they intended to be limiting, but rather are merely used to distinguish one element or operation from another in the same technical term.
As used herein, "connected" or "positioned" may refer to two or more components or devices in physical contact with each other, or indirectly, or in operation or action with each other.
As used herein, the terms "comprising," "including," "having," and the like are intended to be open-ended terms, meaning including, but not limited to.
The term (terms) as used herein generally has the ordinary meaning of each term as used in this field, in this disclosure, and in the special context, unless otherwise noted. Certain terms used to describe the disclosure are discussed below, or elsewhere in this specification, to provide additional guidance to those skilled in the art in light of the description of the disclosure.
The terms "front", "rear", "upper", "lower", "left", "right" and the like used herein are directional terms, and are merely used to describe positional relationships among the structures in the present application, and are not intended to limit the scope of the present application and the specific direction in actual implementation.
As shown in the embodiments of fig. 1 and 2, a power bridge stack with high heat dissipation performance is provided, which is mainly applied to industrial control, charging piles and automotive electronics, and the power bridge stack comprises an epoxy package body 1, a first chip 21, a second chip 22, a third chip 23, a fourth chip 24, a fifth chip 25, a sixth chip 26 and a plurality of chip carrier boards for carrying chips, wherein the first chip 21, the second chip 22, the third chip 23, the fourth chip 24, the fifth chip 25 and the sixth chip 26 are wrapped in the epoxy package body 1.
The chip carrier includes a positive chip carrier 3, a negative chip carrier 5, a first ac chip carrier 41, a second ac chip carrier 42, and a third ac chip carrier 43.
The first chip 21, the second chip 22 and the third chip 23 are all arranged on the positive electrode chip carrier plate 3, and the negative electrode surfaces of the three chips are electrically connected with the upper surface of the positive electrode chip carrier plate 3 in a downward facing manner; the fourth chip 24 is disposed on the first ac chip carrier 41, and the negative electrode surface of the fourth chip 24 faces downward to be electrically connected to the upper surface of the first ac chip carrier 41; the fifth chip 25 is disposed on the second ac chip carrier 42, and the negative electrode surface of the fifth chip 25 faces downward to be electrically connected to the upper surface of the second ac chip carrier 42; the sixth chip 26 is disposed on the third ac chip carrier 43, and the negative electrode surface of the sixth chip 26 is electrically connected to the upper surface of the third ac chip carrier 43.
Therefore, the positive electrode surfaces of the 6 chips are uniformly upward, and the problem that the chip protection ring area bears larger structural stress due to the fact that the positive electrode surfaces of the 6 chips face downward due to the reverse discharge of the chips is avoided.
The semiconductor device further comprises six connecting pieces 6, wherein the positive electrode surface of the first chip 21 is electrically connected with the upper surface of the first ac chip carrier 41 through a connecting piece 6, the positive electrode surface of the second chip 22 is electrically connected with the upper surface of the second ac chip carrier 42 through a connecting piece 6, the positive electrode surface of the third chip 23 is electrically connected with the upper surface of the third ac chip carrier 43 through a connecting piece 6, and the positive electrode surfaces of the fourth chip 24, the fifth chip 25 and the sixth chip 26 are respectively electrically connected with the upper surface of the negative electrode chip carrier 5 through a connecting piece 6.
In this embodiment, the first ac chip carrier 41, the second ac chip carrier 42, and the third ac chip carrier 43 are sequentially arranged at intervals along the length direction of the epoxy package 1, and the negative chip carrier 5 is disposed between the positive chip carrier 3 and each ac chip carrier.
Therefore, the 6 chips are respectively lapped with the independent connecting sheets 6, so that the problem that the stress ratio of the chips is also high due to the fact that the connecting sheets are large in size and large in deformation after thermal expansion caused by the fact that the connecting sheets are commonly used by 3 chips in the existing structure is avoided; meanwhile, the chip carrier plates are arranged in a scattered mode, the heat dissipation area is maximized, heat generated by 6 chips can be rapidly led out to the external radiating fins, the positions of the chips are evenly distributed, the heat dissipation problem caused by the fact that the heating positions of the chips are concentrated is avoided, and therefore the heat dissipation performance is improved.
The epoxy package 1 further includes a heat-conducting silica gel sheet 8 and a metal heat sink 9, the lower surfaces of the chip carriers (i.e., the positive chip carrier 3, the negative chip carrier 5, the first ac chip carrier 41, the second ac chip carrier 42 and the third ac chip carrier 43) are in contact fit with the upper surface of the heat-conducting silica gel sheet 8, the lower surface of the heat-conducting silica gel sheet 8 is in contact fit with the upper surface of the metal heat sink 9, and the lower surface of the metal heat sink 9 is partially or fully exposed to the outside to play a heat dissipation effect.
In this embodiment, the thickness of the heat-conducting silica gel sheet 8 is 0.15mm, and the thickness of the metal radiating fin 9 is 0.5mm, so that the insulating high-heat-conducting silica gel sheet with the thickness of 0.15mm is matched with the metal radiating fin 9 with the thickness of 0.5mm, the epoxy resin layer with the thickness of about 1.0mm of the back plate of the chip in the existing structure is replaced, the heat conducting performance from the chip to the medium material of the external radiating fin is improved, and meanwhile, the heat conducting path is shortened, so that the heat radiating capacity of the packaging structure is improved by several times.
In this embodiment, the first chip 21, the second chip 22, and the third chip 23 are arranged on the positive electrode chip carrier 3 at intervals along the length direction of the epoxy package 1, so that the heat dissipation performance can be improved by the distributed design of the chips.
In this embodiment, the positive electrode chip carrier 3 includes a main body portion for connecting the first chip 21, the second chip 22, and the third chip 23, and further includes an extension portion that extends out from the inside of the epoxy package 1 as the positive electrode pin 71.
In this embodiment, the negative electrode chip carrier 5 includes a main body portion and an extension portion, the main body portion is disposed between the positive electrode chip carrier 3 and each of the ac chip carriers, and is used for connecting the connection piece 6, and the extension portion extends out from the interior of the epoxy package 1 to serve as a negative electrode pin 72.
In this embodiment, the first ac chip carrier 41, the second ac chip carrier 42, and the third ac chip carrier 43 each include a main body portion for connecting the corresponding chips, and an extension portion extending from the inside of the epoxy package 1 to the outside as an ac terminal pin 73.
In summary, the power bridge stack with high heat dissipation performance can avoid the problem of unsmooth heat dissipation caused by concentrated heating positions of a plurality of chips in the prior art by the distributed design of the chip carrier plate and the arrangement of the heat conducting silica gel sheet 8 and the metal heat dissipation sheet 9 on the basis of realizing high power, and improves the whole heat dissipation speed and heat dissipation performance of the product; meanwhile, through arrangement and arrangement of the chip, the carrier plate and other structures, structural stress generated in the packaging process and the long-term use process of the product is reduced, and the stability of the product in the long-term use process is improved.
The above embodiments are provided to illustrate the technical concept and features of the present utility model and are intended to enable those skilled in the art to understand the content of the present utility model and implement the same, and are not intended to limit the scope of the present utility model. All equivalent changes or modifications made in accordance with the spirit of the present utility model should be construed to be included in the scope of the present utility model.
Claims (8)
1. A power bridge stack with high heat dissipation performance is characterized in that:
the packaging structure comprises an epoxy packaging body (1), a first chip (21), a second chip (22), a third chip (23), a fourth chip (24), a fifth chip (25), a sixth chip (26) and a plurality of chip carrier plates for bearing chips, wherein the first chip, the second chip (22), the third chip (23), the fourth chip (24), the fifth chip (25) and the sixth chip carrier plates are coated in the epoxy packaging body (1);
the chip carrier comprises a positive electrode chip carrier (3), a negative electrode chip carrier (5), a first alternating current chip carrier (41), a second alternating current chip carrier (42) and a third alternating current chip carrier (43);
the first chip (21), the second chip (22) and the third chip (23) are all arranged on the positive electrode chip carrier plate (3), and the negative electrode surfaces of the three chips are electrically connected with the upper surface of the positive electrode chip carrier plate (3); the fourth chip (24) is arranged on the first alternating current chip carrier plate (41), and the negative electrode surface of the fourth chip (24) is electrically connected with the upper surface of the first alternating current chip carrier plate (41); the fifth chip (25) is arranged on the second alternating current chip carrier plate (42), and the negative electrode surface of the fifth chip (25) is electrically connected with the upper surface of the second alternating current chip carrier plate (42); the sixth chip (26) is arranged on the third alternating current chip carrier plate (43), and the negative electrode surface of the sixth chip (26) is electrically connected with the upper surface of the third alternating current chip carrier plate (43);
the positive electrode surface of the first chip (21) is electrically connected with the upper surface of the first alternating current chip carrier plate (41) through one connecting sheet (6), the positive electrode surface of the second chip (22) is electrically connected with the upper surface of the second alternating current chip carrier plate (42) through one connecting sheet (6), the positive electrode surface of the third chip (23) is electrically connected with the upper surface of the third alternating current chip carrier plate (43) through one connecting sheet (6), and the positive electrode surfaces of the fourth chip (24), the fifth chip (25) and the sixth chip (26) are respectively electrically connected with the upper surface of the negative electrode chip carrier plate (5) through one connecting sheet (6);
the epoxy packaging body (1) further comprises a heat conduction silica gel sheet (8) and metal radiating fins (9), the lower surface of each chip carrier plate is in contact fit with the upper surface of the heat conduction silica gel sheet (8), the lower surface of the heat conduction silica gel sheet (8) is in contact fit with the upper surface of the metal radiating fins (9), and the lower surface of the metal radiating fins (9) is exposed to the outside.
2. A power bridge stack with high heat dissipation as recited in claim 1, wherein: the first alternating current chip carrier plates (41), the second alternating current chip carrier plates (42) and the third alternating current chip carrier plates (43) are sequentially arranged at intervals along the length direction of the epoxy packaging body (1), and the negative electrode chip carrier plates (5) are arranged between the positive electrode chip carrier plates (3) and the alternating current chip carrier plates.
3. A power bridge stack having high heat dissipation as recited in claim 2, wherein: the first chip (21), the second chip (22) and the third chip (23) are arranged on the positive electrode chip carrier plate (3) at intervals along the length direction of the epoxy packaging body (1).
4. A power bridge stack with high heat dissipation as recited in claim 1, wherein: the positive chip carrier plate (3) comprises a main body part for connecting the first chip (21), the second chip (22) and the third chip (23), and further comprises an extension part which extends outwards from the inside of the epoxy packaging body (1) and serves as a positive pin (71).
5. A power bridge stack with high heat dissipation as recited in claim 1, wherein: the negative electrode chip carrier plate (5) comprises a main body part and an extension part, wherein the main body part is arranged between the positive electrode chip carrier plate (3) and each alternating current chip carrier plate and is used for connecting the connecting sheet (6), and the extension part extends outwards from the inside of the epoxy packaging body (1) to serve as a negative electrode pin (72).
6. A power bridge stack with high heat dissipation as recited in claim 1, wherein: the first alternating current chip carrier plate (41), the second alternating current chip carrier plate (42) and the third alternating current chip carrier plate (43) comprise a main body part and an extension part which extends outwards from the inside of the epoxy packaging body (1) and serves as an alternating current end pin (73).
7. A power bridge stack with high heat dissipation as recited in claim 1, wherein: the thickness of the heat-conducting silica gel sheet (8) is 0.1mm to 0.3mm.
8. A power bridge stack with high heat dissipation as recited in claim 1, wherein: the thickness of the metal radiating fin (9) is 0.4mm to 0.8mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321638500.9U CN220138302U (en) | 2023-06-27 | 2023-06-27 | Power bridge stack with high heat dissipation performance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321638500.9U CN220138302U (en) | 2023-06-27 | 2023-06-27 | Power bridge stack with high heat dissipation performance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220138302U true CN220138302U (en) | 2023-12-05 |
Family
ID=88953596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321638500.9U Active CN220138302U (en) | 2023-06-27 | 2023-06-27 | Power bridge stack with high heat dissipation performance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220138302U (en) |
-
2023
- 2023-06-27 CN CN202321638500.9U patent/CN220138302U/en active Active
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