CN220066957U - Charging power supply management chip and terminal equipment - Google Patents
Charging power supply management chip and terminal equipment Download PDFInfo
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- CN220066957U CN220066957U CN202321674779.6U CN202321674779U CN220066957U CN 220066957 U CN220066957 U CN 220066957U CN 202321674779 U CN202321674779 U CN 202321674779U CN 220066957 U CN220066957 U CN 220066957U
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Abstract
The present disclosure relates to a charging power management chip and a terminal device, the charging power management chip includes: the power supply power part pins are arranged in a first area on the first side of the charging power management chip, and the power supply power part pins are pins for connecting an external power supply power device; the analog part pins are arranged in a second area of the second side of the charging power supply management chip, the first side is opposite to the second side, and the analog part pins are used for connecting an external analog control device; the digital part pins are arranged between the first area and the second area and are used for being connected with an external digital control device. Therefore, the distance between the external power supply power device connected with the pins of the power supply power part and the external analog control device connected with the pins of the analog part is increased, and the influence of high-frequency signals generated when the external power supply power device works on the detection result of the external analog control device is reduced.
Description
Technical Field
The disclosure relates to the field of charging power management chips, and in particular relates to a charging power management chip and terminal equipment.
Background
The power management chip is a chip which plays roles in converting, distributing, detecting and other power management of the power in the electronic equipment system, and is mainly responsible for identifying the power supply amplitude of a central processing unit (Central Processing Unit, CPU), generating corresponding short moment waves and pushing a later-stage circuit to output power.
Disclosure of Invention
To overcome the problems in the related art, an aspect of an embodiment of the present disclosure provides a charging power management chip.
The charging power management chip includes:
the power supply power part pins are arranged in a first area on the first side of the charging power management chip, and the power supply power part pins are pins for connecting an external power supply power device;
the analog part pins are arranged in a second area of the second side of the charging power supply management chip, the first side is opposite to the second side, and the analog part pins are used for connecting an external analog control device;
the digital part pins are arranged between the first area and the second area and are used for being connected with an external digital control device.
Optionally, the power supply power portion pin includes:
the pin of the step-down charging part is used for connecting an external power supply;
the power path management part pin is used for connecting an external direct current power supply and electric equipment;
and the high-voltage protection part pin is used for connecting external wired control equipment.
Optionally, the step-down charging portion pin includes: VBUS pin, PMID pin, SW pin, PGND pin, BST pin and REGN pin; the power path management part pin includes: BAT pin and SYS pin; the high voltage protection part pin includes: VAC pins and OVPGATE pins;
the SYS pins are arranged at the edge of the charging power management chip.
Optionally, the analog part pin includes: EDL pin, NVBUS_OK pin, GND pin, BATN pin, BATP pin, TSBAT pin, TSBUS pin and BAT_ID pin;
wherein the TSBAT pin is adjacent to the BATN pin, or the TSBAT pin is adjacent to the BATP pin.
Optionally, the digital portion pin includes: nQON pin, CC1 pin, CC2 pin, VCONN pin, nINT pin, DM pin, DP pin, PD_nINT pin, SDA pin, and SCL pin.
Optionally, the charging power management chip further includes:
the LED part pins are arranged between the first area and the second area and are used for being connected with external LED lamps.
Optionally, the LED portion pin includes: FLASH_VDD pin, LED1 pin, LED2 pin and Torch_VDD pin;
the FLASH_VDD pin is adjacent to the PMID pin, the LED1 pin is adjacent to the FLASH_VDD pin, the LED2 pin is adjacent to the FLASH_VDD pin, and the Torch_VDD pin is adjacent to the LED2 pin.
Optionally, pins of the charging power management chip are arranged in an array of 6 rows by 7 columns.
Optionally, the first region includes an array region of 6 rows x (1-4) columns and the second region includes an array region of 6 rows x (6-7) columns.
Optionally, the BATN pin, the BAT pin, the TSBUS pin, and the bat_id pin are arranged at the edge of the charging power management chip.
Optionally, the VBUS pin is disposed at an edge of the charging power management chip.
Optionally, the BST pin is adjacent to the SW pin.
Optionally, the REGN pin is arranged in a middle area of the charging power management chip.
Optionally, the EDL pins are arranged in a middle area of the charging power management chip.
Optionally, the nvbus_ok pin is disposed in a middle area of the charging power management chip.
Optionally, the VAC pins are routed at the edge of the charging power management chip.
Optionally, the GND pin is disposed in a middle area of the charging power management chip.
Optionally, the CC1 pins and the CC2 pins are arranged in a middle area of the charging power management chip.
Optionally, the VCONN pin is adjacent to the CC1 pin.
Optionally, the OVPGATE pins are arranged at the edge of the charging power management chip.
Optionally, the nINT pin is disposed in a middle area of the charging power management chip.
Optionally, the DM pin and the DP pin are disposed at an edge of the charging power management chip.
Optionally, the SDA pin and the SCL pin are arranged at an edge of the charging power management chip.
Another aspect of the embodiments of the present disclosure further provides a terminal device, including a charging power management chip as described above.
The technical scheme provided by the embodiment of the disclosure can comprise the following beneficial effects: the power supply power part pins are arranged in a first area on the first side of the charging power supply management chip, the analog part pins are arranged in a second area on the second side of the charging power supply management chip, and the digital part pins are arranged between the first area and the second area, so that the distance between an external power supply power device connected with the power supply power part pins and an external analog control device connected with the analog part pins is increased, and the influence of high-frequency signals generated during the operation of the external power supply power device on the detection result of the external analog control device is weakened.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 is a schematic diagram of a charging power management chip according to an exemplary embodiment.
Fig. 2 is a schematic diagram illustrating a charging power management chip pin location according to another exemplary embodiment.
Fig. 3 is a schematic diagram of a charging power management chip circuit, according to an example embodiment.
Description of the reference numerals
101. First region 102 second region 3 low dropout linear regulator
4. Step-down controller 5 Power Path management controller
Analog controller of 6LED controller 7 analog-to-digital converter 8
9. Digital signal processor 10 driver 11 adapter
12. Wireless port 100 charging power management chip
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present disclosure as detailed in the accompanying claims.
It should be noted that, all actions for acquiring signals, information or data in the present disclosure are performed under the condition of conforming to the corresponding data protection rule policy of the country of the location and obtaining the authorization given by the owner of the corresponding device.
Since the external power device connected to the power supply power part pin of the charging power management chip generates a high-frequency signal during operation, the reference voltage is increased during operation of the external analog control device connected to the power supply power part pin, and thus the error of the detection result of the external analog control device is increased, for example, the equipment connected to the analog part pin for measuring the temperature of the charging interface is affected by the high-frequency signal, and the detected temperature is higher than the actual value. The scheme provides a pin map design scheme of the chip aiming at the defects.
Fig. 1 is a schematic diagram of a charging power management chip according to an exemplary embodiment. As shown in fig. 1, the first side of the charging power management chip 100 is opposite to the second side, and in the embodiment of fig. 1, the first side is the left side of the charging power management chip 100, and the second side is the right side of the charging power management chip 100. The charging power management chip 100 includes a power supply power section pin, an analog section pin, and a digital section pin. The power supply power part pins are arranged in a first area 101 on the first side of the charging power management chip 100, and the power supply power part pins are pins for connecting an external power supply power device; the analog part pins are arranged in a second area 102 on the second side of the charging power management chip 100, and the analog part pins are used for connecting with an external analog control device; the digital portion pins are disposed between the first area 101 and the second area 102, and are pins for connecting to an external digital control device.
As described above, the external power device to which the power supply portion pin is connected generates a high frequency signal when it is operated, resulting in an increase in reference voltage when the external analog control device to which the power supply portion pin is connected is operated, thereby resulting in an increase in error in the detection result of the external analog control device. In this scheme, the power supply power part pin is arranged in the first area of the first side of the charging power management chip 100, the analog part pin is arranged in the second area of the second side of the charging power management chip 100, and the digital part pin is arranged between the first area and the second area, so that the external power device and the external analog control device connected with the power supply power part pin and the analog part pin are usually positioned at a far distance from each other in the charging power management chip 100, and the reference voltage of the external analog control device is less influenced by the high-frequency signal generated during the operation of the external power device.
The power supply power part pins are arranged in the first area on the first side of the charging power supply management chip, the analog part pins are arranged in the second area on the second side of the charging power supply management chip, and the digital part pins are arranged between the first area and the second area, so that the distance between an external power supply power device connected with the power supply power part pins and an external analog control device connected with the analog part pins is increased, and the influence of high-frequency signals generated during the operation of the external power supply power device on the detection result of the external analog control device is weakened.
In yet another embodiment, the power supply power section pins include a buck charging section pin, a power path management section pin, and a high voltage protection section pin.
The pin of the step-down charging part is used for connecting an external power supply; the power path management part pins are pins for connecting an external direct current power supply and electric equipment; the high voltage protection part pin is a pin for connecting with external wired control equipment.
The buck charging section pin is used to connect an external power source, such as an external charger. The power path management part pin is used for connecting an external direct current power supply and electric equipment, such as a battery and an inductor. The high-voltage protection part pin is used for connecting an external wired control device, and when the fault occurs, the load and the power supply can be cut off through the external wired control device.
Fig. 2 is a schematic diagram illustrating a charging power management chip pin location according to another exemplary embodiment. In this embodiment, the step-down charging section pin includes: VBUS pin, PMID pin, SW pin, PGND pin, BST pin and REGN pin; the power path management section pin includes: BAT pin and SYS pin; the high voltage protection part pin includes: VAC pins and OVPGATE pins. The SYS pins are arranged at the edge of the charging power management chip.
In the embodiment of fig. 2, the pins of the charging power management chip are laid out in an array of 6 rows by 7 columns.
The pin of the step-down charging part comprises 2 VBUS pins, the VBUS pins are inputs of a charging power management chip and can be connected with an external charger, and a 220V alternating current source is sent to the VBUS pins after passing through the charger. The 2 VBUS pins are arranged in the 1 st column and the 2 nd column of the 1 st row of the charging power management chip (the edge of the charging power management chip 100) in order to connect the external capacitor and the wiring.
The step-down charging portion pins include 2 PMID pins, and the 2 PMID pins are arranged in the 1 st and 2 nd columns of the 2 nd row of the charging power management chip.
The step-down charging part pins comprise 2 SW pins, and the 2 PMID pins are arranged on the 1 st column and the 2 nd column of the 3 rd row of the charging power management chip and are connected with an external inductor.
The step-down charging portion pins include 2 PGND pins, and the 2 PGND pins are arranged in the 1 st and 2 nd columns of the 4 th row of the charging power management chip.
The step-down charging part pins comprise 1 BST pin, and the 1 BST pin is arranged on the 3 rd column of the 3 rd row of the charging power supply management chip and is adjacent to the SW pin arranged on the 2 nd column of the 3 rd row of the charging power supply management chip.
The step-down charging part pin comprises 1 REGN pin, the REGN pin is used for supplying power to the analog part pin and the digital part pin of the charging power management chip, and the 1 REGN pin is arranged on the 3 rd column of the 4 th row of the charging power management chip (the middle area of the charging power management chip).
The power path management part pins comprise 4 BAT pins, the 4 BAT pins are arranged in the 1 st column, the 2 nd column, the 3 rd column and the 4 th column of the 5 th row of the charging power management chip, and the BAT pins are used for being connected with the anode of an external battery.
The power path management part pins comprise 4 SYS pins, the 4 SYS pins are arranged in the 1 st column, the 2 nd column, the 3 rd column and the 4 th column of the 6 th row of the charging power management chip, the SYS pins are connected with the inductor and external electric equipment, and the inductor and the external electric equipment are generally longer in size, so that the SYS pins are arranged at the edge of the charging power management chip, and wiring is facilitated.
The high-voltage protection part pins comprise 1 VAC pin, the 1 VAC pin is arranged on the 5 th column of the 1 st row of the charging power supply management chip, and the 1 VAC pin is arranged on the edge of the charging power supply management chip, so that wiring is facilitated.
The high-voltage protection part pins comprise 1 OVPGATE pin which is arranged on the 6 th column of the 1 st row of the charging power supply management chip and on the edge of the charging power supply management chip, so that the high-voltage protection part pins are convenient to connect with an external wired control device.
In the embodiment, the SYS pins are arranged at the edge of the charging power supply management chip, so that the arrangement of the external inductor connected with the SYS pins is facilitated, and wiring is facilitated.
In yet another embodiment, the analog portion pin includes: EDL pin, NVBUS_OK pin, GND pin, BATN pin, BATP pin, TSBAT pin, TSBUS pin and BAT_ID pin;
wherein the TSBAT pin is adjacent to the BATN pin, or the TSBAT pin is adjacent to the BATP pin.
The simulation part pins comprise 1 EDL pin which is arranged on the 4 th column of the 3 rd row of the charging power supply management chip, the use scene is not more, and the simulation part pins can be arranged in the middle area of the charging power supply management chip.
The analog part pin comprises 1 NVBUS_OK pin which is arranged on the 4 th column of the 4 th row of the charging power management chip, and when the NVBUS_OK pin detects the VBUS voltage in the normal voltage range, the output low level can be arranged in the middle area of the chip.
The analog part pins comprise 1 GND pin which is arranged on the 5 th column of the 3 rd row of the charging power management chip, and the GND pin is the analog ground of the charging power management chip, so that the GND pin needs to be arranged in the middle area of the charging power management chip and adjacent to the analog part pins.
The analog part pins comprise 1 BATN pin which is arranged on the 6 th column of the 3 rd row of the charging power management chip.
The analog part pins comprise 1 BATP pin, and are arranged on the 7 th column of the 3 rd row of the charging power management chip.
The analog part pins comprise 1 TSBAT pin which is arranged on the 6 th column of the 4 th row of the charging power management chip. The BATN pin and the BATP pin are connected with external equipment for detecting the positive and negative ends of the battery, and the TSBAT pin is connected with the external equipment for detecting the temperature of the battery, so that the TSBAT pin and the BATN pin can be adjacently arranged.
The analog part pins comprise 1 TSBUS pin which is arranged on the 7 th column of the 1 st row of the charging power management chip.
The analog part pin comprises 1 BAT_ID pin which is arranged on the 7 th column of the 4 th row of the charging power management chip.
In yet another embodiment, the digital section pin includes: nQON pin, CC1 pin, CC2 pin, VCONN pin, nINT pin, DM pin, DP pin, PD_nINT pin, SDA pin, and SCL pin.
The digital part pins comprise 1 nQON pin which is arranged on the 3 rd column of the 1 st row of the charging power management chip and is a digital control signal pin for controlling the hardware reset of the charging power management chip.
The digital part pins comprise 1 CC1 pin which is arranged on the 5 th column of the 5 th row of the charging power management chip.
The digital part pins comprise 1 CC2 pin which is arranged in the 5 th column of the 4 th row of the charging power management chip, the CC1 pin and the CC2 pin are connected with the Type-C interface, and the wiring requirements of the CC1 pin and the CC2 pin are not high, so that the digital part pins can be arranged in the middle area of the charging power management chip.
The digital part pins comprise 1 VCONN pin which is arranged on the 5 th column of the 6 th row of the charging power management chip and used for supplying power to the Type-C interface. Because the switch tube is connected with the CC1 pin in the charging power management chip, the VCONN pin and the CC1 pin are adjacently arranged.
The digital part pins comprise 1 nINT pin, are arranged on the 6 th column of the 2 nd row of the charging power management chip (the middle area of the charging power management chip) and are used for interrupting the output of the charging power management chip.
The digital part pins comprise 1 DM pin, and are arranged on the 6 th column of the 6 th row of the charging power management chip. The digital part pins comprise 1 DP pin which is arranged on the 6 th column of the 5 th row of the charging power management chip. The DM pins and the DP pins are used for detecting the charging type, are arranged at the edge of the charging power supply management chip, are convenient to connect with the outside, and are convenient to wire.
The digital part pin comprises 1 PD_nINT pin, which is arranged on the 7 th column of the 2 nd row of the charging power management chip.
The digital part pins comprise 1 SDA pin which is arranged on the 7 th column of the 5 th row of the charging power management chip. The digital part pins comprise 1 SCL pin which is arranged on the 7 th column of the 6 th row of the charging power management chip. The SDA pin and the SCL pin are arranged at the edge of the charging power management chip, so that wiring is facilitated.
In yet another embodiment, the charging power management chip further includes an LED portion pin. The LED part pins are arranged between the first area and the second area, and the LED part pins are pins for connecting an external LED lamp.
The LED part pins are arranged between a first area on the first side of the charging power management chip and a second area on the second side of the charging power management chip. The LED lamp connected with the LED part pins is not interfered by high-frequency signals generated by the operation of the power supply part pins in the operation process, so that the LED lamp can be arranged between the first area and the second area.
In this embodiment, by arranging the LED portion pins between the first area and the second area, the space of the charging power management chip is reasonably utilized while ensuring that the analog portion pins are located at a far distance from the power portion pins.
In yet another embodiment, the LED portion pin includes: FLASH_VDD pin, LED1 pin, LED2 pin and Torch_VDD pin;
wherein the FLASH_VDD pin is adjacent to the PMID pin, the LED1 pin is adjacent to the FLASH_VDD pin, the LED2 pin is adjacent to the FLASH_VDD pin, and the Torch_VDD pin is adjacent to the LED2 pin.
The LED part pins comprise 1 FLASH_VDD pin which is arranged on the 3 rd column of the 2 nd row of the charging power management chip. The FLASH_VDD pin is a power supply input of the external LED lamp when the external LED lamp works in a FLASH mode, and the voltage of the FLASH_VDD pin is provided by the PMID pin, so that the FLASH_VDD pin is arranged at a position adjacent to the PMID pin, and wiring is convenient.
The LED part pins comprise 1 LED1 pin which is arranged on the 4 th column of the 1 st row of the charging power supply management chip. The LED part pins comprise 1 LED2 pin which is arranged on the 4 th column of the 2 nd row of the charging power supply management chip. The LED1 pin and the LED2 pin are connected with anodes of 2 external LED lamps, and because the FLASH_VDD pin is a power supply input when the LED lamps work in a FLASH mode, the LED1 pin and the FLASH_VDD pin are adjacently arranged, and the LED2 pin and the FLASH_VDD pin are adjacently arranged, so that wiring is facilitated.
The LED part pins comprise 1 Torch_VDD pin, which is arranged on the 5 th column of the 2 nd row of the charging power management chip. The torchjvdd pin is the power input of an external LED lamp when operating in flashlight mode, therefore, the torchjvdd pin is routed adjacent to the LED2 pin, and the torchjvdd pin is routed adjacent to the LED1 pin, facilitating routing.
In the case where the pins of the charging power management chip are arranged in an array of 6 rows by 7 columns, the first region may include an array region of 6 rows by (1-4) columns, and the second region may include an array region of 6 rows by (6-7) columns.
The first area is an array area of 6 rows x (1-4) columns in an array of 6 rows x 7 columns of the charging power management chip, the second area is an array area of 6 rows x (6-7) columns in an array of 6 rows x 7 columns of the charging power management chip, and an area between the first area and the second area is an area of 6 rows x 5 th columns. Therefore, the power supply power part pins arranged in the first area are not adjacent to the analog part pins arranged in the second area in the charging power supply management chip, and the influence of high-frequency signals generated when an external power supply power device connected with the power supply power part pins works on the accuracy of detection results of an external analog control device connected with the analog part pins is weakened.
In yet another embodiment, the above-mentioned BATN pin, BAT pin, TSBUS pin, and bat_id pin are arranged at the edge of the charging power management chip.
The BATN pins and the BATP pins are connected with external equipment for detecting the positive and negative ends of the battery, so that the battery is arranged at the edge of the charging power management chip, and wiring is facilitated.
The TSBUS pin is connected with external equipment for detecting the temperature of the Type-C connector, so that the TSBUS pin is arranged at the edge of the charging power management chip, and wiring is facilitated.
The BAT_ID pin is connected with external equipment for identifying information of a battery manufacturer, and therefore, the BAT_ID pin is arranged at the edge of the charging power management chip, and wiring is facilitated.
Fig. 3 is a schematic diagram of a charging power management chip circuit, according to an example embodiment. As shown in fig. 3, the VBUS pin is connected to the PMID pin via a switching tube.
The SW pin is connected to a Buck controller (Buck Control) 4 via an upper switching tube and a lower switching tube inside the chip, and the SW pin is used for connecting to an external inductor.
The PGND pin is connected with the buck controller 4 through a lower switch tube.
The BAT pin and the SYS pin are connected to a power path management controller (BAT Control) 5.
The nQON pin is connected to an Analog controller 8 (Analog Control).
The flash_vdd pin and the torch_vdd pin are connected to an LED controller (LED Control) 6 via a switching tube.
A capacitance may be provided between the BST pin and the SW pin.
The REGN pin is connected to a low dropout linear regulator (LDO) 3.
The LED1 pin and the LED2 pin are connected with an LED controller 6 through a switch tube.
The EDL pin, the nvbus_ok pin, and the VCONN pin are connected to the analog controller 8.
The VAC pin and the OVPGATE pin are connected to a Driver 10.
The GND pin is connected with the TSBAT pin.
The CC1 pin, the CC2 pin, the DP pin, the DM pin, the SDA pin, the SCL pin, the nINT pin, and the PD_nINT pin are connected with a digital signal processor (Dial Core) 9. The CC1 pin, the CC2 pin, the DP pin, and the DM pin are connected to an adapter (adapter) 11, and the SDA pin, the SCL pin, the nINT pin, and the pd_nint pin are connected to an application processor (Application Processor, AP for short) 12.
The BAT_ID pin is connected with an external battery.
An analog-to-digital converter (ADC) 7 is connected to the digital signal processor 9.
The disclosure also provides a terminal device, which comprises the charging power management chip.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure. This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It is to be understood that the present disclosure is not limited to the precise arrangements and instrumentalities shown in the drawings, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (24)
1. A charging power management chip, characterized in that the charging power management chip (100) comprises:
the power supply power part pins are arranged in a first area (101) on the first side of the charging power management chip, and the power supply power part pins are pins for connecting an external power supply power device;
the analog part pins are arranged in a second area (102) of the second side of the charging power management chip, the first side is opposite to the second side, and the analog part pins are used for connecting an external analog control device;
and the digital part pins are arranged between the first area (101) and the second area (102), and are used for connecting an external digital control device.
2. The charging power management chip of claim 1, wherein the power section pin comprises:
the pin of the step-down charging part is used for connecting an external power supply;
the power path management part pin is used for connecting an external direct current power supply and electric equipment;
and the high-voltage protection part pin is used for connecting external wired control equipment.
3. The charging power management chip of claim 2, wherein the buck charging section pin comprises: VBUS pin, PMID pin, SW pin, PGND pin, BST pin and REGN pin; the power path management part pin includes: BAT pin and SYS pin; the high voltage protection part pin includes: VAC pins and OVPGATE pins;
the SYS pins are arranged on the edge of the charging power management chip (100).
4. The charging power management chip of claim 1, wherein the analog portion pin comprises: EDL pin, NVBUS_OK pin, GND pin, BATN pin, BATP pin, TSBAT pin, TSBUS pin and BAT_ID pin;
wherein the TSBAT pin is adjacent to the BATN pin, or the TSBAT pin is adjacent to the BATP pin.
5. The charging power management chip of claim 1, wherein the digital section pin comprises: nQON pin, CC1 pin, CC2 pin, VCONN pin, nINT pin, DM pin, DP pin, PD_nINT pin, SDA pin, and SCL pin.
6. The charging power management chip of claim 1, further comprising:
the LED part pins are arranged between the first area (101) and the second area (102), and the LED part pins are used for being connected with an external LED lamp.
7. The charging power management chip of claim 6, wherein the LED segment pins comprise: FLASH_VDD pin, LED1 pin, LED2 pin and Torch_VDD pin;
the FLASH_VDD pin is adjacent to the PMID pin, the LED1 pin is adjacent to the FLASH_VDD pin, the LED2 pin is adjacent to the FLASH_VDD pin, and the Torch_VDD pin is adjacent to the LED2 pin.
8. The charging power management chip according to claim 1, wherein pins of the charging power management chip (100) are arranged in an array of 6 rows by 7 columns.
9. The charging power management chip of claim 8, wherein the first region (101) comprises an array region of 6 rows x (1-4) columns and the second region (102) comprises an array region of 6 rows x (6-7) columns.
10. The charging power management chip of claim 4, wherein the BATN pin, the BAT pin, the TSBUS pin, and the bat_id pin are routed at an edge of the charging power management chip (100).
11. A charging power management chip according to claim 3, characterized in that the VBUS pins are routed at the edge of the charging power management chip (100).
12. The charging power management chip of claim 3, wherein the BST pin and the SW pin are adjacent.
13. A charging power management chip according to claim 3, characterized in that the REGN pin is arranged in a middle area of the charging power management chip (100).
14. The charging power management chip of claim 4, wherein the EDL pins are routed in a middle region of the charging power management chip (100).
15. The charging power management chip of claim 4, wherein the nvbus_ok pin is routed in a middle area of the charging power management chip (100).
16. A charging power management chip according to claim 3, characterized in that the VAC pins are routed at the edge of the charging power management chip (100).
17. The charging power management chip according to claim 4, wherein the GND pin is arranged in a middle region of the charging power management chip (100).
18. The charging power management chip of claim 5, wherein the CC1 pins and the CC2 pins are routed in a middle region of the charging power management chip (100).
19. The charging power management chip of claim 5, wherein the VCONN pin is adjacent to the CC1 pin.
20. A charging power management chip according to claim 3, characterized in that the OVPGATE pins are routed at the edge of the charging power management chip (100).
21. The charging power management chip of claim 5, wherein the nINT pin is disposed in a middle region of the charging power management chip (100).
22. The charging power management chip of claim 5, wherein the DM pin and the DP pin are routed at an edge of the charging power management chip (100).
23. The charging power management chip of claim 5, wherein the SDA pin and the SCL pin are routed at an edge of the charging power management chip (100).
24. A terminal device comprising a charging power management chip according to any of claims 1-23.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321674779.6U CN220066957U (en) | 2023-06-28 | 2023-06-28 | Charging power supply management chip and terminal equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321674779.6U CN220066957U (en) | 2023-06-28 | 2023-06-28 | Charging power supply management chip and terminal equipment |
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