CN220023129U - Flash lamp circuit and electronic equipment - Google Patents

Abstract

The utility model discloses a flash lamp circuit and electronic equipment, and belongs to the technical field of electronic equipment. The flash circuit includes: the driving chip, the first light-emitting piece and the second light-emitting piece; the first pin of the driving chip is connected with the first light-emitting piece and the second light-emitting piece; the driving chip is used for driving the first light-emitting piece and the second light-emitting piece to work in a time-sharing mode through the first pin.

Description

Flash lamp circuit and electronic equipment

Technical Field

The utility model belongs to the technical field of electronic equipment, and particularly relates to a flash lamp circuit and the electronic equipment.

Background

At present, a shooting function is an indispensable function of an electronic device, and when the electronic device shoots under a dim light condition, a flash lamp is used as an important auxiliary peripheral, so that the electronic device is widely applied. To meet the shooting requirements, the product design will place an increasing number of flash Lamps (LEDs). If the LED1 and the LED2 are arranged to be used as a flash lamp function, the LED1 and the LED2 are lighted when the flash lamp function is started; the layout LED3 is used as a light supplementing function, and when the light supplementing function is turned on, the light supplementing lamp is turned on.

However, only two outputs of one driving chip (driving IC) can drive the flash, and the existing flash circuit is shown in fig. 1, in which two driving ICs are used to drive 3 lamps to emit light, one driving IC drives LED1 and LED2, and the other driving IC drives the light compensating lamp (LED 3), resulting in higher cost of the flash circuit.

Disclosure of Invention

The embodiment of the utility model aims to provide a flash lamp circuit and electronic equipment, which can solve the problem of higher cost of the flash lamp circuit.

In a first aspect, an embodiment of the present utility model provides a flash circuit, including: the driving chip, the first light-emitting piece and the second light-emitting piece; the first pin of the driving chip is connected with the first light-emitting piece and the second light-emitting piece;

the driving chip is used for driving the first light-emitting piece and the second light-emitting piece to work in a time-sharing mode through the first pin.

In a second aspect, an embodiment of the present utility model provides an electronic device, including a flash circuit as described in the first aspect.

In the embodiment of the utility model, the first pin of the driving chip is connected with the first light-emitting piece and the second light-emitting piece, and the driving chip can drive the first light-emitting piece and the second light-emitting piece through the first pin in a time-sharing manner. Therefore, in the embodiment of the utility model, the time-sharing lighting of different light emitting parts connected on the same pin of the driving chip can be realized through the switching logic, so that the number of the light emitting parts driven by one driving chip can be increased, and compared with the prior art, the embodiment of the utility model can reduce the number of the driving chips in the flash lamp passage under the condition of driving the same number of the light emitting parts, thereby reducing the cost of the flash lamp circuit.

Drawings

FIG. 1 is one of the block diagrams of a flash circuit provided by an embodiment of the present utility model;

FIG. 2 is a second block diagram of a flash circuit according to an embodiment of the present utility model;

FIG. 3 is a third block diagram of a flash circuit provided in an embodiment of the present utility model;

FIG. 4a is a diagram illustrating a flashlight circuit according to an embodiment of the present utility model;

FIG. 4b is a fifth block diagram of a flashlight circuit according to an embodiment of the present utility model;

FIG. 5 is a diagram showing a structure of a flash circuit according to an embodiment of the present utility model;

FIG. 6 is a diagram of a flashlight circuit according to an embodiment of the present utility model;

fig. 7 is a diagram illustrating a structure of a flash circuit according to an embodiment of the present utility model.

Detailed Description

The technical solutions of the embodiments of the present utility model will be clearly described below with reference to the drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments. All other embodiments, which are obtained by a person skilled in the art based on the embodiments of the present utility model, fall within the scope of protection of the present utility model.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present utility model may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.

The embodiment of the utility model can provide a novel flash lamp circuit, and 3 or more than 3 luminous elements can be driven by one driving IC, so that the cost of the flash lamp circuit is reduced.

The flashlight circuit provided by the embodiment of the utility model is described in detail below through specific embodiments and application scenes thereof with reference to the accompanying drawings.

In an embodiment of the present utility model, the flash circuit may include: the driving chip, the first light-emitting piece and the second light-emitting piece.

The first pin of the driving chip is connected with the first light-emitting piece and the second light-emitting piece. That is, the first light emitting element and the second light emitting element are connected to the same pin of the driving chip.

The driving chip is used for driving the first light-emitting piece and the second light-emitting piece to work in a time-sharing mode through the first pin. That is, the first light emitting member and the second light emitting member are time-divisionally lighted up by the driving of the driving chip. When the first luminous element is on, the second luminous element is off; when the second light emitting element is on, the first light emitting element is off.

The embodiment of the utility model is not limited to the switching logic of time-sharing lighting of the first light emitting piece and the second light emitting piece.

In some embodiments, the driving chip may implement time-division lighting of the first light emitting member and the second light emitting member through the switching circuit. In this embodiment, the switching circuit may time-divisionally conduct the connection between the driving chip and the first light emitting member, or the connection between the driving chip and the second light emitting member. When the driving chip is conducted with the first light-emitting piece, the second light-emitting piece is turned off when the first light-emitting piece is turned on; when the driving chip is conducted with the second light emitting piece, the first light emitting piece is turned off when the second light emitting piece is turned on.

In other embodiments, a switch assembly may be provided in the flash circuit for each light emitting element connected to the first pin, and the time-sharing lighting of the first light emitting element and the second light emitting element may be achieved by time-sharing switching on the light emitting assembly connected to the first light emitting element, or the switch assembly connected to the second light emitting element.

According to the flash lamp circuit provided by the embodiment of the utility model, the first pin of the driving chip is connected with the first light-emitting piece and the second light-emitting piece, and the driving chip can drive the first light-emitting piece and the second light-emitting piece through the first pin in a time-sharing manner. Therefore, in the embodiment of the utility model, the time-sharing lighting of different light emitting parts connected on the same pin of the driving chip can be realized through the switching logic, so that the number of the light emitting parts driven by one driving chip can be increased, and compared with the prior art, the embodiment of the utility model can reduce the number of the driving chips in the flash lamp passage under the condition of driving the same number of the light emitting parts, thereby reducing the cost of the flash lamp circuit.

In some embodiments, the first light emitting element is a flash and the second light emitting element is a light supplementing lamp. In this embodiment, the flash and the light compensating lamp can be time-division lighted by one driving chip, and compared with fig. 1, the number of driving chips can be reduced, so that the cost of the flash circuit can be reduced.

Further, the flash circuit may further include a third light emitting member connected to the second pin of the driving chip; the driving chip is used for driving the third luminous element to work through the second pin.

Therefore, the number of the light emitting elements which can be driven by one driving chip can be increased, and in this way, compared with the prior art, the embodiment of the utility model can reduce the number of the driving chips in the flash lamp passage under the condition of driving the same number of the light emitting elements, thereby reducing the cost of the flash lamp circuit.

Notably, the third light emitting element may be in a lit state at all times, where the third light emitting element supplements the first light emitting element and the second light emitting element; alternatively, the third light emitting element may be turned on when the first light emitting element is turned on, and turned off when the second light emitting element is turned on, and at this time, the third light emitting element is used as a supplement to the first light emitting element; alternatively, the third light emitting member may be turned on when the second light emitting member is turned on, turned off when the first light emitting member is turned on, and the third light emitting member is added to the second light emitting member. The concrete explanation is as follows:

in some embodiments, the driving chip is configured to drive the third light emitting element to operate through the second pin under the condition that the first light emitting element is driven to operate through the first pin.

In this embodiment, the third light emitting member may be turned on when the first light emitting member is turned on and turned off when the second light emitting member is turned on, and at this time, the third light emitting member is added to the first light emitting member. In an alternative implementation, the first light emitting element corresponds to LED2 in fig. 1, and the third light emitting element corresponds to LED1 in fig. 1, which is on and off; the second light emitting element corresponds to LED3 in fig. 1, and is turned on in a time-sharing manner with LEDs 1 and 2.

The switching logic of this embodiment is described below.

In some embodiments, the flash circuit further comprises a first switch assembly and a second switch assembly;

the first switch component is connected with the first light-emitting piece and the third light-emitting piece; the second switch component is connected with the second luminous piece;

the driving chip is used for:

when the first switch component is conducted and the second switch component is disconnected, the first light-emitting piece and the third light-emitting piece are driven to work;

and under the condition that the first switch component is disconnected and the second switch component is conducted, the second light emitting piece is driven to work.

For ease of understanding, see fig. 2. As shown in fig. 2, the flash circuit includes a driving chip 10, a first light emitting member 20, a second light emitting member 30, a third light emitting member 40, a first switching assembly 50, and a second switching assembly 60.

The first light emitting member 20 and the second light emitting member 30 are connected to one pin, i.e., a first pin, of the driving chip 10; the third light emitting element 40 is connected to another pin of the driving chip 10, namely, the second pin.

The first light emitting element 20 and the third light emitting element 40 are connected to the same switching element, i.e., the first switching element 50, and are turned on and off simultaneously. The second light emitting element 30 is connected to another switch assembly, namely, the second switch assembly 60, and is turned on in a time-sharing manner with the first light emitting element 20 and the third light emitting element 40.

The first switching assembly 50 is used to turn on or off the driving chip 10 and the first light emitting member 20, and the driving chip 10 and the third light emitting member 40, and the second switching assembly 60 is used to turn on or off the driving chip 10 and the third light emitting member 40.

For the flash circuit shown in fig. 2, the driving chip 10 can be used to:

when the first switching assembly 50 is turned on and the second switching assembly 60 is turned off, the first light emitting member 20 and the third light emitting member 40 are driven to operate, i.e., the first light emitting member 20 and the third light emitting member 40 are lighted. In the case where the first light emitting member corresponds to the LED2 in fig. 1 and the third light emitting member corresponds to the LED1 in fig. 1, the driving chip 10 can realize a flash function by lighting the first light emitting member 20 and the third light emitting member 40;

when the first switch assembly 50 is turned off and the second switch assembly 60 is turned on, the second light emitting member 30 is driven to operate, i.e., the second light emitting member 30 is turned on. In the case where the third light emitting member corresponds to the LED3 in fig. 1, the driving chip 10 can realize the light supplementing function by lighting the second light emitting member 30.

It can be seen that, for the flash circuit shown in fig. 2, the first switch assembly 50 and the second switch assembly 60 can be turned on in a time-sharing manner, so that the driving chip 10 can light the first light emitting element 20, the third light emitting element 40, and the second light emitting element 30 in a time-sharing manner, so as to meet the light requirements of different photographing application scenarios.

The embodiment of the utility model is not limited to the specific structure of the switch assembly, and any switch module that can be used to turn on or off the driving chip and the flash group can be applied to the embodiment of the utility model. Optionally, the switch assembly may comprise at least one of: NMOS tube, PMOS tube and load switch.

It will be appreciated that the connection relationship of the elements in the flash circuit may be different for different configurations of the switch assembly. Examples are illustrated below in some embodiments.

In some embodiments, as shown in fig. 3, the first switching component 50 may include a first NMOS tube 51; the gate of the first NMOS transistor 51 is connected to a first interface, which is used to provide a level signal; the drain electrode of the first NMOS tube 51 is connected with the negative electrodes of the first light emitting element 20 and the third light emitting element 40 respectively; the source electrode of the first NMOS tube 51 is grounded; the anodes of the first light emitting element 20 and the third light emitting element 40 are connected with the driving chip 10, specifically, the anode of the first light emitting element 20 is connected with a first pin of the driving chip 10, and the anode of the third light emitting element 40 is connected with a second pin of the driving chip 10;

the second switching component 60 may include a second NMOS transistor 61; the gate of the second NMOS tube 61 is connected with a second interface, and the second interface is used for providing a level signal; the drain electrodes of the second NMOS tubes 61 are respectively connected with the negative electrodes of the second light emitting elements 30; the source electrode of the second NMOS tube 61 is grounded; the anodes of the second light emitting elements 30 are all connected with the driving chip 10, specifically, the anodes of the second light emitting elements 30 are all connected with the first pins of the driving chip 10.

In this embodiment, the first switch element 50 and the second switch element 60 have the same structure and are both N-channel field effect transistors (N-channel MOSFETs).

Specifically, the source electrode of the NMOS transistor may be connected to the negative electrode of the light emitting element to which it is connected. The source of the NMOS transistor may be grounded. The grid electrode of the NMOS tube is connected with an interface, and the interface can provide a level signal for the grid electrode of the NMOS tube so as to control the working state of the NMOS tube. The level signal of the interface may be provided by the processor. In some alternative implementations, the interface may be a General-Purpose Input/Output interface (GPIO), but is not limited thereto. In fig. 3, the first interface appears as GPIO1 and the second interface appears as GPIO2.

In the flash circuit shown in fig. 3, the driving chip 10, the first light emitting element 20 (or the third light emitting element 40) and the first NMOS transistor 51 are sequentially connected in series, and the driving chip 10, the second light emitting element 30 and the second NMOS transistor 61 are sequentially connected in series. That is, the light emitting member is disposed between the driving chip and the switching assembly.

For the flash circuit shown in fig. 3, alternatively, the driver chip 10 may be used to:

in the case that the first interface provides a high level signal and the second interface provides a low level signal, the first light emitting part 20 and the third light emitting part 40 are driven to operate;

in the case that the first interface provides a low level signal and the second interface provides a high level signal, the second light emitting member 30 is driven to operate.

In particular, when the photographing application scene is that a flash lamp is turned on, the level signal provided by the first interface can be controlled to be changed from a low level signal to a high level signal, so that the first NMOS tube 51 is turned on, and a loop formed by the driving chip 10, the first light emitting element 20 (or the third light emitting element 40), the first NMOS tube 51 and the ground is turned on; the level signal provided by the second interface is controlled to keep a low level signal, so that the second NMOS tube 61 is disconnected, and a loop formed by the driving chip 10, the second light emitting part 30, the second NMOS tube 61 and the ground is disconnected. In this way, the first light emitting element 20 and the third light emitting element 40 can be lightened, the second light emitting element 30 is not lightened, and the light requirement of the photographing application scene is met.

Under the condition that the photographing application scene is that the light supplementing lamp is turned on, the level signal provided by the first interface can be controlled to keep a low level signal, so that the first NMOS tube 51 is disconnected, and a loop formed by the driving chip 10, the first light emitting piece 20 (or the third light emitting piece 40), the first NMOS tube 51 and the ground is disconnected; the level signal provided by the second interface is controlled to be changed from a low level signal to a high level signal, so that the second NMOS tube 61 is conducted, and the loop conduction consisting of the driving chip 10, the second light emitting part 30, the second NMOS tube 61 and the ground is realized. In this way, the first light emitting element 20 and the third light emitting element 40 can be turned off, and the second light emitting element 30 is turned on, so as to meet the light requirement of the photographing application scene.

It can be seen that, for the flash circuit shown in fig. 3, the switching on of the first light emitting element 20 (or the third light emitting element 40) and the second light emitting element 30 can be realized by controlling the level signals provided by the first interface and the second interface, so as to meet the light requirements of different photographing application scenarios of turning on the flash and turning on the light supplement.

In the flash circuit shown in fig. 3, the cathodes of the first light emitting element 20 and the third light emitting element 40 of the first switch assembly 10 are connected to the same NMOS, so that the first light emitting element 20 and the third light emitting element 40 can be turned on or off simultaneously by controlling the state of one NMOS, and the cost of the flash circuit can be further reduced.

In other alternative implementations, as shown in fig. 4a, the number of the first NMOS transistors 51 may be two, including a first NMOS sub-transistor 511 and a second NMOS sub-transistor 512, where the gate of the first NMOS sub-transistor 511 and the gate of the second NMOS sub-transistor 512 are connected to the first interface, the drain of the first NMOS sub-transistor 511 is connected to the negative electrode of the first light emitting element 20, the drain of the second NMOS sub-transistor 512 is connected to the negative electrode of the third light emitting element 40, and the source of the first NMOS sub-transistor 511 and the source of the second NMOS sub-transistor 512 are both grounded.

In fig. 4a, the cathodes of the first light emitting element 20 and the third light emitting element 40 are connected with different sub-NMOS tubes, but the gates of the two sub-NMOS tubes are connected with the same interface, so that the working states of the sub-NMOS tubes can be kept consistent.

For the flash circuit shown in fig. 4a, since the first light emitting element 20 and the third light emitting element 40 are connected with different sub-NMOS transistors, independent control of the first light emitting element 20 and the third light emitting element 40 can be achieved, and thus, compared with the case that the first light emitting element 20 and the third light emitting element 40 are connected with the same NMOS transistor, the operational reliability of the flash circuit can be improved when the NMOS transistor fails.

In other alternative implementations, as shown in fig. 4b, the number of the first NMOS transistors 51 may be three, including a third sub NMOS transistor 513, a fourth sub NMOS transistor 514, and a fifth sub NMOS transistor 515, where the gate of the third sub NMOS transistor 513, the gate of the fourth sub NMOS transistor 514, and the gate of the fifth sub NMOS transistor 515 are all connected to the first interface, the drain of the third sub NMOS transistor 513 is connected to the negative electrode of the first light emitting element, the drain of the fourth sub NMOS transistor 514 and the drain of the fifth sub NMOS transistor 515 are all connected to the negative electrode of the third light emitting element, and the source of the third sub NMOS transistor 513, the source of the fourth sub NMOS transistor 514, and the source of the fifth sub NMOS transistor 515 are all grounded.

In fig. 4b, compared with fig. 4a, the negative electrode of the third light emitting element 40 is further connected to two sub-NMOS tubes, so that when one sub-NMOS tube connected to the third light emitting element 40 fails, the third light emitting element 40 can be turned on through the other sub-NMOS tube, so that the working reliability of the third light emitting element 40 can be further improved, and the working reliability of the flash lamp circuit can be further improved.

The gates of the three first NMOS tubes 51 are all connected to the first interface, where the drains of the first NMOS tubes 51 in the two first NMOS tubes 51 are all connected to the negative electrode of the first light emitting element 20, the drains of the other first NMOS tubes 51 are connected to the negative electrode of the third light emitting element 40, and the sources of the three first NMOS tubes 51 are all grounded.

In other embodiments, as shown in fig. 5, the first switching component 50 may include a third NMOS transistor 52 and a PMOS transistor 53; the source electrode of the PMOS tube 53 is connected with the driving chip 10, the drain electrode of the PMOS tube 53 is respectively connected with the positive electrodes of the first luminescent member 20 and the third luminescent member 40, the grid electrode of the PMOS tube 53 is connected with the drain electrode of the third NMOS tube 52, the grid electrode of the third NMOS tube 52 is connected with a third interface, the third interface is used for providing a level signal, and the source electrode of the third NMOS tube 52 is grounded; the cathodes of the first light emitting element 20 and the third light emitting element 40 are grounded;

the second switching component 60 may include a fourth NMOS transistor 62; the gate of the fourth NMOS transistor 62 is connected to a fourth interface, which is used for providing a level signal; the drain electrodes of the fourth NMOS transistors 62 are respectively connected with the negative electrodes of the second light emitting elements 30; the source of the fourth NMOS tube 62 is grounded; the anodes of the second light emitting elements 30 are connected with the driving chip 10.

In the flash circuit shown in fig. 5, the first switch assembly 50 and the second switch assembly 60 are different in structure. Specifically, the first switching element 50 includes an NMOS transistor and a P-channel field effect transistor (PMOS transistor); the second switching element 60 comprises an NMOS transistor.

Fig. 5 is different from fig. 3 in that the first switching assembly 50 is different in structure.

In fig. 5, a PMOS transistor 53 is disposed between the driving chip 10 and the first light emitting device 20 (or the third light emitting device 40), and a gate of the PMOS transistor 53 is connected to the third interface through a third NMOS transistor 52. In fig. 5, the third interface appears as GPIO1 and the fourth interface appears as GPIO2.

For the flash circuit shown in fig. 5, alternatively, the driver chip 10 may be used to:

in the case that the third interface provides a low level signal and the fourth interface provides a low level signal, the first light emitting part 20 and the third light emitting part 40 are driven to operate; or,

in the case where the third interface provides a high level signal and the fourth interface provides a high level signal, the second light emitting member 30 is driven to operate.

In particular, when the photographing application scene is that the flash lamp is turned on, the level signal provided by the third interface can be controlled to keep a high level signal, so that the third NMOS tube 31 is turned off, the PMOS tube 53 is provided with a low level signal, so that the PMOS tube 53 is turned on, and a loop formed by the driving chip 10, the first light emitting element 20 (or the third light emitting element 40), the first NMOS tube 51 and the ground is turned on; the level signal provided by the fourth interface is controlled to keep a low level signal, so that the second NMOS tube 61 is disconnected, and a loop formed by the driving chip 10, the second light emitting part 30, the second NMOS tube 61 and the ground is disconnected. In this way, the first light emitting element 20 and the third light emitting element 40 can be lightened, and the second light emitting element 30 is not lightened, so as to meet the light requirement of the photographing application scene.

When the photographing application scene is that the light supplementing lamp is turned on, the level signal provided by the third interface can be controlled to be changed from a low level signal to a high level signal, so that the first NMOS tube 51 is turned on, the PMOS tube 53 is provided with a high level signal, so that the PMOS tube 53 is turned off, and a loop formed by the driving chip 10, the first light emitting element 20 (or the third light emitting element 40), the first NMOS tube 51 and the ground is turned off; the level signal provided by the fourth interface is controlled to be changed from a low level signal to a high level signal, so that the second NMOS tube 61 is conducted, and the circuit formed by the driving chip 10, the second light emitting part 30, the second NMOS tube 61 and the ground is conducted. In this way, the first light emitting element 20 and the third light emitting element 40 can be turned off, and the second light emitting element 30 is turned on, so as to meet the light requirement of the photographing application scene.

As can be seen, for the flash circuit shown in fig. 5, the switching on of the first light emitting element 20 (or the third light emitting element 40) and the second light emitting element 30 can be realized by controlling the level signals provided by the third interface and the fourth interface, so as to meet the light requirements of different photographing application scenarios of turning on the flash and turning on the light supplement.

As can be seen from the foregoing, in some embodiments, the third light emitting element may be always in the on state, and the third light emitting element is used as a supplement to the first light emitting element and the second light emitting element. Fig. 6 and 7 illustrate two different representations of this embodiment.

In some embodiments, the flash circuit further comprises a load switch 60 and a fifth NMONS tube;

the first end of the load switch 60 is connected with a first pin of the driving chip 10, the second end of the load switch 60 is connected with the positive electrode of the first light-emitting element 20, and the negative electrode of the first light-emitting element 20 is grounded;

the gate of the fifth NMOS transistor 70 is connected to a fifth interface, which is used for providing a level signal; the drain electrode of the fifth NMOS tube 70 is connected with the negative electrode of the second light emitting element 30; the source electrode of the fifth NMOS tube 70 is grounded; the positive electrode of the second light emitting element 30 is connected with the first pin of the driving chip 10;

the positive electrode of the third light-emitting element 40 is connected with the second pin of the driving chip 10, and the negative electrode of the third light-emitting element 40 is grounded;

a driving chip 10 for:

when the load switch 60 is turned on and the fifth interface provides a low level signal, the first light emitting element 20 and the third light emitting element 40 are driven to operate;

in the case where the load switch 60 is turned off and the fifth interface provides a high level signal, the second light emitting member 30 and the third light emitting member 40 are driven to operate.

As shown in fig. 6, the first light emitting element 20 is connected to the driving chip 10 through the load switch 60, the second light emitting element is grounded through the fifth NMOS transistor 70, and the third light emitting element 40 and the driving chip 10 form a loop. In fig. 6, the fifth interface appears as GPIO2.

For the flash circuit shown in fig. 6, the driving chip 10 may be used to:

when the load switch 60 is turned on and the fifth NMOS transistor 70 is turned off, the first light emitting element 20 and the third light emitting element 40 are driven to operate;

when the load switch 60 is turned off and the fifth NMOS transistor 70 is turned on, the second light emitting element 30 and the third light emitting element 40 are driven to operate.

As can be seen, with the flash circuit shown in fig. 6, the switching lighting of the first light emitting element 20 and the second light emitting element 30 can be achieved by controlling the states of the load switch 60 and the fifth NMOS transistor 70, and the third light emitting element 40 is always in the lighted state when the driving chip 10 is driven.

In some embodiments, the flash circuit further comprises a sixth NMONS tube and a seventh NMONS tube;

the gate of the sixth NMOS 80 is connected to a sixth interface, which is configured to provide a level signal; the drain electrode of the sixth NMOS tube 80 is connected with the cathode of the first light emitting element 20; the source electrode of the sixth NMOS tube 80 is grounded; the positive electrode of the first light-emitting element 20 is connected with a first pin of the driving chip 10;

the gate of the seventh NMOS transistor 90 is connected to a seventh interface, which is configured to provide a level signal; the drain electrode of the seventh NMOS tube 90 is connected with the negative electrode of the second luminescent member 30; the source electrode of the seventh NMOS tube 90 is grounded; the positive electrode of the second light emitting element 30 is connected with the first pin of the driving chip 10;

the positive electrode of the third light-emitting element 40 is connected with the second pin of the driving chip 10, and the negative electrode of the third light-emitting element 40 is grounded;

a driving chip 10 for:

in the case that the sixth interface provides a high level signal and the seventh interface provides a low level signal, the first light emitting part 20 and the third light emitting part 40 are driven to operate;

in the case where the sixth interface provides a low level signal and the seventh interface provides a high level signal, the second light emitting member 30 and the third light emitting member 40 are driven to operate.

As shown in fig. 7, the first light emitting element 20 is connected to the driving chip 10 through a sixth NMOS transistor 80, the second light emitting element is grounded through a seventh NMOS transistor 90, and the third light emitting element 40 and the driving chip 10 form a loop. In fig. 7, the sixth interface is represented by GPIO1 and the seventh interface is represented by GPIO2.

For the flash circuit shown in fig. 7, the driving chip 10 may be used to:

when the sixth NMOS transistor 80 is turned on and the seventh NMOS transistor 90 is turned off, the first light emitting element 20 and the third light emitting element 40 are driven to operate;

when the sixth NMOS transistor 80 is turned off and the seventh NMOS transistor 90 is turned on, the second light emitting element 30 and the third light emitting element 40 are driven to operate.

As can be seen, with the flash circuit shown in fig. 7, the switching lighting of the first light emitting element 20 and the second light emitting element 30 can be achieved by controlling the states of the sixth NMOS transistor 80 and the seventh NMOS transistor 90, and the third light emitting element 40 is always in the lighted state when the driving chip 10 is driven.

It should be noted that, in fig. 1 to 7, the flash lamp is embodied as a Light-Emitting Diode (LED), but the specific form of the flash lamp is not limited thereto.

It should be noted that, the various alternative embodiments described in the embodiments of the present utility model may be implemented in combination with each other without collision, or may be implemented separately, which is not limited to the embodiments of the present utility model.

The embodiment of the utility model can solve the problems of resources and cost faced by FIG. 1 by constructing the discrete passive device, so that the product has more competitive power in the market.

In one scene embodiment, the function of driving 3 lamps and the photographing application scene can be realized by matching a driving IC with an NMOS tube. NMOS tube cost is better, and has great advantage than drive IC cost.

The flash circuit of the present scene embodiment may be applicable to the following photographing application scenes: the LEDs 1 and 2 are simultaneously lightened and simultaneously turned off, so that a simultaneous application scene exists; LED3 works alone, not with LED1 and LED2, then two NMOS transistors are used to implement the time division multiplexing switching logic to drive the lighting of LED1 and LED2, and LED3.

The NMOS tube has three pins, wherein the grid controls the function of conducting and enabling the NMOS tube, and GPIO connected through the processor is used as the control function.

1. When the flash lamp is started, the GPIO1 controls the enabling pin of the first NMOS tube, when the GPIO1 signal is changed from low level to high level, the first NMOS tube is conducted, the GPIO2 keeps low level, the whole loop of the driving output lamp ground is conducted, and the LED2 lamp is driven to be lighted.

2. When the light supplementing lamp is started, the GPIO2 controls the enabling pin of the second NMOS tube, when the GPIO2 signal is changed from low level to high level, the second NMOS tube is conducted, GPIO1 keeps low level, the whole loop circuit of driving output lamp second NMOS tube ground is electrified and conducted, and the LED3 lamp is driven to light.

The hardware scheme uses the same driving IC and a double N-MOS switching scheme to realize the application of switching the rear light supplementing lamp and the single flash lamp.

The embodiment of the scene can be generally used for a scheme of matching a drive IC with an NMOS tube circuit of a discrete passive device, solves the problems of platform resource supply and cost reduction, and increases the income and improves the product quality selling point from the design angle.

It can be understood that the flash lamp circuit can be additionally provided with a plurality of MOS transistors to build up to deal with more photographing application scenes; the switching-off and switching-on application on the path can also be performed by adding a device of the load switch.

The embodiment of the utility model also provides the electronic equipment which can comprise the flash lamp circuit provided by the embodiment of the utility model, so that the cost of the electronic equipment can be reduced.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present utility model is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present utility model may be embodied essentially or in a part contributing to the prior art in the form of a computer software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present utility model.

The embodiments of the present utility model have been described above with reference to the accompanying drawings, but the present utility model is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present utility model and the scope of the claims, which are to be protected by the present utility model.

Claims (10)

1. A flash circuit, comprising: the driving chip, the first light-emitting piece and the second light-emitting piece; the first pin of the driving chip is connected with the first light-emitting piece and the second light-emitting piece;

the driving chip is used for driving the first light-emitting part and the second light-emitting part to work in a time-sharing manner through the first pin;

the flash lamp circuit further comprises a third light emitting part connected with the second pin of the driving chip, wherein the first light emitting part and the third light emitting part are flash lamps, and the second light emitting part is a light supplementing lamp;

the driving chip is further configured to drive the third light emitting element to work through the second pin under the condition that the first light emitting element is driven to work through the first pin.

2. The flash circuit of claim 1, further comprising a first switch assembly and a second switch assembly;

the first switch component is connected with the first light-emitting piece and the third light-emitting piece; the second switch component is connected with the second luminous piece;

the driving chip is used for:

when the first switch component is conducted and the second switch component is disconnected, the first light-emitting piece and the third light-emitting piece are driven to work;

and under the condition that the first switch component is disconnected and the second switch component is conducted, the second light emitting piece is driven to work.

3. The flash circuit of claim 2, wherein the switch assembly comprises at least one of: NMOS tube, PMOS tube and load switch.

4. The flash circuit of claim 2, wherein the first switch assembly comprises a first NMOS tube; the grid electrode of the first NMOS tube is connected with a first interface, and the first interface is used for providing a level signal; the drain electrode of the first NMOS tube is respectively connected with the cathodes of the first light-emitting part and the third light-emitting part; the source electrode of the first NMOS tube is grounded; the positive electrode of the first light-emitting part is connected with the first pin of the driving chip, and the positive electrode of the third light-emitting part is connected with the second pin of the driving chip;

the second switch component comprises a second NMOS tube; the grid electrode of the second NMOS tube is connected with a second interface, and the second interface is used for providing a level signal; the drain electrode of the second NMOS tube is connected with the cathode of the second luminescent piece; the source electrode of the second NMOS tube is grounded; the anodes of the second luminous parts are connected with the first pins of the driving chip;

the driving chip is used for:

driving the first light emitting element and the third light emitting element to work under the condition that the first interface provides a high-level signal and the second interface provides a low-level signal;

and under the condition that the first interface provides a low-level signal and the second interface provides a high-level signal, the second light emitting part is driven to work.

5. The flash circuit of claim 4, wherein the number of first NMOS transistors comprises a first sub NMOS transistor and a second sub NMOS transistor, wherein the gate of the first sub NMOS transistor and the gate of the second sub NMOS transistor are connected to the first interface, the drain of the first sub NMOS transistor is connected to the negative electrode of the first light emitting device, the drain of the second sub NMOS transistor is connected to the negative electrode of the third light emitting device, and the source of the first sub NMOS transistor and the source of the second sub NMOS transistor are grounded.

6. The flash circuit of claim 4, wherein the number of first NMOS transistors includes a third sub NMOS transistor, a fourth sub NMOS transistor, and a fifth sub NMOS transistor, wherein the gates of the third sub NMOS transistor, the fourth sub NMOS transistor, and the fifth sub NMOS transistor are all connected to the first interface, the drain of the third sub NMOS transistor is connected to the negative electrode of the first light emitting element, the drain of the fourth sub NMOS transistor and the drain of the fifth sub NMOS transistor are all connected to the negative electrode of the third light emitting element, and the sources of the third sub NMOS transistor, the fourth sub NMOS transistor, and the fifth sub NMOS transistor are all grounded.

7. The flash circuit of claim 2, wherein the first switch assembly comprises a third NMOS tube and a PMOS tube; the source electrode of the PMOS tube is connected with the driving chip, the drain electrode of the PMOS tube is respectively connected with the positive electrodes of the first light emitting part and the third light emitting part, the grid electrode of the PMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is connected with a third interface, the third interface is used for providing a level signal, and the source electrode of the third NMOS tube is grounded; the cathodes of the first light-emitting part and the third light-emitting part are grounded;

the second switch component comprises a fourth NMOS tube; the grid electrode of the fourth NMOS tube is connected with a fourth interface, and the fourth interface is used for providing a level signal; the drain electrode of the fourth NMOS tube is connected with the negative electrode of the second light-emitting element; the source electrode of the fourth NMOS tube is grounded; the anodes of the second luminous parts are connected with the first pins of the driving chip;

the driving chip is used for:

driving the first light emitting element and the third light emitting element to work under the condition that the third interface provides a low-level signal and the fourth interface provides a low-level signal;

and driving the second light emitting element to work under the condition that the third interface provides a high-level signal and the fourth interface provides a high-level signal.

8. The flash circuit of claim 1, further comprising a load switch and a fifth NMOS transistor;

the first end of the load switch is connected with the first pin of the driving chip, the second end of the load switch is connected with the positive electrode of the first light-emitting piece, and the negative electrode of the first light-emitting piece is grounded;

the grid electrode of the fifth NMOS tube is connected with a fifth interface, and the fifth interface is used for providing a level signal; the drain electrode of the fifth NMOS tube is connected with the negative electrode of the second light-emitting part; the source electrode of the fifth NMOS tube is grounded; the positive electrode of the second light-emitting part is connected with the first pin of the driving chip;

the anode of the third light-emitting part is connected with the second pin of the driving chip, and the cathode of the third light-emitting part is grounded;

the driving chip is used for:

under the condition that the load switch is conducted and the fifth interface provides a low-level signal, the first light emitting part and the third light emitting part are driven to work;

and under the condition that the load switch is disconnected and the fifth interface provides a high-level signal, the second light emitting part and the third light emitting part are driven to work.

9. The flash circuit of claim 1, further comprising a sixth NMOS transistor and a seventh NMOS transistor;

the grid electrode of the sixth NMOS tube is connected with a sixth interface, and the sixth interface is used for providing a level signal; the drain electrode of the sixth NMOS tube is connected with the negative electrode of the first light-emitting element; the source electrode of the sixth NMOS tube is grounded; the positive electrode of the first light emitting element is connected with the first pin of the driving chip;

the grid electrode of the seventh NMOS tube is connected with a seventh interface, and the seventh interface is used for providing a level signal; the drain electrode of the seventh NMOS tube is connected with the negative electrode of the second light-emitting element; the source electrode of the seventh NMOS tube is grounded; the positive electrode of the second light-emitting part is connected with the first pin of the driving chip;

the anode of the third light-emitting part is connected with the second pin of the driving chip, and the cathode of the third light-emitting part is grounded;

the driving chip is used for:

driving the first light emitting element and the third light emitting element to operate under the condition that the sixth interface provides a high-level signal and the seventh interface provides a low-level signal;

and driving the second light emitting element and the third light emitting element to work under the condition that the sixth interface provides a low-level signal and the seventh interface provides a high-level signal.

10. An electronic device comprising a flash circuit as claimed in any one of claims 1 to 9.