CN219590425U - MOSFET parasitic capacitance measuring system - Google Patents

Abstract

The utility model discloses a MOSFET parasitic capacitance measuring system, which belongs to the field of parasitic parameter measurement of power devices, and when the system is used for measuring the MOSFET output capacitance Coss, the system comprises an impedance analyzer and an external power supply; h of impedance analyzer _POT Port, H _CUR The port is connected with the drain electrode of the MOSFET; MOSFET gate and source short circuit, impedance analyzer L _POT Port, L _CUR The port is connected with the grid electrode and the source electrode of the MOSFET; an external power source is connected to the drain of the MOSFET. H by impedance analyzer _POT Port, L _POT The port measures the voltage at two ends of the tested element (MOSFET) and the voltage is measured by the H of the impedance analyzer _CUR 、L _CUR The port measures the current flowing through the tested element, so that the user can obtain the current accuratelyThe actual output capacitance Coss in the current MOSFET working process is taken, and the MOSFET performance is accurately mastered.

Description

MOSFET parasitic capacitance measuring system

Technical Field

The utility model relates to the field of parasitic parameter measurement of power devices, in particular to a MOSFET parasitic capacitance measurement system.

Background

Power semiconductor devices are receiving increasing attention as key components of various power electronic systems. Over the past several decades, si power devices have been significantly improved, but are limited by the basic material properties of Si, which nowadays have almost reached performance limits. In order to make a larger breakthrough, people gradually shift their eyes to wide bandgap semiconductor materials with better performance. Silicon carbide is used as a wide forbidden band semiconductor material, and has the characteristics of excellent physical and electrical properties, such as high voltage, high electron saturation drift speed, high thermal conductivity and the like. The device made of the silicon carbide material has higher breakdown voltage, working frequency and working junction temperature, and the switching loss is lower.

Both the increase in power density and the miniaturization of power electronic converters are in urgent need for higher switching frequencies. Silicon carbide MOSFET switching speeds are faster than Si IGBT devices, and therefore applications in the field of high frequency power electronic converters continue to expand. However, its fast switching transient response presents a series of problems such as the higher du/dt and di/dt that the device has to withstand under conventional hard switching converter topologies. The larger voltage and current change rate can induce transient voltage and current through parasitic inductance and capacitance in the loop, so that the MOSFET has larger voltage overshoot and current overshoot, and under even more serious conditions, the silicon carbide power MOSFET device can be directly caused to malfunction or damage. In addition, due to the interaction between the distributed inductance of the circuit and the stray capacitance, electromagnetic oscillations may also occur in the loop, increasing switching losses and presenting a series of electromagnetic interference problems.

The parasitic parameters of the switch device have a critical influence on the performance of the switch device, and the research on the influence of the parasitic parameters on the performance of the traditional Si power switch device can be divided into three methods. The first approach is to model and extract these parasitic parameters mainly by ANSYS Q3D and evaluate their effect by circuit simulation studies, which puts high demands on the accuracy of the model. The second method aims at constructing an analytical model of the MOSFET; however, if all parasitic parameters are taken into account, it is difficult to obtain an accurate analytical expression of the overall switching transient characteristics, so that variations in certain parasitic parameters, such as gate inductance and port parasitic capacitance of the MOSFET, may be ignored. The last one is the experimental method; although this method cannot clearly express the physical meaning of the parameters, it can intuitively exhibit the relationship between each parasitic parameter and the switching characteristics.

Aiming at the silicon carbide MOSFET, the current research is mainly focused on the design, packaging, modeling and application of the silicon carbide MOSFET power device, and the discussion of the influence of parasitic parameters such as parasitic capacitance on the device is relatively less, so how to measure the parasitic capacitance of the silicon carbide MOSFET power device, thereby helping a user to obtain the performance of the silicon carbide MOSFET more accurately is a technical problem which needs to be solved at present.

Disclosure of Invention

The utility model aims to overcome the problems in the prior art and provides a MOSFET parasitic capacitance measuring system.

The aim of the utility model is realized by the following technical scheme: a MOSFET parasitic capacitance measurement system, when used to measure a MOSFET output capacitance Coss, the system includes an impedance analyzer and an external power source;

h of impedance analyzer _POT Port, H _CUR The port is connected with the drain electrode of the MOSFET; MOSFET gate and source short circuit, impedance analyzer L _POT Port, L _CUR The port is connected with the grid electrode and the source electrode of the MOSFET; an external power source is connected to the drain of the MOSFET.

In an example, the drain of the MOSFET and the H of the impedance analyzer _POT H between ports, drain of MOSFET and impedance analyzer _CUR And blocking capacitors are arranged between the ports.

A MOSFET parasitic capacitance measurement system, when used to measure MOSFET reverse transfer capacitance Crss, the system comprising an impedance analyzer and an external power source;

the ground port of the impedance analyzer is connected with the source electrode of the MOSFET, and H of the impedance analyzer _POT Port, H _CUR Port and portDrain connection of MOSFET, L of impedance analyzer _POT Port, L _CUR The port is connected with the grid electrode of the MOSFET; an external power source is connected to the drain of the MOSFET.

In an example, the drain of the MOSFET and the H of the impedance analyzer _POT H between ports, drain of MOSFET and impedance analyzer _CUR And blocking capacitors are arranged between the ports.

A MOSFET parasitic capacitance measurement system, when used to measure a MOSFET input capacitance Ciss, the system includes an impedance analyzer and an external power source;

the drain electrode and the source electrode of the MOSFET are short-circuited through a short-circuit capacitor, and H of an impedance analyzer _POT Port, H _CUR The port is connected with the grid electrode of the MOSFET, L of the impedance analyzer _POT Port, L _CUR The port is connected with the source electrode of the MOSFET; an external power source is connected to the drain of the MOSFET.

In an example, the gate of the MOSFET and the H of the impedance analyzer _POT H between ports, drain of MOSFET and impedance analyzer _CUR And blocking capacitors are arranged between the ports.

In an example, the system further comprises a measurement fixture comprising a measurement circuit; the measuring circuit comprises a plurality of switches, and each switch is arranged on the grid electrode and/or the source electrode and/or the drain electrode of the MOSFET.

In one example, the switch is a relay.

In one example, the system further includes a controller coupled to the switch and/or the external power source.

In an example, the measurement fixture further includes a protection circuit including a first protection sub-circuit, a second protection sub-circuit, a third protection sub-circuit, and a fourth protection sub-circuit;

the first protection sub-circuit is provided with a direct-current blocking module and a first voltage-stabilizing diode module, and the first direct-current blocking module comprises a plurality of parallel capacitors; h of impedance analyzer _CUR H of port through first protection subcircuit and measuring circuit _C The ports are connected; the second protection sub-circuit is provided with a second direct current blocking module and a second voltage stabilizing diode module; impedance componentH of analyzer _POT H of port through second protection subcircuit and measuring circuit _P The ports are connected; two anti-parallel diodes D6 and D7 are arranged between the first protection sub-circuit and the second protection sub-circuit;

the third protection subcircuit is provided with two groups of diodes which are connected in series; l of impedance analyzer _POT L of port through third protection subcircuit and measuring circuit _P The ports are connected; two anti-parallel diodes D18 and D19 are arranged between the third protection sub-circuit and the fourth protection sub-circuit; l of impedance analyzer _CUR L of port through fourth protection sub-circuit and measuring circuit _C The ports are connected.

It should be further noted that the technical features corresponding to the examples above may be combined with each other or replaced to form a new technical solution.

Compared with the prior art, the utility model has the beneficial effects that:

1. in one example, H is measured by an impedance analyzer _POT Port, L _POT The port measures the voltage at two ends of the tested element (MOSFET) and the voltage is measured by the H of the impedance analyzer _CUR 、L _CUR The port measures the current flowing through the tested element, so that a user can accurately acquire the actual output capacitance Coss in the current MOSFET working process, accurately grasp the MOSFET performance, and conveniently guide the user to build a corresponding circuit model based on the current MOSFET.

2. In one example, H is measured by an impedance analyzer _POT Port, L _POT The port measures the voltage at two ends of the tested element and the voltage is measured by the H of the impedance analyzer _CUR 、L _CUR The port measures the current flowing through the tested element, so that a user can accurately acquire the reverse transmission capacitance Crss in the current MOSFET working process, accurately grasp the MOSFET performance, and conveniently guide the user to build a corresponding circuit model based on the current MOSFET.

3. In one example, H is measured by an impedance analyzer _POT Port, L _POT The port measures the voltage at two ends of the tested element and the voltage is measured by the H of the impedance analyzer _CUR 、L _CUR The port measures the current flowing through the tested element, which is convenient for the user to accurately measureAnd the input capacitance Ciss in the current MOSFET working process is obtained, the MOSFET performance is accurately mastered, and a user is conveniently guided to build a corresponding circuit model based on the current MOSFET.

4. In one example, the impedance analyzer is connected with the drain electrode (or gate electrode) of the tested element through H _POT Port, H _CUR And a blocking capacitor is arranged between the ports and used for preventing the impedance analyzer from being damaged by high voltage, so that the use safety of the instrument in the capacitance measurement process is ensured.

5. In one example, by introducing a measurement circuit, automatic switching of the MOSFET pins at the time of three capacitance measurements is achieved.

6. In an example, a controller is introduced to control a switch in a measuring circuit, so that automatic switching of MOSFET pins is realized, measuring convenience is improved, and measuring continuity is ensured.

7. In an example, by introducing the protection circuit, the direct current of an external power supply can be prevented from flowing back to the impedance analyzer, and meanwhile, overvoltage is prevented by the zener diode module and the diode, so that the reliability of system test is ensured.

Drawings

The following detailed description of the present utility model is provided in connection with the accompanying drawings, which are included to provide a further understanding of the utility model, and in which like reference numerals are used to designate like or similar parts throughout the several views, and in which are shown by way of illustration of the utility model and not limitation thereof.

FIG. 1 is a diagram of a MOSFET equivalent circuit taking into account parasitic capacitance;

FIG. 2 is a circuit diagram of an output capacitance measurement circuit in an example of the utility model;

FIG. 3 is a circuit diagram of a reverse transmission capacitance measurement circuit in an example of the present utility model;

FIG. 4 is a circuit diagram of an input capacitance measurement circuit in an example of the utility model;

FIG. 5 is a schematic diagram of a portion of a relay circuit in an example of the utility model;

FIG. 6 is a schematic diagram of another portion of a relay circuit in an example of the utility model;

FIG. 7 is a schematic diagram of an exemplary relay driving circuit according to the present utility model;

FIG. 8 is a diagram of a connection port in an example of the present utility model;

FIG. 9 is a schematic diagram of a controller control in an example of the utility model;

FIG. 10 is a communication schematic in an example of the utility model;

FIG. 11 is a schematic diagram of a protection circuit in an example of the utility model;

FIG. 12 is a graph showing parasitic capacitance value trend of the SiC-MOSFET at voltages of 0-200V given in the data book;

fig. 13 is a graph showing the parasitic capacitance value trend of the SiC-MOSFET measured by the system of the present utility model at voltages of 0 to 200V.

Detailed Description

The following description of the embodiments of the present utility model will be made apparent and fully understood from the accompanying drawings, in which some, but not all embodiments of the utility model are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

In the description of the present utility model, it should be noted that directions or positional relationships indicated as being "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are directions or positional relationships described based on the drawings are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Further, ordinal words (e.g., "first and second," "first through fourth," etc.) are used to distinguish between objects, and are not limited to this order, but rather are not to be construed to indicate or imply relative importance.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

In addition, the technical features of the different embodiments of the present utility model described below may be combined with each other as long as they do not collide with each other.

The MOSFET equivalent circuit taking into account parasitic capacitance is shown in fig. 1. Wherein L is _D 、L _S And L _G Parasitic inductances of drain pin, source pin and gate pin of device (MOSFET), C _GS 、C _GD And C _DS Respectively a gate-source capacitance, a gate-drain capacitance and a drain-source capacitance of the device, R _G Is the internal gate resistance. The three parasitic capacitances of the MOSFET are intrinsic parameters of the MOSFET, and an external circuit must charge and discharge the parasitic capacitances during the switching on and off process, so the parasitic capacitances directly affect the switching performance of the device.

Wherein C is _GS Is formed by overlapping the metalized portions of the gate and the source, and consists of three parts, a first part C _O The device is in a parallel arrangement structure between a grid electrode and a source electrode on the surface of the device; the second part is C _N+ It is the capacitance between the gate and the n+ source diffusion region; the third part is C _P It is the capacitance between the gate and the P-type body.

C _GD (also called reverse transfer capacitance Crss) consists essentially of oxide layer electrostatic capacitance and MOS interface dissipation capacitance, which has a non-linear characteristic, and follows V _ds Increasing and decreasing.

C _DS Represents the capacitance of the PN junction dissipation layer of the drain-source, the capacitance value of the PN junction dissipation layer is related to the unit area and the drain-source voltage and can be along with V _ds Increasing and decreasing.

Device manufacturers typically only use dataThe curves for input capacitance Ciss, output capacitance Coss, and reverse capacitance Crss are provided in the manual. Where ciss=c _GD +C _GS ，Coss＝C _GD +C _DS ，Crss＝C _GD . In order to accurately grasp the influence of the parasitic capacitance on the device, the parasitic capacitance of the device needs to be tested before the device is applied, therefore, the utility model provides a MOSFET parasitic capacitance measuring system which is used for realizing the measurement of the output capacitance Coss, the reverse transmission capacitance Crss and the input capacitance Ciss of the MOSFET; the system mainly comprises an impedance analyzer and an external power supply, and specific connection relations are given for measurement of different parasitic capacitances:

in one example, as shown in FIG. 2, when the system is used to measure the MOSFET output capacitance Coss, the gate and source of the MOSFET are first shorted, then the H of the impedance analyzer _POT Port, H _CUR The port is connected with the drain electrode of the MOSFET, and then the L of the impedance analyzer _POT Port, L _CUR The port is connected with the gate and source of the MOSFET. Because parasitic capacitance parameters of the MOSFET under different voltages need to be measured, an external direct current power supply is added to the drain electrode of the MOSFET; preferably, H is provided at the drain of the MOSFET and the impedance analyzer simultaneously _POT H between ports, drain of MOSFET and impedance analyzer _CUR Blocking capacitors are arranged between the ports to prevent the impedance analyzer from being damaged by high voltage.

In this example, H is passed through an impedance analyzer _POT Port, L _POT Two-terminal voltage V of port pair MOSFET _m Measurement is performed by H of an impedance analyzer _CUR 、L _CUR Port pair current I flowing through MOSFET _m The measurement is performed, at which time the impedance Z of the MOSFET is:

wherein j is a symbol, corresponding to i in complex numbers; ω represents the angular frequency of the current. At the moment, the impedance Z of the MOSFET can be accurately calculated, so that a user can accurately acquire the actual output capacitance Coss in the current MOSFET working process, the MOSFET performance can be accurately mastered, and the user can be guided to build a corresponding circuit model based on the current MOSFET.

In one example, as shown in FIG. 3, when the system is used to measure the MOSFET reverse transfer capacitance Crss, the ground port of the impedance analyzer is first connected to the source of the MOSFET, then the H of the impedance analyzer is connected _POT Port, H _CUR The port is connected with the drain electrode of the MOSFET, and then the L of the impedance analyzer _POT Port, L _CUR The port is connected with the grid electrode of the MOSFET; because parasitic capacitance parameters of the MOSFET under different voltages need to be measured, an external direct current power supply is added to the drain electrode of the MOSFET; preferably, a blocking capacitor is added between the drain of the MOSFET and the HPOT port of the impedance analyzer and between the drain of the MOSFET and the HCUR port of the impedance analyzer, respectively, so as to prevent the impedance analyzer from being damaged by high voltage.

In this example, H is passed through an impedance analyzer _POT Port, L _POT Two-terminal voltage V of port pair MOSFET _m Measurement is performed by H of an impedance analyzer _CUR 、L _CUR Port pair current I flowing through MOSFET _m The measurement is performed, at which time the impedance Z of the MOSFET is:

wherein j is a symbol, corresponding to i in complex numbers; ω represents the angular frequency of the current. At the moment, the impedance Z of the MOSFET can be accurately calculated, so that a user can accurately acquire the reverse transmission capacitance Crss in the current MOSFET working process, the MOSFET performance can be accurately mastered, and the user can be guided to build a corresponding circuit model based on the current MOSFET.

In one example, as shown in FIG. 4, when the system is used to measure MOSFET input capacitance Ciss, the drain of the MOSFET is first of allThe source electrode is short-circuited through a short-circuit capacitor, and then the H of the impedance analyzer _POT Port, H _CUR The port is connected with the grid electrode of the MOSFET, and then the L of the impedance analyzer _POT Port, L _CUR The port is connected to the source of the MOSFET.

Because parasitic capacitance parameters of the MOSFET under different voltages need to be measured, an external direct current power supply is added to the drain electrode of the MOSFET; preferably, the H of the impedance analyzer is simultaneously performed on the grid of the MOSFET _POT H between ports, drain of MOSFET and impedance analyzer _CUR And a blocking capacitor is added between the ports.

In this example, H is passed through an impedance analyzer _POT Port, L _POT Two-terminal voltage V of port pair MOSFET _m Measurement is performed by H of an impedance analyzer _CUR 、L _CUR Port pair current I flowing through MOSFET _m The measurement is performed, at which time the impedance Z of the MOSFET is:

wherein j is a symbol, corresponding to i in complex numbers; ω represents the angular frequency of the current. At the moment, the impedance Z of the MOSFET can be accurately calculated, so that a user can accurately acquire the input capacitance Ciss in the current MOSFET working process, accurately grasp the MOSFET performance, and conveniently guide the user to build a corresponding circuit model based on the current MOSFET.

In an example, the system further comprises a measurement fixture comprising a measurement circuit; specifically, the measuring circuit comprises a plurality of switches, each switch is arranged on the grid electrode and/or the source electrode and/or the drain electrode of the MOSFET, and preferably the grid electrode, the source electrode and the drain electrode of the MOSFET are all provided with the switches. The switch may be a relay or a device having a switching function such as a transistor. In this example, by introducing switches at the gate, source, and drain of the MOSFET, pin switching control can be achieved by controlling the on/off state of the switches, thereby switching between output capacitance Coss, reverse transfer capacitance Crss, and input capacitance Ciss measurements.

In an example, the switch is a relay, as shown in fig. 5, K1, K2, K4, K7 are common relays, and are respectively connected with the gate, the source and the drain of the MOSFET, and are turned on when the relay is attracted; as shown in fig. 6, K3, K5, and K6 are single pole double throw relays, respectively connected to the gate, source, and drain of the MOSFET, and when the relay is attracted, the common leg cuts off the current leg from conducting, and then establishes conduction with the other leg. Preferably, as shown in fig. 7, the measuring circuit further comprises a relay driving circuit, and the relay driving circuit is connected with the relay and the controller. Specifically, the relay driving circuit is composed of a triode, and when the triode is conducted, a loop controlled by the relay is conducted, and meanwhile an LED lamp is used for indicating the state of the relay. Further, as shown in fig. 8, the measurement circuit further includes a connection port, which is connected as a reservation to other external circuits.

In one example, the system further includes a controller, specifically an STM32 series single-chip microcomputer, connected to the switch and/or the external power source. As shown in fig. 9, the controller STM32F103C8T6 (pin 39-pin 42) is connected to the relay and the relay driving circuit, and outputs a high-low level to realize the on-off control of the relay. As shown in fig. 10, the controller STM32F103C8T6 reads the impedance analyzer data by using an RS232 communication method (RS 232 communication module), and sends a command to control the output voltage of the dc power supply through the RS232 communication module, thereby realizing the control of the output voltage of the external power supply.

In an example, the measurement fixture further includes a protection circuit including a first protection sub-circuit, a second protection sub-circuit, a third protection sub-circuit, and a fourth protection sub-circuit;

as shown in fig. 11, a first blocking module and a first zener diode module are arranged on the first protection sub-circuit, the first blocking module comprises 6 parallel capacitors C4-C10, and the first zener diode module comprises two zener diodes D4 and D5 which are connected in reverse series; h of impedance analyzer _CUR H of port through first protection subcircuit and measuring circuit _C The ports are connected; the second protection sub-circuit is provided with a second blocking module and a second zener diode module, the second blocking module comprises capacitors C11 and C12 which are connected in parallel, the second zener diode module comprises two groups of zener diodes which are connected in reverse series, one group of zener diodes consists of D8 and D13, and the other group of zener diodes consists of D9 and D14; h of impedance analyzer _POT H of port through second protection subcircuit and measuring circuit _P The ports are connected; further, two anti-parallel diodes D6 and D7 are arranged between the first protection sub-circuit and the second protection sub-circuit;

two groups of grounding diodes are arranged on the third protection subcircuit, one group of the grounding diodes consists of D10-D12, and the cathode is grounded; the other group consists of D15-D17, and the anode is grounded; l of impedance analyzer _POT L of port through third protection subcircuit and measuring circuit _P The ports are connected; two anti-parallel diodes D18 and D19 are arranged between the third protection sub-circuit and the fourth protection sub-circuit; l of impedance analyzer _CUR L of port through fourth protection sub-circuit and measuring circuit _C The ports are connected. In fig. 11, the DC port is used to connect to an external direct current power supply, and the Check port is used to detect the input voltage of the external direct current power supply. H _C -H _CUR And H _P -H _POT A blocking capacitor is added in the middle of a connecting wire of the MOSFET to prevent direct current loaded by an external direct current power supply to the MOSFET from flowing back to the impedance analyzer, and an anti-series voltage stabilizing diode and an anti-parallel diode are added on a port connected with the impedance analyzer for preventing overvoltage.

Combining the above examples, a preferred example of the utility model is obtained, where the system comprises an impedance analyzer IM3570 and a programmable high voltage power supply IT6726V, based on which the parasitic capacitance value of the SiC-MOSFET of C2M0160120D type is measured at a voltage of 0-200V. At this time, the system measurement flow is:

after power-on, firstly testing an input capacitor Ciss, and pulling up a Ciss pin of the controller by an STM32 controller, wherein at the moment, relays K1 and K2 of a measuring part are closed, and a short-circuit capacitor between a drain electrode and a source electrode is conducted; pulling up the DC_control pin (voltage control of external power supply), and controlling the external DC power supply to be loaded to the MOSF by the relay K5A drain of ET; relays K3 and K6 maintain a default connection state, H of the impedance analyzer _CUR And H _POT The port being connected to the gate of MOSFET, L _POT And L _CUR The port is connected to the source of the MOSFET; at this time, the capacitance measured by the impedance analyzer is C _GD And C _GS The sum is the input capacitance Ciss; the controller reads the current value of the impedance analyzer through an instruction, uploads data to a computer through serial port communication (RS 232 communication), then keeps the relays K1 and K2 closed, controls the voltage of an external direct current power supply to continuously rise through the instruction, and measures input capacitances under different voltages.

Then, starting to measure the reverse capacitance Crss, firstly pulling down the Ciss pin of the controller, and switching off the relays K1 and K2; pulling down the DC_control pin again, and at this time, restoring the default connection of the relay K5, connecting an external direct current power supply to a DC port on the protection part through the DC_Biastee port, and loading external direct current to the drain electrode of the MOSFET through the DC port; pulling up the Crss pin, closing the relay K4 at the moment, and connecting the source electrode of the MOSFET to the ground port of the impedance analyzer; then pull up the Crss_Coss pin again, and then relays K3 and K6 switch connection pins to connect the HCUR and HPOT ports of the impedance analyzer to the drain of the MOSFET, L _POT And L _CUR The port is connected to the gate of the MOSFET, and the capacitance measured by the impedance analyzer is C _GD The controller reads the current value of the impedance analyzer through an instruction, uploads data to a computer through serial port communication, then keeps the state of the current relay unchanged, controls the voltage of an external direct current power supply to continuously rise through the instruction, and measures the reverse capacitance under different voltages.

Finally, measuring an output capacitor Coss, firstly pulling down a Crss pin of the controller, disconnecting a relay K4, disconnecting a source electrode of the MOSFET and connecting the source electrode with a ground port of the impedance analyzer; continuously keeping the DC_control pin pulled down, and keeping the state of the relay K5 unchanged; then the Crss_Coss pin is pulled up, the states of the relays K3 and K6 are unchanged, and the H of the impedance analyzer is maintained _CUR And H _POT The port being connected to the drain of MOSFET, L _POT And L _CUR The port is connected to the gate of the MOSFET; the Coss pin of the controller is pulled up, and the relay is at the momentK7 is closed, and the source electrode and the grid electrode of the MOSFET are short-circuited; at this time, the capacitance measured by the impedance analyzer is C _GD And C _DS The sum is the output capacitance Coss; the controller reads the current value of the impedance analyzer through the instruction, uploads data to the computer through serial communication, then keeps the state of the current relay unchanged, controls the voltage of the external direct current power supply to continuously rise through the instruction, and measures the output capacitance under different voltages.

At this time, the measurement results of the parasitic capacitance value of the C2M0160120D type SiC-MOSFET at the voltage of 0 to 200V are shown in fig. 12 to 13, fig. 12 is the parasitic capacitance value at the voltage of 0 to 200V given by the C2M0160120D type SiC-MOSFET data manual, and fig. 13 is the measurement result obtained using the present system. As can be seen from comparing the test results of FIG. 13 with those of FIG. 12, the test results of the test system of the present utility model are not much different from those given by the data manual, so that the test results of the system can be applied to the establishment of the physical simulation model of the MOSFET.

The foregoing detailed description of the utility model is provided for illustration, and it is not to be construed that the detailed description of the utility model is limited to only those illustration, but that several simple deductions and substitutions can be made by those skilled in the art without departing from the spirit of the utility model, and are to be considered as falling within the scope of the utility model.

Claims (10)

1. A MOSFET parasitic capacitance measurement system, characterized by: when used to measure MOSFET output capacitance Coss, the system includes an impedance analyzer and an external power source;

h of impedance analyzer _POT Port, H _CUR The port is connected with the drain electrode of the MOSFET; MOSFET gate and source short circuit, impedance analyzer L _POT Port, L _CUR The port is connected with the grid electrode and the source electrode of the MOSFET;

an external power source is connected to the drain of the MOSFET.

2. A MOSFET parasitic capacitance measurement system according to claim 1, wherein: the saidH of drain electrode and impedance analyzer of MOSFET _POT H between ports, drain of MOSFET and impedance analyzer _CUR And blocking capacitors are arranged between the ports.

3. A MOSFET parasitic capacitance measurement system, characterized by: when used to measure MOSFET reverse transfer capacitance Crss, the system includes an impedance analyzer and an external power source;

the ground port of the impedance analyzer is connected with the source electrode of the MOSFET, and H of the impedance analyzer _POT Port, H _CUR The port is connected with the drain electrode of the MOSFET, L of the impedance analyzer _POT Port, L _CUR The port is connected with the grid electrode of the MOSFET;

an external power source is connected to the drain of the MOSFET.

4. A MOSFET parasitic capacitance measurement system according to claim 3, wherein: h of drain electrode of MOSFET and impedance analyzer _POT H between ports, drain of MOSFET and impedance analyzer _CUR And blocking capacitors are arranged between the ports.

5. A MOSFET parasitic capacitance measurement system, characterized by: when used to measure MOSFET input capacitance Ciss, the system includes an impedance analyzer and an external power source;

the drain electrode and the source electrode of the MOSFET are short-circuited through a short-circuit capacitor, and H of an impedance analyzer _POT Port, H _CUR The port is connected with the grid electrode of the MOSFET, L of the impedance analyzer _POT Port, L _CUR The port is connected with the source electrode of the MOSFET;

an external power source is connected to the drain of the MOSFET.

6. A MOSFET parasitic capacitance measurement system according to claim 5, wherein: h of grid electrode and impedance analyzer of MOSFET _POT H between ports, drain of MOSFET and impedance analyzer _CUR And blocking capacitors are arranged between the ports.

7. A MOSFET parasitic capacitance measurement system according to any one of claims 1-6, wherein: the system further includes a measurement fixture including a measurement circuit;

the measuring circuit comprises a plurality of switches, and each switch is arranged on the grid electrode and/or the source electrode and/or the drain electrode of the MOSFET.

8. A MOSFET parasitic capacitance measurement system according to claim 7, wherein: the switch is a relay.

9. A MOSFET parasitic capacitance measurement system according to claim 7, wherein: the system further comprises a controller, which is connected with the switch and/or the external power supply.

10. A MOSFET parasitic capacitance measurement system according to claim 7, wherein: the measuring clamp further comprises a protection circuit, wherein the protection circuit comprises a first protection sub-circuit, a second protection sub-circuit, a third protection sub-circuit and a fourth protection sub-circuit;

the first protection sub-circuit is provided with a direct-current blocking module and a first voltage-stabilizing diode module, and the first direct-current blocking module comprises a plurality of parallel capacitors; h of impedance analyzer _CUR H of port through first protection subcircuit and measuring circuit _C The ports are connected;

the second protection sub-circuit is provided with a second direct current blocking module and a second voltage stabilizing diode module; h of impedance analyzer _POT H of port through second protection subcircuit and measuring circuit _P The ports are connected;

two anti-parallel diodes D6 and D7 are arranged between the first protection sub-circuit and the second protection sub-circuit;

the third protection subcircuit is provided with two groups of diodes which are connected in series; l of impedance analyzer _POT L of port through third protection subcircuit and measuring circuit _P The ports are connected;

two anti-parallel diodes D18 and D19 are arranged between the third protection sub-circuit and the fourth protection sub-circuit; impedance ofL of analyzer _CUR L of port through fourth protection sub-circuit and measuring circuit _C The ports are connected.