CN219577013U

CN219577013U - Bias circuit and device for improving linearity of power amplifier

Info

Publication number: CN219577013U
Application number: CN202122172740.1U
Authority: CN
Inventors: 张海涛; 张泽洲; 许育森; 谢善谊; 刘雨非
Original assignee: Shenzhen Xinbaite Microelectronics Co ltd
Current assignee: Shenzhen Xinbaite Microelectronics Co ltd
Priority date: 2021-09-08
Filing date: 2021-09-08
Publication date: 2023-08-22
Anticipated expiration: 2031-09-08

Abstract

The utility model discloses a bias circuit and a device for improving linearity of a power amplifier, wherein the bias circuit comprises a reference voltage source and a power supply voltage source, the bias circuit comprises a first mirror image module, a second mirror image module and an emitter follower module, the first mirror image module is respectively connected with the reference voltage source, the power supply voltage source, the second mirror image module and the emitter follower module and is used for providing proper bias current for each amplifying stage and determining a static working point; the second mirror module is respectively connected with the reference voltage source and the first mirror module and is used for stabilizing current and distributing the current in proportion; the emitter following module and the first mirror module are used for outputting bias voltage and improving linearity of the power amplifier.

Description

Bias circuit and device for improving linearity of power amplifier

Technical Field

The present utility model relates to the field of power amplifier design technology, and in particular, to a bias circuit and a device for improving linearity of a power amplifier.

Background

Modern communication systems are continuously upgraded, and the linearity requirements of wireless communication systems such as 2G to 3G,3G to 4G,4G to 5G, wiFi and the like are increasingly higher. The power amplifier is a key device for signal power transmission, and the bias circuit plays a critical role in the linearity index of the power amplifier.

At present, under the condition of large signal, the base voltage of the radio frequency triode at the output end of the traditional power amplifier bias circuit can be reduced along with the rising of power due to the self-bias effect, so that the base voltage of the radio frequency triode is reduced, the radio frequency performance is finally reduced, and the requirement of a communication system cannot be met.

Therefore, it is desirable to provide a bias circuit and a device for improving the linearity of a power amplifier to solve the problems in the prior art.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present utility model is to provide a bias circuit and a device for improving linearity of a power amplifier.

In order to achieve the above object, the present utility model provides a bias circuit for improving linearity of a power amplifier, including a reference voltage source and a supply voltage source, where the bias circuit includes a first mirror module, a second mirror module, and an emitter follower module, where the first mirror module is connected to the reference voltage source, the supply voltage source, the second mirror module, and the emitter follower module, respectively, and is configured to provide appropriate bias currents to each amplifying stage, and determine a static operating point; the second mirror module is respectively connected with the reference voltage source and the first mirror module and is used for stabilizing current and distributing the current in proportion; the emitter following module and the first mirror module are used for outputting bias voltage and improving linearity of the power amplifier.

Preferably, the emitter follower module comprises at least one emitter follower.

Preferably, the first mirror module includes a first triode and a second triode, wherein a first end and a second end of the first triode are both connected with a first end of the second triode and a first end of the emitter-follower, a second end of the emitter-follower is connected with a second end of the second triode, and a third end of the emitter-follower is used for outputting bias voltage.

Preferably, the first mirror module further includes a first impedance and a second impedance, a first end of the first impedance is connected to a second end of the first triode, and a second end of the first impedance is connected to the reference voltage source; the first end of the second impedance is connected with the second end of the second triode, and the second end of the second impedance is connected with the power supply voltage source.

Preferably, the second mirror module includes a third triode, a third impedance, a fourth impedance, a negative feedback capacitor, and a bypass capacitor, wherein a first end of the third triode is connected with a third end of the first triode and a third end of the second triode, a first end of the third impedance is connected with a second end of the third triode, and a second end of the third impedance is connected with the reference voltage source; the first end of the fourth impedance is connected with the third end of the third triode, and the second end of the fourth impedance is grounded; the first end of the negative feedback capacitor is connected with the first end of the third triode, and the second end of the negative feedback capacitor is connected with the second end of the third triode; the first end of the bypass capacitor is connected with the first end of the third triode, and the second end of the bypass capacitor is grounded.

Preferably, the third impedance comprises at least one resistor in series and/or parallel, and the fourth impedance comprises at least one resistor in series and/or parallel.

Preferably, the negative feedback capacitance comprises at least one capacitance in series and/or parallel, and the bypass capacitance comprises at least one capacitance in series and/or parallel.

Preferably, the first impedance comprises at least one resistor in series and/or parallel, and the second impedance comprises at least one resistor in series and/or parallel.

Preferably, the first triode, the second triode, the third triode and the radio follower comprise BJT triodes or MOS (metal oxide semiconductor) tubes.

Based on the same technical conception, the utility model also provides a bias circuit device for improving the linearity of the power amplifier, which comprises a memory, a processor and a program stored on the memory and capable of running on the processor, wherein the program is normally operated according to the bias circuit for improving the linearity of the power amplifier when being executed by the processor.

Compared with the prior art, the utility model has the beneficial effects that:

the bias circuit for improving the linearity of the power amplifier comprises a reference voltage source, a power supply voltage source, a first mirror image module, a second mirror image module and an emitter follower module, wherein the first mirror image module is respectively connected with the reference voltage source, the power supply voltage source, the second mirror image module and the emitter follower module and is used for providing proper bias current for each amplifying stage and determining a static working point; the second mirror module is respectively connected with the reference voltage source and the first mirror module and is used for stabilizing current and distributing the current in proportion; the emitter following module and the first mirror module, specifically, the emitter following module includes at least one emitter follower BJT10 for outputting the bias voltage Vbias, so as to improve the linearity of the power amplifier, that is, when the first triode, the second triode, the third triode and the emitter follower all adopt BJT triodes, by adding the emitter follower BJT10 and changing the corresponding topological structure, when the emitter of the emitter follower BJT10 does not provide the base current for the third triode BJT6 in a high power state, the base voltage drop amplitude of the emitter follower BJT10 is improved, and the AM-AM/AM-PM of the radio frequency signal becomes flatter, so that the linearity of the power amplifier is improved.

Drawings

In order to more clearly illustrate the solution of the present utility model, a brief description will be given below of the drawings required for the description of the embodiments of the present utility model, it being apparent that the drawings in the following description are some embodiments of the present utility model, and that other drawings may be obtained from these drawings without the exercise of inventive effort for a person of ordinary skill in the art.

FIG. 1 is a schematic circuit diagram of a bias circuit for improving linearity of a power amplifier provided by the present utility model;

FIG. 2 is a block diagram of a bias circuit arrangement for improving linearity of a power amplifier according to the present utility model;

reference numerals illustrate:

10. a first mirror module; 20. a second mirror module; 30. an emitter follower module; 40. a memory; 50. a processor.

Detailed Description

The preferred embodiments of the present utility model will be described in detail below with reference to the accompanying drawings so that the advantages and features of the present utility model can be more easily understood by those skilled in the art, thereby making clear and defining the scope of the present utility model. It will be apparent that the described embodiments are only some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to fall within the scope of the utility model.

The terms "comprising" and "having" and any variations thereof in the description of the utility model and the claims and the description of the drawings above are intended to cover a non-exclusive inclusion. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order. The terms "upper," "lower," "left," "right," "front," "rear," "side," and the like in the description and claims of the utility model or in the above-described drawings are used for relative positional description with respect to the provided drawings and are not intended to describe a particular order of actual products.

Referring to fig. 1, an embodiment of the present utility model provides a bias circuit for improving linearity of a power amplifier, which includes a reference voltage source Vreg and a supply voltage source Vbat, wherein the reference voltage source Vreg has high precision and small temperature drift, and can be used to provide stable voltages for each amplifying stage in the bias circuit, and the supply voltage source Vbat is used to provide an input voltage for a desired amplifying stage of the bias circuit.

Further, the bias circuit comprises a first mirror module 10, a second mirror module 20 and an emitter follower module 30, wherein the first mirror module 10 is respectively connected with a reference voltage source, a power supply voltage source, the second mirror module 20 and the emitter follower module 30, and is used for providing proper bias current for each amplifying stage and determining a static working point; the second mirror module 20 is respectively connected with the reference voltage source and the first mirror module 10 and is used for stabilizing current and distributing the current in proportion; the emitter follower module 30 and the first mirror module 10, specifically, the emitter follower module 30 includes at least one emitter follower BJT10 for outputting the bias voltage Vbias, improving the linearity of the power amplifier, i.e. by adding a set of emitter follower BJTs 10 to provide the bias current, a higher linearity of the power amplifier is achieved by improving the AM-AM/AM-PM characteristics.

With continued reference to fig. 1, the first mirror module 10 includes a first triode BJT4 and a second triode BJT5, wherein a first end and a second end of the first triode BJT4 are both connected to a first end of the second triode BJT5 and a first end of the emitter follower BJT10, a second end of the emitter follower BJT10 is connected to a second end of the second triode BJT5, and a third end of the emitter follower BJT10 is used for outputting the bias voltage Vbias.

It should be noted that, the first triode BJT4, the second triode BJT5 and the emitter follower BJT10 include BJT transistors or MOS transistors, for example, when the first triode BJT4, the second triode BJT5 and the emitter follower BJT10 all use BJT transistors, then the base and the collector of the first triode BJT4 are connected to the base of the second triode BJT5 and the base of the emitter follower BJT10, the collector of the emitter follower BJT10 is connected to the collector of the second triode BJT5, and the emitter of the emitter follower BJT10 is used for outputting the bias voltage. When the first transistor BJT4, the second transistor BJT5 and the follower BJT10 are all MOS transistors, the connection manner of the first transistor BJT4, the second transistor BJT5 and the follower BJT10 may be connected according to the actual circuit condition, which is not limited herein.

The first mirror module 10 further includes a first impedance R16 and a second impedance R17, wherein a first end of the first impedance R16 is connected to a second end of the first triode BJT4, and a second end of the first impedance R16 is connected to the reference voltage source Vreg; the first terminal of the second impedance R17 is connected to the second terminal of the second transistor BJT5, and the second terminal of the second impedance R17 is connected to the supply voltage source Vbat. The first resistor R16 and the second resistor R17 are used for limiting current to supply appropriate current to the second end of the first triode BJT4 and the second end of the second triode BJT5, that is, when the first triode BJT4, the second triode BJT5 and the follower BJT10 all adopt BJT transistors, the first resistor R16 and the second resistor R17 are used for limiting current to supply appropriate current to the collector of the first triode BJT4 and the collector of the second triode BJT 5. The present utility model is not particularly limited herein.

Wherein the first impedance comprises at least one resistor in series and/or parallel, and the second impedance comprises at least one resistor in series and/or parallel, not specifically defined herein.

With continued reference to fig. 1, the second mirror module 20 includes a third transistor BJT6, a third resistor R14, a fourth resistor R20, a negative feedback capacitor C15, and a bypass capacitor C17, wherein a first end of the third transistor BJT6 is connected to a third end of the first transistor BJT4 and a third end of the second transistor BJT5, a first end of the third resistor R14 is connected to a second end of the third transistor BJT6, and a second end of the third resistor R14 is connected to a reference voltage Vreg; the first end of the fourth impedance R20 is connected with the third end of the third triode BJT6, and the second end of the fourth impedance R20 is grounded; the first end of the negative feedback capacitor C15 is connected with the first end of the third triode BJT6, and the second end of the negative feedback capacitor C15 is connected with the second end of the third triode BJT 6; a first end of the bypass capacitor C17 is connected to a first end of the third transistor BJT6, and a second end of the bypass capacitor C17 is grounded.

When the third triode adopts a BJT triode or an MOS tube, the base electrode of the third triode BJT6 is connected with the emitter electrode of the first triode BJT4 and the emitter electrode of the second triode BJT5, the first end of the third impedance R14 is connected with the collector electrode of the third triode BJT6, and the second end of the third impedance R14 is connected with the reference voltage source Vreg; the first end of the fourth impedance R20 is connected with the emitter of the third triode BJT6, and the second end of the fourth impedance R20 is grounded; the first end of the negative feedback capacitor C15 is connected with the base electrode of the third triode BJT6, and the second end of the negative feedback capacitor C15 is connected with the collector electrode of the third triode BJT 6; the first end of the bypass capacitor C17 is connected with the base electrode of the third triode BJT6, and the second end of the bypass capacitor C17 is grounded. When the third transistor BJT6 is a MOS transistor, the connection manner described above may be connected according to the actual circuit condition, which is not limited herein.

The third impedance R14 comprises at least one resistor in series and/or parallel, and the fourth impedance R20 comprises at least one resistor in series and/or parallel; the negative feedback capacitor C15 includes at least one capacitor connected in series and/or in parallel, and the bypass capacitor C17 includes at least one capacitor connected in series and/or in parallel, which is not particularly limited herein.

The third resistor R14 is a current limiter for supplying a suitable current to the collector of the third transistor BJT 6. The negative feedback capacitor C15 achieves the effects of less feedback and stable output.

The fourth resistor R20 is used for stabilizing the operating point and improving the switching characteristic of the third transistor BJT6, because the third transistor BJT6 has a storage time from on to off, and the storage time becomes longer with the increase of temperature, the fourth resistor R20 can inhibit the rate of change, thereby accelerating the turn-off of the third transistor BJT and avoiding the deep saturation of the third transistor BJT. The bypass capacitor C17 is used for high-frequency filtering, so that the anti-interference capability is improved. When high-frequency alternating current clutter is interfered, the capacitor can short-circuit the high-frequency alternating current clutter to the ground, so that the interference is eliminated.

By adding the emitter follower BJT10 and the corresponding topology change, when the power amplifier works in a high power state, the emitter of the emitter follower BJT10 does not provide base current for the third triode BJT6, so that the base voltage drop amplitude of the emitter follower BJT10 is improved, and the AM-AM/AM-PM of the radio frequency signal is flatter, thereby improving the linearity of the power amplifier.

Referring to fig. 2, fig. 2 is a schematic block diagram of a bias circuit device for improving linearity of a power amplifier according to an embodiment of the present utility model based on the same technical concept, which further includes a memory 40, a processor 50, and a program stored in the memory 40 and capable of running on the processor 50, wherein the program when executed by the processor 50 performs normal operation according to the bias circuit for improving linearity of the power amplifier.

The foregoing is merely illustrative of the present utility model and is not to be construed as limiting thereof; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced with equivalents; all equivalent structures or equivalent flow changes made by the specification and the attached drawings of the utility model or directly or indirectly applied to other related technical fields are included in the protection scope of the utility model.

Claims

1. A bias circuit for improving linearity of a power amplifier comprises a reference voltage source and a supply voltage source, and is characterized in that the bias circuit comprises a first mirror image module, a second mirror image module and an emitter following module,

the first mirror module is respectively connected with the reference voltage source, the power supply voltage source, the second mirror module and the emitter follower module and is used for providing proper bias current for each amplifying stage and determining a static working point;

the second mirror module is respectively connected with the reference voltage source and the first mirror module and is used for stabilizing current and distributing the current in proportion;

the emitter following module and the first mirror module are used for outputting bias voltage and improving linearity of the power amplifier.

2. The bias circuit of claim 1 wherein said emitter follower module comprises at least one emitter follower.

3. The bias circuit of claim 2, wherein the first mirror module comprises a first transistor and a second transistor, wherein the first terminal and the second terminal of the first transistor are connected to the first terminal of the second transistor and the first terminal of the emitter follower, the second terminal of the emitter follower is connected to the second terminal of the second transistor, and the third terminal of the emitter follower is configured to output a bias voltage.

4. The bias circuit of claim 3 wherein said first mirror module further comprises a first impedance and a second impedance, a first end of said first impedance being connected to a second end of said first transistor, a second end of said first impedance being connected to said reference voltage source; the first end of the second impedance is connected with the second end of the second triode, and the second end of the second impedance is connected with the power supply voltage source.

5. The bias circuit of claim 4, wherein said second mirror module comprises a third transistor, a third impedance and a fourth impedance, a negative feedback capacitance and a bypass capacitance, a first end of said third transistor being connected to a third end of said first transistor and a third end of said second transistor, a first end of said third impedance being connected to a second end of said third transistor, a second end of said third impedance being connected to said reference voltage source; the first end of the fourth impedance is connected with the third end of the third triode, and the second end of the fourth impedance is grounded; the first end of the negative feedback capacitor is connected with the first end of the third triode, and the second end of the negative feedback capacitor is connected with the second end of the third triode; the first end of the bypass capacitor is connected with the first end of the third triode, and the second end of the bypass capacitor is grounded.

6. The bias circuit of claim 5 wherein said third impedance comprises at least one resistor in series and/or parallel and said fourth impedance comprises at least one resistor in series and/or parallel.

7. The bias circuit of claim 5 wherein said negative feedback capacitance comprises at least one series and/or parallel capacitance and said bypass capacitance comprises at least one series and/or parallel capacitance.

8. The bias circuit of claim 4 wherein said first impedance comprises at least one resistor in series and/or parallel and said second impedance comprises at least one resistor in series and/or parallel.

9. The bias circuit of claim 5, wherein the first transistor, the second transistor, the third transistor, and the follower comprise BJT transistors or MOS transistors.

10. A bias circuit arrangement for improving linearity of a power amplifier, comprising a memory, a processor and a program stored on said memory and executable on said processor, wherein said program when executed by said processor performs a normal operation according to a bias circuit for improving linearity of a power amplifier as claimed in any of claims 1 to 9.