CN114268281A - Power amplification circuit and radio frequency front end module - Google Patents
Power amplification circuit and radio frequency front end module Download PDFInfo
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- CN114268281A CN114268281A CN202111567449.2A CN202111567449A CN114268281A CN 114268281 A CN114268281 A CN 114268281A CN 202111567449 A CN202111567449 A CN 202111567449A CN 114268281 A CN114268281 A CN 114268281A
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Abstract
The application discloses a power amplification circuit and a radio frequency front end module, and relates to the technical field of electronic circuits. Wherein, a power amplifier circuit includes: the power amplifier comprises a signal input end, a signal output end, a first power amplifying transistor, a first voltage division circuit and a second voltage division circuit; one end of the second voltage division circuit is connected with the first node of the first power amplification transistor, the other end of the second voltage division circuit is connected with the third node of the first power amplification transistor, the second voltage division circuit is configured to enable the voltage difference value between the first node and the third node of the first power amplification transistor to be reduced along with the increase of the power of the amplified radio-frequency signal, the current value of the radio-frequency signal received by the first power amplification transistor can be increased, the gain of the first power amplification transistor under the condition of larger output power is increased, the phenomenon that the gain of the first power amplification transistor is prematurely compressed along with the increase of the output power is avoided, and the working linearity of the power amplification circuit is further optimized.
Description
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to a power amplification circuit and a radio frequency front-end module.
Background
Nowadays, with the popularization of the fifth Generation Mobile Communication Technology (5th Generation Mobile Communication Technology, 5G), the performance requirement of the power amplifier circuit is higher and higher.
In the prior art, design indexes of a power amplifier circuit include output power, efficiency, gain, bandwidth, linearity, and the like. For mobile communication systems employing linear modulation techniques, any non-linearity of the power amplification circuit tends to produce unwanted frequency components that affect the performance of the mobile communication system. For example, in the process of amplifying a radio frequency signal by the power amplifier circuit, as the output power increases, the gain of the power amplifier circuit may be compressed too early, thereby affecting the linearity of the power amplifier circuit.
Disclosure of Invention
The embodiment of the application provides a power amplification circuit and a radio frequency front end module, which aim to solve the problem that the working linearity of the power amplification circuit is poor in the prior art.
In a first aspect, an embodiment of the present application provides a power amplification circuit, including: the power amplifier comprises a signal input end, a signal output end, a first power amplifying transistor, a first voltage division circuit and a second voltage division circuit; the signal input is configured to receive a radio frequency signal, and the signal output is configured to output an amplified radio frequency signal;
a first node of the first power amplifying transistor is coupled to the signal input terminal, a second node of the first power amplifying transistor is coupled to the signal output terminal, and a third node of the first power amplifying transistor is connected to a ground terminal through the first voltage dividing circuit;
one end of the second voltage division circuit is connected to the first node of the first power amplification transistor, and the other end of the second voltage division circuit is connected to the third node of the first power amplification transistor;
the second voltage dividing circuit is configured to decrease a voltage difference between the first node of the first power amplifying transistor and the third node as the power of the amplified radio frequency signal increases.
Further, the second node of the first power amplifying transistor is also used for connecting a power supply end.
Further, the first voltage dividing circuit includes a first resistor.
Further, the second voltage division circuit comprises a first diode; the anode of the first diode is connected with the first node of the first power amplifying transistor, and the cathode of the first diode is connected with the third node of the first power amplifying transistor.
Furthermore, the second voltage division circuit comprises a first diode and a second resistor;
the anode of the first diode is connected with the first node of the first power amplifying transistor, the cathode of the first diode is connected with the first end of the second resistor, and the second end of the second resistor is connected with the third node of the first power amplifying transistor.
Further, when the first power amplifying transistor approaches or reaches a saturation state, the first diode is in a cut-off state.
Further, the resistance value of the second resistor is larger than that of the first resistor.
Further, the first power amplifying transistor is a BJT transistor and comprises a base, a collector and an emitter, and the base of the first power amplifying transistor is coupled to the signal input end; the collector of the first power amplifying transistor is coupled to the signal output terminal, and the emitter of the first power amplifying transistor is connected to a ground terminal through the first voltage dividing circuit.
Furthermore, the power amplifying circuit further comprises a second power amplifying transistor, a first node of the second power amplifying transistor is connected with a second node of the first power amplifying transistor, a second node of the second power amplifying transistor is connected with the signal output end, and a third node of the second power amplifying transistor is connected with a ground terminal.
In a second aspect, an embodiment of the present application further provides a radio frequency front end module, including the power amplification circuit provided in the first aspect.
The embodiment of the application provides a power amplification circuit and radio frequency front end module, wherein, a power amplification circuit includes: the power amplifier comprises a signal input end, a signal output end, a first power amplifying transistor, a first voltage division circuit and a second voltage division circuit; the signal input end is configured to receive a radio frequency signal, and the signal output end is configured to output an amplified radio frequency signal; since the first node of the first power amplifying transistor is coupled to the signal input terminal, the second node of the first power amplifying transistor is coupled to the signal output terminal, and the third node of the first power amplifying transistor is connected to the ground terminal through the first voltage dividing circuit, the third node of the first power amplifying transistor changes with the change of the Ibe current of the first power amplifying transistor under the action of the first voltage dividing circuit, and since one end of the second voltage dividing circuit is connected to the first node of the first power amplifying transistor and the other end of the second voltage dividing circuit is connected to the third node of the first power amplifying transistor, the second voltage dividing circuit is configured such that the difference voltage between the first node and the third node of the first power amplifying transistor decreases with the increase of the power of the amplified radio frequency signal, thereby, under the combined action of the first voltage dividing circuit and the second voltage dividing circuit, when the power of the amplified radio frequency signal output by the first power amplifying transistor is increased, the Ibe current of the first power amplifying transistor is also increased, so that the voltage of the third node of the first power amplifying transistor is also increased, in the case where the voltage of the first node of the first power amplifying transistor is constant, the voltage difference between the first node and the third node of the first power amplifying transistor is decreased, so that a current flowing from the first node of the first power amplifying transistor to the first node through the second voltage dividing circuit decreases, a current inputted to the first power amplifying transistor for amplification increases, therefore, the gain of the first power amplifying transistor in a power close to saturation state is increased, the phenomenon that the gain of the first power amplifying transistor is prematurely compressed along with the increase of output power is avoided, and the working linearity of the power amplifying circuit is optimized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a power amplification circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a power amplifier circuit according to another embodiment of the present application;
fig. 3 is a specific circuit diagram one of a power amplifying circuit provided in an embodiment of the present application;
fig. 4 is a specific circuit diagram of a power amplifier circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a radio frequency front end module according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a power amplifier circuit according to an embodiment of the present disclosure. Fig. 1 shows a power amplifier circuit 100, which is applied to a radio frequency circuit.
As shown in fig. 1, the power amplification circuit 100 includes: signal input terminal 10, signal output terminal 20, first power amplifying transistor Q1, first voltage divider circuit 30, and second voltage divider circuit 40. Specifically, the method comprises the following steps:
the signal input 10 is configured to receive a radio frequency signal and the signal output 20 is configured to output an amplified radio frequency signal.
The first node P1 of the first power amplifying transistor Q1 is coupled to the signal input terminal 10, the second node P2 of the first power amplifying transistor Q1 is coupled to the signal output terminal 20, and the third node P3 of the first power amplifying transistor Q1 is connected to the ground terminal through the first voltage dividing circuit 30.
One end of the second voltage dividing circuit 40 is connected to the first node P1 of the first power amplifying transistor Q1, and the other end of the second voltage dividing circuit 40 is connected to the third node P3 of the first power amplifying transistor Q1.
The second voltage division circuit 40 is configured such that a voltage difference between the first node P1 and the third node P3 of the first power amplifying transistor Q1 is decreased as the power of the amplified radio frequency signal is increased.
In the present embodiment, the signal input 10 is configured to receive a radio frequency signal. Since the first node P1 of the first power amplifying transistor Q1 is coupled to the signal input terminal 10, and one end of the second voltage divider circuit 40 is connected to the first node P1 of the first power amplifying transistor Q1, a part of the current of the rf signal is inputted to the first power amplifying transistor Q1 for amplification, and a part of the current is inputted to the second voltage divider circuit 40. That is, the first power amplifying transistor Q1 amplifies the rf signal, and the second voltage dividing circuit 40 divides the equivalent current of the rf signal. Since the third node P3 of the first power amplifying transistor Q1 is connected to the ground terminal through the first voltage divider circuit 30, that is, the first voltage divider circuit 30 is connected to the second voltage divider circuitThe third node P3 of the first power amplifying transistor Q1 is connected to the ground, one end of the second voltage divider circuit 40 is connected to the first node P1 of the first power amplifying transistor Q1, and the other end of the second voltage divider circuit 40 is connected to the third node P3 of the first power amplifying transistor Q1, so that the first voltage divider circuit 30 and the second voltage divider circuit 40 are connected to the third node P3 of the first power amplifying transistor Q1 in common. That is, the voltage value of the third node P3 of the first power amplifying transistor Q1 may be determined according to the magnitude of the Ibe current value flowing through the first power amplifying transistor Q1 and the resistance value of the first voltage dividing circuit 30. Meanwhile, since the second voltage division circuit 40 is connected between the first node P1 of the first power amplification transistor Q1 and the third node P3 of the first power amplification transistor Q1, the current value I flowing through the second voltage division circuit 401Is affected by a voltage difference between the first node P1 and the third node P3.
As shown in fig. 1, the first node P1 of the first power amplifying transistor Q1 is coupled to the signal input terminal 10, the second node P2 of the first power amplifying transistor Q1 is coupled to the signal output terminal 20, since the third node P3 of the first power amplifying transistor Q1 is connected to the ground terminal through the first voltage dividing circuit 30, the voltage value at the third node P3 of the first power amplifying transistor Q1 is not equal to the ground terminal voltage value, and the voltage magnitude of the third node P3 of the first power amplifying transistor Q1 is related to the magnitude of the Ibe current of the first power amplifying transistor under the condition that the resistance value of the first voltage dividing circuit 30 is not changed. The voltage of the third node P3 of the first power amplifying transistor Q1 increases as the Ibe current of the first power amplifying transistor increases and decreases as the Ibe current of the first power amplifying transistor decreases.
When it needs to be mentioned, in the practical application process, since the first voltage divider circuit 30 is connected between the third node of the first power amplifying transistor Q1 and the ground terminal, extra loss is brought, so as to affect the gain of the power amplifying circuit, the application scenario of the present application is mainly to implement flexible adjustment of the gain of the power amplifying circuit by connecting the first voltage divider circuit 30 between the third node of the first power amplifying transistor Q1 and the ground terminal, under the condition that the gain of the power amplifying circuit is rich; since the first voltage divider circuit 30 is connected, when the output power of the first power amplifier transistor Q1 is larger, a larger loss is generated, so that the phenomenon of premature gain compression occurs when the output power of the first power amplifier transistor Q1 is larger, therefore, in the present application, the second voltage divider circuit 40 is connected between the first node and the third node of the first power amplifier transistor Q1, and the second voltage divider circuit 40 can increase the magnitude of the gain of the first power amplifier transistor when the output power is larger, so that under the combined action of the first voltage divider circuit 30 and the second voltage divider circuit 40, not only flexible adjustment of the gain of the power amplifier circuit is realized, but also the phenomenon of premature gain compression of the first power amplifier transistor along with the increase of the output power is avoided, and further the working linearity of the power amplifier circuit is optimized.
In a specific implementation, the first voltage dividing circuit 30 may be implemented by an existing pure resistor circuit, so that the voltage from the third node P3 of the first power amplifying transistor Q1 to the ground is not equal to 0, and the resistance value of the first voltage dividing circuit 30 is ensured to be unchanged, and further, when the voltage value of the first node P1 is unchanged, the voltage difference between the first node P1 and the third node P3 can also be changed. If the voltage value of the first node P1 is not changed when the voltage from the third node P3 to ground is equal to 0, the voltage difference between the first node P1 and the third node P3 can only be equal to the voltage value of the first node P1.
In the present embodiment, since the second voltage divider circuit 40 is connected between the first node P1 and the third node P3 of the first power amplifying transistor Q1, when the second voltage divider circuit 40 divides the equivalent current in the radio frequency signal, the current value I1 passing through the second voltage divider circuit 40 is affected by the voltage difference between the first node P1 and the third node P3 of the first power amplifying transistor Q1. Specifically, the value of the current passing through the second voltage dividing circuit 40 is higher when the voltage difference between the first node P1 and the third node P3 is larger, and the value of the current passing through the second voltage dividing circuit 40 is smaller when the voltage difference between the first node P1 and the third node P3 is smaller. It is to be understood that, in all embodiments of the present application, the first node P1 and the third node P3 refer to the first node P1 and the third node P3 of the first power amplifying transistor Q1.
In all embodiments of the present application, the magnitude of the Ibe current of the first power amplifying transistor increases as the output power of the first power amplifying transistor increases, the voltage value of the third node P3 is related to the magnitude of the Ibe current of the first power amplifying transistor, and the voltage value of the third node P3 increases as the Ibe current of the first power amplifying transistor increases. Since the voltage value of the first node P1 is not changed, the voltage value of the third node P3 affects the magnitude of the voltage difference between the first node P1 and the third node P3. Under the condition that the current I of the RF signal is constant, the magnitude of the voltage difference between the first node P1 and the third node P3 influences the magnitude of the current I1 passing through the second voltage divider circuit 40.
It should be noted that the voltage value of the third node P3 is related to the amplification power of the first power amplifying transistor Q1, and in the process of gradually increasing the output power of the first power amplifying transistor Q1, the radio frequency signal is amplified by the first power amplifying transistor Q1, and the power of the obtained amplified radio frequency signal is gradually increased, so the current value Ibe flowing through the first power amplifying transistor Q1 is also gradually increased, and since the resistance value of the first voltage-dividing circuit 30 is also constant, the voltage value of the third node P3 is increased as the current value flowing through the first power amplifying transistor Q1 is increased, and at the same time, the voltage difference between the first node P1 and the third node P3 is gradually decreased, so the current value passing through the second voltage-dividing circuit 40 is also gradually decreased. Since the current value passing through the second voltage divider circuit 40 also gradually decreases, the current of the equivalent electrical signal of the rf signal flows to the first power amplifying transistor Q1 more, that is, the current value of the rf signal received by the first power amplifying transistor Q1 is increased, the gain of the first power amplifying transistor Q1 is increased when the output power is increased, the flatness of the output gain is ensured, and the linearity of the operation of the power amplifying circuit is further improved.
In some embodiments, the power amplification circuit 100 inputs a radio frequency signal through the signal input terminal 10 and outputs the amplified radio frequency signal through the signal output terminal 20, and when the amplified radio frequency signal still cannot meet the signal output requirement, a secondary amplification circuit may be further added to the power amplification circuit 100, and the secondary amplification circuit is used to amplify the amplified radio frequency signal again to meet the signal output requirement.
Fig. 2 shows a schematic diagram of a power amplifier circuit according to another embodiment of the present application. As shown in fig. 2, as an embodiment, as shown in fig. 2, the power amplifying circuit 100 further includes a second power amplifying transistor Q2, a first node of the second power amplifying transistor Q2 is connected to a second node P2 of the first power amplifying transistor Q2, a second node of the second power amplifying transistor Q2 is connected to the signal output terminal 20, and a third node of the second power amplifying transistor Q2 is connected to the ground terminal.
In this embodiment, the second power amplifying transistor Q2 is used to amplify the amplified rf signal again to obtain the target rf signal. Here, the second power amplifying transistor Q2 corresponds to a secondary amplifying circuit, and the first voltage dividing circuit 30 and the second voltage dividing circuit 40 are disposed in a preceding amplifying circuit, that is, the first voltage dividing circuit 30, the second voltage dividing circuit 40, and the first power amplifying transistor Q1 constitute a preceding amplifying circuit.
In the solution of this embodiment, the first voltage divider circuit 30, the second voltage divider circuit 40, and the first power amplifier transistor Q1 form a pre-stage amplifier circuit, and then form the power amplifier circuit 100 together with a secondary amplifier circuit where the second power amplifier transistor Q2 is located, so that when the gain of the power amplifier circuit 100 is increased, premature compression of the gain can be avoided, and meanwhile, excessive power loss caused by the addition of the first voltage divider circuit 30 and the second voltage divider circuit 40 in the circuit can be avoided, so that the application range of the power amplifier circuit is wider.
Fig. 3 shows a specific circuit diagram of a power amplification circuit according to an embodiment of the present application. As shown in fig. 3, the second node P2 of the first power amplifying transistor Q1 is further used for connecting a power supply terminal VCC, as one embodiment.
In this embodiment, the power supply terminal VCC is configured to apply a working voltage to the second node P2 of the first power amplifying transistor Q1, so that the first power amplifying transistor Q1 receives the radio frequency signal through the signal input terminal 10 and forms a closed loop with the ground terminal through the first voltage dividing circuit 30, thereby implementing that the first power amplifying transistor Q1 is turned on based on the equivalent voltage of the working voltage and the radio frequency signal, and further amplifies the radio frequency signal and outputs the amplified radio frequency signal.
For one embodiment, first voltage divider circuit 30 includes a first resistor R1. Here, the first terminal of the first resistor R1 is connected to the third node P3 of the first power amplifying transistor Q1, and the second terminal of the first resistor R1 is connected to the ground terminal, so that the voltage value of the third node P3 is equal to the product of the current value of Ibe flowing through the first power amplifying transistor Q1 and the resistance value of the first resistor R1.
As shown in fig. 3, the first terminal of the first resistor R1 is also connected to the second voltage divider circuit 40 in common with the third node P3 of the first power amplifier transistor Q1. When the equivalent current value of the rf signal is not changed and the resistance value of the first resistor R1 is not changed, the voltage of the first node P1 of the first power amplifying transistor Q1 is not changed, and the voltage difference between the first node P1 of the first power amplifying transistor Q1 and the third node P3 of the first power amplifying transistor Q1 at this time depends on the magnitude of the Ibe current value flowing through the first power amplifying transistor Q1. The first power amplifying transistor Q1 amplifies and outputs the rf signal, and when the power of the amplified rf signal is higher, the larger the Ibe current value flowing through the first power amplifying transistor Q1 is, the higher the voltage value of the third node P3 is, and accordingly, the smaller the voltage difference between the first node P1 and the third node P3 is, and the smaller the current flowing through the second voltage dividing circuit 40 is.
As shown in fig. 3, for one embodiment, second voltage divider circuit 40 includes a first diode D1. An anode of the first diode D1 is connected to the first node P1 of the first power amplifying transistor Q1, and a cathode of the first diode D1 is connected to the third node P3 of the first power amplifying transistor Q1.
In this embodiment, since the first diode D1 has a special effect of unidirectional conduction, when a voltage is applied to the anode of the first diode D1, a current is input through the anode of the first diode D1 and flows out from the cathode of the first diode D1 to the third node P3 of the first power amplifying transistor Q1.
In the embodiment shown in fig. 3, when the first power amplifying transistor Q1 approaches or reaches a saturation state, the first diode D1 is in a turn-off state.
Here, the first power amplifying transistor Q1 amplifies the input rf signal, and as the power of the amplified rf signal becomes larger, the first power amplifying transistor Q1 gradually approaches or reaches a saturation state. Accordingly, the Ibe current value flowing through the third node P3 of the first power amplifying transistor Q1 at this time also increases to approach the maximum current value, the voltage difference between the first node P1 and the third node P3 gradually decreases, and the current value from the first node P1 to the third node P3 through the first diode D1 gradually decreases. When the voltage difference between the first node P1 and the third node P3 is gradually reduced to be smaller than the on-state voltage of the first diode D1, the first diode D1 is turned off, no current is input to the third node P3 and the first resistor R1 through the first diode D1, and the equivalent current of the radio frequency signal is completely transmitted to the power amplifying transistor Q1 for amplification, so that the gain of the power amplifying circuit 100 is increased, and the phenomenon that the gain of the power amplifying transistor Q1 is compressed when the power amplifying transistor Q1 approaches or reaches a saturation state is improved. Preferably, the turn-on voltage of the first diode D1 and the turn-on voltage of the first power amplifying transistor Q1 are equal.
It is easy to understand that the second voltage dividing circuit 40 can be implemented by matching other voltage dividing components on the basis of a diode, besides the diode.
Fig. 4 shows a specific circuit diagram ii of a power amplification circuit according to an embodiment of the present application. As shown in fig. 4, as one embodiment, the second voltage dividing circuit 40 includes: a first diode D1 and a second resistor R2.
An anode of the first diode D1 is connected to the first node P1 of the first power amplifying transistor Q1, a cathode of the first diode D1 is connected to a first terminal of the second resistor R2, and a second terminal of the second resistor R2 is connected to the third node P3 of the first power amplifying transistor Q1.
In this embodiment, since the first diode D1 has a special effect of unidirectional conduction, when a voltage is applied to the anode of the first diode D1, a current flows from the cathode of the first diode D1 to the second resistor R2 through the anode input of the first diode D1, and then flows to the third node P3 of the first power amplifying transistor Q1 through the second resistor R2.
In the embodiment shown in fig. 4, when the first power amplifying transistor Q1 approaches or reaches a saturation state, the first diode D1 is in a turn-off state.
Here, the first power amplifying transistor Q1 amplifies the input rf signal, and as the power of the amplified rf signal becomes larger, the first power amplifying transistor Q1 gradually approaches or reaches a saturation state. Accordingly, the Ibe current flowing through the third node P3 of the first power amplifying transistor Q1 at this time also increases to approach the maximum current value, the voltage difference between the first node P1 and the third node P3 gradually decreases, and the current value from the first node P1 to the third node P3 through the first diode D1 and the second resistor R2 gradually decreases. When the voltage difference between the first node P1 and the third node P3 is gradually reduced to be smaller than the on-state voltage of the first diode D1, the first diode D1 is turned off, no current is input to the third node P3 and the first resistor R1 through the first diode D1 and the second resistor R2, and the equivalent current of the radio frequency signal is completely transmitted to the first power amplifying transistor Q1 for amplification, so that the gain of the power amplifying circuit 100 in the power near saturation state is increased, and the phenomenon of gain compression of the power amplifying transistor Q1 in the power near saturation state or the power near saturation state is improved. Preferably, the turn-on voltage of the first diode D1 and the turn-on voltage of the first power amplifying transistor Q1 are equal.
In all embodiments of the present application, in order to avoid the first power amplifying transistor Q1 from being short-circuited, the equivalent resistance value of the second voltage dividing circuit 40 is larger than that of the first voltage dividing circuit 30. Accordingly, in the example shown in fig. 4, the resistance value of the second resistor R2 is larger than the resistance value of the first resistor R1. In practical applications, if the resistance of the first resistor R1 is too large, the loss of the first power amplifying transistor Q1 is too large, and if the resistance of the second resistor R2 is too small, the voltage dividing function cannot be performed well. Therefore, in this embodiment, the second resistor R2 is preferably a resistor with a large resistance, typically several kilo ohms, and the first resistor R1 is a resistor with a small resistance, typically several ohms.
As a possible implementation manner of this embodiment, the first power amplifying transistor Q1 is a BJT transistor, and includes a base, a collector and an emitter, the base of the first power amplifying transistor Q1 is coupled to the signal input terminal; the collector of the first power amplifying transistor Q1 is coupled to the signal output terminal, and the emitter of the first power amplifying transistor Q1 is connected to the ground terminal through the first voltage dividing circuit 30.
It is easily understood that, in the example shown in fig. 3 or fig. 4, the first voltage dividing circuit 30 includes the first resistor R1, and here, the first resistor R1 may be regarded as a specific implementation circuit of the first voltage dividing circuit 30 or an equivalent resistor circuit of the first voltage dividing circuit 30, that is, a pure resistor circuit equivalent to the first resistor R1 may be used for specific implementation. Accordingly, it can be understood that the emitter of the first power amplifying transistor Q1 is connected to the ground terminal through the first voltage dividing circuit 30, which is equivalent to the emitter of the first power amplifying transistor Q1 connected to the ground terminal through the first resistor R1.
The operation principle of the power amplifier circuit 100 according to the present embodiment will be described in detail with reference to fig. 1 to 4. Specifically, the method comprises the following steps:
as shown in fig. 1 to 4, let the equivalent current of the rf signal received by the signal input terminal 10 be I, and assume that the part of the equivalent current I flowing through the second voltage-dividing circuit 40 is I1Then I is greater than I1. And the partial current I1Is influenced by the voltage difference between the first node P1 and the third node P3.
In fig. 3 or 4, let the current flowing through the first power amplifying transistor Q1 be Ibe, the voltage at the first node P1 of the first power amplifying transistor Q1 be the equivalent voltage V1 of the radio frequency signal, and assuming that the resistance value of the first resistor R1 is R, when the first power amplifying transistor Q1 is turned on, the voltage V2 at the third node P3 of the first power amplifying transistor Q1 is Ibe × R.
When the output power of the power amplification circuit 100 increases, the current Ibe flowing through the first power amplification transistor Q1 increases, and since the voltage V2 of the third node P3 of the first power amplification transistor Q1 is Ibe × R, the voltage V2 of the third node P3 of the first power amplification transistor Q1 increases as the current Ibe flowing through the first power amplification transistor Q1 increases, without changing the resistance value R of the first resistor R1. Since the voltage V1 of the first node P1 of the first power amplifying transistor Q1 is an equivalent electrical signal voltage of the radio frequency signal, and V1 is a constant value or a constant, the voltage difference V between the first node P1 and the third node P3 is V1-V2, and decreases as V2 increases. At this time, a current I from the first node P1 of the first power amplifying transistor Q1 to the third node P3 of the first power amplifying transistor Q1 through the second voltage dividing circuit 401The current I-I input to the first power amplifying transistor Q1 is reduced under the condition that the equivalent current I of the radio frequency signal is not changed1The gain of the power amplifier circuit 100 is increased, so that the situation that the gain of the power amplifier circuit is compressed too early along with the increase of the output power is avoided, and the linearity of the power amplifier circuit is improved.
In fig. 3, when the first power amplifying transistor Q1 operates in a state close to or reaching saturation while the first power amplifying transistor Q1 amplifies an input radio frequency signal, the power of the amplified radio frequency signal becomes large. Accordingly, the value of the current flowing through the third node P3 of the first power amplifying transistor Q1 increases, the voltage difference between the first node P1 and the third node P3 gradually decreases, and the value of the current flowing from the first node P1 to the third node P3 through the first diode D1 gradually decreases. When the voltage difference between the first node P1 and the third node P3 is smaller than the turn-on voltage of the first diode D1, the first diode D1 is turned off, no current passes through the first diode D1 and is input to the third node P3 and the first resistor R1, the equivalent current of the radio frequency signal is completely transmitted to the power amplifying transistor Q1 for amplification, and the gain of the power amplifying circuit 100 is the maximum at this time, so that the phenomenon that the gain is compressed too early is avoided.
In fig. 4, when the first power amplifying transistor Q1 approaches or reaches a saturation state while the first power amplifying transistor Q1 amplifies an input radio frequency signal, the power of the amplified radio frequency signal becomes large. Accordingly, the value of the current flowing through the third node P3 of the first power amplifying transistor Q1 increases, the voltage difference between the first node P1 and the third node P3 gradually decreases, and the value of the current flowing from the first node P1 to the third node P3 through the first diode D1 and the second resistor R2 gradually decreases. When the voltage difference between the first node P1 and the third node P3 is smaller than the turn-on voltage of the first diode D1, the first diode D1 is turned off, no current passes through the first diode D1 and the second resistor R2 and is input to the third node P3 and the first resistor R1, the equivalent current of the radio frequency signal is completely transmitted to the first power amplifying transistor Q1 for amplification, and the gain of the power amplifying circuit 100 is the maximum at this time, so that the phenomenon of premature gain compression is avoided.
Based on any one of the embodiments of fig. 1 to 4, fig. 5 shows a schematic structural diagram of a radio frequency front-end module according to another embodiment of the present application. As shown in fig. 5, the rf front-end module 200 includes the power amplifier circuit 100 in the above-mentioned scheme.
It can be understood that, since the content and implementation manner related to the present application of the radio frequency front-end module 200 provided in this embodiment have been described in detail in the content of the above-mentioned embodiment of the power amplification circuit 100, no further description is provided herein.
The units in the terminal of the embodiment of the application can be combined, divided and deleted according to actual needs.
While the invention has been described with reference to specific embodiments, the scope of the invention is not limited thereto, and those skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the invention, and these modifications or substitutions are intended to be included in the scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A power amplification circuit, comprising: the power amplifier comprises a signal input end, a signal output end, a first power amplifying transistor, a first voltage division circuit and a second voltage division circuit; the signal input is configured to receive a radio frequency signal, and the signal output is configured to output an amplified radio frequency signal;
a first node of the first power amplifying transistor is coupled to the signal input terminal, a second node of the first power amplifying transistor is coupled to the signal output terminal, and a third node of the first power amplifying transistor is connected to a ground terminal through the first voltage dividing circuit;
one end of the second voltage division circuit is connected to the first node of the first power amplification transistor, and the other end of the second voltage division circuit is connected to the third node of the first power amplification transistor;
the second voltage dividing circuit is configured to decrease a voltage difference between the first node of the first power amplifying transistor and the third node as the power of the amplified radio frequency signal increases.
2. The power amplifier circuit according to claim 1, wherein the second node of the first power amplifying transistor is further adapted to be connected to a supply power terminal.
3. The power amplifier circuit according to claim 1, wherein the first voltage divider circuit comprises a first resistor.
4. The power amplifier circuit according to claim 1, wherein the second voltage divider circuit comprises a first diode; the anode of the first diode is connected with the first node of the first power amplifying transistor, and the cathode of the first diode is connected with the third node of the first power amplifying transistor.
5. The power amplifier circuit according to claim 3, wherein the second voltage divider circuit comprises a first diode and a second resistor;
the anode of the first diode is connected with the first node of the first power amplifying transistor, the cathode of the first diode is connected with the first end of the second resistor, and the second end of the second resistor is connected with the third node of the first power amplifying transistor.
6. The power amplification circuit of claim 5, wherein; when the first power amplifying transistor approaches or reaches a saturation state, the first diode is in a cut-off state.
7. The power amplifier circuit according to claim 5, wherein a resistance value of the second resistor is larger than a resistance value of the first resistor.
8. The power amplification circuit of claim 1, wherein the first power amplification transistor is a BJT transistor comprising a base, a collector, and an emitter, the base of the first power amplification transistor being coupled to the signal input; the collector of the first power amplifying transistor is coupled to the signal output terminal, and the emitter of the first power amplifying transistor is connected to a ground terminal through the first voltage dividing circuit.
9. The power amplifier circuit according to claim 1, further comprising a second power amplifier transistor, wherein a first node of the second power amplifier transistor is connected to a second node of the first power amplifier transistor, a second node of the second power amplifier transistor is connected to the signal output terminal, and a third node of the second power amplifier transistor is connected to a ground terminal.
10. A radio frequency front end module comprising the power amplification circuit of any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111567449.2A CN114268281A (en) | 2021-12-20 | 2021-12-20 | Power amplification circuit and radio frequency front end module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111567449.2A CN114268281A (en) | 2021-12-20 | 2021-12-20 | Power amplification circuit and radio frequency front end module |
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| Publication Number | Publication Date |
|---|---|
| CN114268281A true CN114268281A (en) | 2022-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202111567449.2A Pending CN114268281A (en) | 2021-12-20 | 2021-12-20 | Power amplification circuit and radio frequency front end module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117749116A (en) * | 2023-12-04 | 2024-03-22 | 锐磐微电子科技(上海)有限公司 | Radio frequency front end module |
-
2021
- 2021-12-20 CN CN202111567449.2A patent/CN114268281A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117749116A (en) * | 2023-12-04 | 2024-03-22 | 锐磐微电子科技(上海)有限公司 | Radio frequency front end module |
| CN117749116B (en) * | 2023-12-04 | 2024-06-21 | 锐磐微电子科技(上海)有限公司 | Radio frequency front end module |
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