CN219536034U - Digital trimming circuit and operational amplifier - Google Patents

Digital trimming circuit and operational amplifier Download PDF

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Publication number
CN219536034U
CN219536034U CN202223037058.2U CN202223037058U CN219536034U CN 219536034 U CN219536034 U CN 219536034U CN 202223037058 U CN202223037058 U CN 202223037058U CN 219536034 U CN219536034 U CN 219536034U
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electrode
pmos tube
tube
type triode
drain electrode
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周文质
包磊
陈潇
王平霜
彭俊
陈昭君
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GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
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GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
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Abstract

The utility model provides a digital trimming circuit and an operational amplifier, wherein the digital trimming circuit comprises: a current source compensation unit and a trimming unit; the current source compensation unit is connected with the tail current source unit and is used for compensating the tail current source unit and generating a first compensation parameter only comprising a resistance temperature coefficient; the trimming unit is connected with the differential input pair unit and is used for trimming the input offset voltage generated by the differential input pair unit and generating a second compensation parameter only comprising a resistance temperature coefficient, and the resistance temperature coefficient of the second compensation parameter counteracts the resistance temperature coefficient of the first compensation parameter, so that the problem that extra parameters which change along with temperature are introduced when a digital trimming circuit trims the input offset voltage in the operational amplifier in the prior art is solved, and the trimming precision of the operational amplifier is reduced.

Description

Digital trimming circuit and operational amplifier
Technical Field
The present utility model relates to the field of integrated circuits, and more particularly, to a digital trimming circuit and an operational amplifier.
Background
The operational amplifier is widely applied to an analog integrated circuit, the input offset voltage is an important parameter index of the integrated operational amplifier, any integrated operational amplifier can have the input offset voltage, the input offset voltage is from mismatch of components, in practical application, the input offset voltage of the operational amplifier needs to be modified after the current sheet is completed to realize smaller input offset voltage, and the performance of the operational amplifier is improved.
The MOS tube is adopted as the operational amplifier of the differential pair, the input offset voltage of the operational amplifier can change along with temperature, the changing function is related to the size mismatch, the threshold voltage mismatch, the wiring mismatch and other seed factors, so that the temperature coefficient of the offset voltage has randomness, and the temperature coefficient of the offset voltage is difficult to reflect in normal temperature test.
For economy and operability, trimming is usually performed only at normal temperature, so that the temperature coefficient of the offset voltage after trimming is reduced, and the input of parameters which are not additionally introduced along with temperature change during trimming is mainly considered. The digital trimming circuit in the prior art can introduce extra parameters which change along with temperature when trimming the input offset voltage in the operational amplifier, so that the trimming precision of the operational amplifier is reduced.
Disclosure of Invention
Aiming at the defects existing in the prior art, the utility model provides a digital trimming circuit and an operational amplifier, which solve the problem that the digital trimming circuit in the prior art can introduce extra parameters which change along with temperature when trimming the input offset voltage in the operational amplifier, so that the trimming precision of the operational amplifier is reduced.
In a first aspect, the present utility model provides a digital trimming circuit applied to an operational amplifier, the operational amplifier comprising: the digital trimming circuit comprises a tail current source unit and a differential input pair unit, wherein the tail current source unit is connected with the differential input pair unit and is used for providing working voltage for the differential input pair unit, and the digital trimming circuit comprises: a current source compensation unit and a trimming unit; the current source compensation unit is connected with the tail current source unit and is used for compensating the tail current source unit and generating a first compensation parameter only comprising a temperature coefficient of resistance; the trimming unit is connected with the differential input pair unit and is used for trimming the input offset voltage generated by the differential input pair unit and generating a second compensation parameter only comprising a temperature coefficient of resistance, and the temperature coefficient of resistance of the second compensation parameter counteracts the temperature coefficient of resistance of the first compensation parameter.
Optionally, the trimming unit includes: the trimming current source unit, the first digital gating unit and the second digital gating unit; the trimming current source unit is used for generating a first trimming current and a second trimming current; the first digital gating unit is respectively connected with the trimming current source unit and the normal-phase current input end of the differential input pair unit, and is used for controlling a first trimming current input by the trimming current source and generating a second compensation parameter comprising a temperature coefficient of resistance; the second digital gating unit is respectively connected with the trimming current source unit and the negative-phase current input end of the differential input pair unit, and is used for controlling the second trimming current input by the trimming current source and generating a second compensation parameter comprising a temperature coefficient of resistance; wherein the first digital gating unit and the second digital gating unit are not turned on at the same time.
Optionally, the current source compensation unit includes: a ninth PMOS tube, a tenth PMOS tube, a third resistor, a seventh NMOS tube and an eighth NMOS tube; the grid electrode of the ninth PMOS tube is connected with the drain electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the seventh NMOS tube; the grid electrode of the tenth PMOS tube is connected with the control end of the tail current source, the source electrode of the tenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the eighth NMOS tube through a third resistor; the grid electrode of the seventh NMOS tube is connected with the grid electrode of the eighth NMOS tube, the source electrode of the seventh NMOS tube is connected with the second end of the first power supply, and the grid electrode of the seventh NMOS tube is connected with the drain electrode; and the drain electrode of the eighth NMOS tube is connected with the second end of the first power supply.
Optionally, the current source compensation unit includes: a ninth PMOS tube, a tenth PMOS tube, a third resistor, an eleventh PMOS tube, a twelfth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a seventh NMOS tube and an eighth NMOS tube; the grid electrode of the ninth PMOS tube is connected with the drain electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the eleventh PMOS tube; the grid electrode of the tenth PMOS tube is connected with the control end of the tail current source, the source electrode of the tenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the twelfth PMOS tube through a third resistor; the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the twelfth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth NMOS tube; the grid electrode of the twelfth PMOS tube is connected with the drain electrode, the source electrode of the twelfth PMOS tube is connected with the second end of the third resistor, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the eleventh NMOS tube; the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, the drain electrode of the tenth NMOS tube is connected with the grid electrode, and the source electrode of the tenth NMOS tube is connected with the drain electrode of the seventh NMOS tube; the source electrode of the eleventh NMOS tube is connected with the drain electrode of the eighth NMOS tube; the grid electrode of the seventh NMOS tube is connected with the grid electrode of the eighth NMOS tube, the drain electrode of the seventh NMOS tube is connected with the grid electrode, the source electrode of the seventh NMOS tube is connected with the second end of the first power end, and the source electrode of the eighth NMOS tube is connected with the second end of the first power end.
Optionally, the trimming current source unit includes: the band gap reference source, the built-in operational amplifier, the ninth NMOS tube, the eighth PMOS tube and the fourth resistor; the positive electrode of the band gap reference source is connected with the non-inverting input end of the built-in operational amplifier, and the negative electrode of the band gap reference source is connected with the second end of the first power supply; the inverting input end of the built-in operational amplifier is connected with the first end of the fourth resistor, and the output end of the built-in operational amplifier is connected with the grid electrode of the ninth NMOS tube; the drain electrode of the ninth NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the source electrode of the ninth NMOS tube is connected with the first end of the fourth resistor; the grid electrode of the eighth PMOS tube is respectively connected with the control end of the first digital gating unit and the control end of the second digital gating unit, the source electrode of the eighth PMOS tube is connected with the first end of the first power supply end, and the drain electrode of the eighth PMOS tube is connected with the grid electrode; the second end of the fourth resistor is connected with the second end of the first power supply.
Optionally, the trimming current source unit includes: a twenty-first PMOS transistor, a twenty-second PMOS transistor, a third P-type triode, a fourth P-type triode, a sixth N-type triode, a seventh N-type triode, a first resistor, a seventh resistor, a ninth N-type triode, an eighth resistor, an eighth N-type triode, a ninth resistor, an eighth PMOS transistor, a tenth N-type triode and a fourth resistor; the grid electrode of the twenty-first PMOS tube is connected with the grid electrode of the twenty-second PMOS tube, the source electrode of the twenty-first PMOS tube is connected with the first end of the first power supply, and the drain electrode of the twenty-first PMOS tube is respectively connected with the emitter electrode of the third P-type triode, the emitter electrode of the fourth P-type triode, the base electrode of the ninth N-type triode and the base electrode of the tenth N-type triode; the source electrode of the twenty-second PMOS tube is connected with the first end of the first power supply, the grid electrode of the twenty-second PMOS tube is connected with the drain electrode, and the drain electrode of the twenty-second PMOS tube is connected with the collector electrode of the eighth N-type triode; the base electrode of the third P-type triode is connected with the base electrode of the fourth P-type triode, and the collector electrode of the third P-type triode is connected with the collector electrode of the sixth N-type triode; the base electrode and the collector electrode of the fourth P-type triode are connected, and the collector electrode of the fourth P-type triode is connected with the emitter electrode of the seventh N-type triode; the base electrode of the sixth N-type triode is respectively connected with the base electrode of the seventh N-type triode, and the emitter electrode of the sixth N-type triode is connected with the second end of the first resistor; the emitter of the seventh N-type triode is connected with the first end of the first resistor; the first end of the seventh resistor is connected with the second end of the first resistor, and the second end of the seventh resistor is connected with the second end of the first power supply; the first end of the eighth resistor is connected with the grid electrode of the seventh N-type triode, and the second end of the eighth resistor is connected with the second end of the first power supply; the emitter of the ninth N-type triode is connected with the base of the eighth N-type triode; the grid electrode of the eighth PMOS tube is respectively connected with the control ends of the first digital gating unit and the second digital gating unit, the grid electrode of the eighth PMOS tube is connected with the drain electrode, the source electrode of the eighth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the eighth PMOS tube is connected with the collector electrode of the tenth N-type triode; and the emitter of the tenth N-type triode is connected with the second end of the first power supply through the fourth resistor.
Optionally, each digital gating unit includes: a plurality of PMOS tubes and a digital gating module; the grid electrode of each PMOS tube is connected with the grid electrode of the eighth PMOS tube, the source electrode of each PMOS tube is connected with the first end of the first power supply, and the drain electrode of each PMOS tube is connected with the digital gating module; the digital gating module is also connected with the differential input pair unit.
Optionally, the trimming current source unit includes: a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a first capacitor, a ninth NMOS tube, a fifth resistor, a sixth resistor, a first P-type triode and a second P-type triode; the grid electrode of the thirteenth PMOS tube is respectively connected with the grid electrode of the tenth PMOS tube and the grid electrode of the fourteenth PMOS tube, the source electrode of the thirteenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the thirteenth PMOS tube is connected with the source electrode of the fifteenth PMOS tube and the source electrode of the sixteenth PMOS tube; the source electrode of the fourteenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the fourteenth NMOS tube and the grid electrode of the ninth NMOS tube; the grid electrode of the fifteenth PMOS tube is connected with the second end of the fifth resistor and the first end of the first resistor, and the drain electrode of the fifteenth PMOS tube is connected with the drain electrode of the twelfth NMOS tube; the grid electrode of the sixteenth PMOS tube is respectively connected with the second end of the sixth resistor and the emitter electrode of the second P-type triode, and the drain electrode of the sixteenth PMOS tube is connected with the drain electrode of the thirteenth NMOS tube; the grid electrode of the twelfth NMOS tube is connected with the grid electrode of the thirteenth NMOS tube, the drain electrode of the twelfth NMOS tube is connected with the grid electrode, and the source electrode of the twelfth NMOS tube is connected with the second end of the first power supply; the drain electrode of the thirteenth NMOS tube is also connected with the first end of the first capacitor and the grid electrode of the fourteenth NMOS tube respectively, and the source electrode of the thirteenth NMOS tube is connected with the second end of the first power supply; the drain electrode of the fourteenth NMOS tube is also connected with the second end of the first capacitor, and the source electrode of the fourteenth NMOS tube is also connected with the second end of the first power supply; the drain electrode of the ninth NMOS tube is connected with the first end of the first power supply, and the source electrode of the ninth NMOS tube is respectively connected with the first end of the fifth resistor and the first end of the sixth resistor; the second end of the first resistor is connected with the emitter of the first P-type triode; the base electrode and the collector electrode of the first P-type triode are connected with the second end of the first power supply; and the base electrode and the collector electrode of the second P-type triode are connected with the second end of the first power supply.
Optionally, each digital gating unit includes: the digital gating module and a plurality of trimming current control modules, each trimming current control module comprises: PMOS tube and trimming resistor; the first end of the digital gating module is connected with the differential input pair unit; the grid electrode of the PMOS tube is connected with the grid electrode of the ninth NMOS tube, the drain electrode of the PMOS tube is connected with the first end of the trimming resistor, and the source electrode of the PMOS tube is connected with the first end of the trimming resistor; the second end of the trimming resistor is connected with the second end of the first power supply.
In a second aspect, the present utility model provides an operational amplifier, including the digital trimming circuit described above, the operational amplifier comprising: the third PMOS tube, the first PMOS tube, the second PMOS tube and the active load; the grid electrode of the third PMOS tube is connected with the current source compensation unit, the source electrode of the third PMOS tube is connected with the first end of the first power supply, and the drain electrode of the third PMOS tube is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube; the grid electrode of the first PMOS tube is used as a non-inverting input end of an input signal, and the drain electrode of the first PMOS tube is connected with the active load; the grid electrode of the second PMOS tube is used as an inverting input end of an input signal, and the drain electrode of the second PMOS tube is connected with the active load; the active load is also connected to the second terminal of the first power supply.
In a third aspect, the present utility model provides an operational amplifier, including the digital trimming circuit, the operational amplifier including: the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the eleventh N-type triode, the twelfth N-type triode, the thirteenth N-type triode, the fourteenth N-type triode, the fifteenth N-type triode, the tenth resistor, the eleventh resistor and the second capacitor; the grid electrode of the third PMOS tube is connected with the current source compensation unit, the source electrode of the third PMOS tube is connected with the first end of the first power supply, and the drain electrode of the third PMOS tube is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube; the grid electrode of the first PMOS tube is used as a non-inverting input end of an input signal, and the drain electrode of the first PMOS tube is respectively connected with the collector electrode of the eleventh N-type triode and the base electrode of the thirteenth N-type triode; the grid electrode of the second PMOS tube is used as an inverting input end of an input signal, and the drain electrode of the second PMOS tube is respectively connected with the collector electrode of the twelfth N-type triode and the base electrode of the fourteenth N-type triode; the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with the source electrode of the first power supply, and the emitter electrode of the fourth PMOS tube is connected with the collector electrode of the fifteenth N-type triode; the base electrode of the eleventh N-type triode is connected with the base electrode of the twelfth N-type triode, and the emitter electrode of the eleventh N-type triode is connected with the second end of the first power supply; the emitter of the twelfth N-type triode is connected with the second end of the first power supply; two ends of the tenth resistor are respectively connected with the base electrode and the emitter electrode of the twelfth N-type triode; the collector of the thirteenth N-type triode is connected with the first end of the first power supply, and the emitter of the thirteenth N-type triode is connected with the base of the twelfth N-type triode; the collector of the fourteenth N-type triode is connected with the first end of the first power supply, and the emitter of the fourteenth N-type triode is connected with the first end of the eleventh resistor; the second end of the eleventh resistor is connected with the second end of the first power supply; the base electrode of the fifteenth N-type triode is connected with the emitter electrode of the fourteenth N-type triode, and the emitter electrode of the fifteenth N-type triode is connected with the second end of the first power supply.
In a fourth aspect, the present utility model provides an operational amplifier, including the digital trimming circuit, the operational amplifier including: a first PMOS tube, a second PMOS tube, a third PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a fifteenth NMOS tube and a sixteenth NMOS tube; the grid electrode of the third PMOS tube is connected with the current source compensation unit, the source electrode of the third PMOS tube is connected with the first end of the first power supply, and the drain electrode of the third PMOS tube is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube; the grid electrode of the first PMOS tube is used as a non-inverting input end of an input signal, and the drain electrode of the first PMOS tube is respectively connected with the digital gating module of the first digital gating unit, the drain electrode of the fifteenth NMOS tube and the drain electrode of the seventeenth NMOS tube; the grid electrode of the second PMOS tube is used as an inverting input end of an input signal, and the drain electrode of the second PMOS tube is respectively connected with the digital gating module of the second digital gating unit, the drain electrode of the sixteenth NMOS tube and the drain electrode of the eighteenth NMOS tube; the grid electrode of the nineteenth PMOS tube is respectively connected with the grid electrode of the twentieth PMOS tube and the drain electrode of the seventeenth PMOS tube, the source electrode of the nineteenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the nineteenth PMOS tube is connected with the source electrode of the seventeenth PMOS tube; the source electrode of the twentieth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the twentieth PMOS tube is connected with the source electrode of the eighteenth PMOS tube; the grid electrode of the seventeenth PMOS tube is connected with a third bias voltage and is connected with the grid electrode of the eighteenth PMOS tube, and the drain electrode of the seventeenth PMOS tube is connected with the drain electrode of the seventeenth NMOS tube; the drain electrode of the eighteenth PMOS tube is connected with the drain electrode of the eighteenth NMOS tube; the grid electrode of the seventeenth NMOS tube is connected with the second bias voltage and the grid electrode of the eighteenth NMOS tube; the grid electrode of the fifteenth NMOS tube is connected with a first bias voltage and the grid electrode of the sixteenth NMOS tube, and the source electrode of the fifteenth NMOS tube is respectively connected with the source electrode of the sixteenth NMOS tube and the second end of the first power supply.
Compared with the prior art, the utility model has the following beneficial effects:
the current source compensation unit is used for compensating the tail current source unit and generating a first compensation parameter only comprising a temperature coefficient of resistance, the trimming unit is used for trimming the input offset voltage, a second compensation parameter only comprising the temperature coefficient of resistance is generated by trimming, and the temperature coefficient of resistance of the second compensation parameter counteracts the temperature coefficient of resistance of the first compensation parameter, so that the trimming circuit of the technical scheme does not finally comprise parameters along with temperature change, thereby realizing that no additional parameters along with temperature change are introduced, and improving the trimming precision of the operational amplifier.
Drawings
FIG. 1 is a block diagram of a digital trimming circuit according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of a digital trimming circuit according to an embodiment of the present utility model;
FIG. 3 is a circuit diagram of a first digital trimming circuit according to an embodiment of the present utility model;
FIG. 4 is a circuit diagram of a second digital trimming circuit according to an embodiment of the present utility model;
fig. 5 is a block diagram of a third digital trimming circuit according to an embodiment of the present utility model.
Detailed Description
The technical scheme of the utility model is further described below with reference to the accompanying drawings and examples.
The following is a symbol description referred to in all the formulas of the present utility model:
μ P 、μ N channel carrier mobilities of PMOS and NMOS are shown, respectively.
V TP 、V TN The threshold voltages of PMOS and NMOS are shown, respectively.
C OX Representing the gate oxide capacitance per unit area.
I X The reference numerals denote current sources, PMOS also denote current magnitudes of current sources of the same name, and the following numerals denote serial numbers of the current sources.
RX represents the resistance, and the following figures represent the serial numbers of the resistances; r is R X The number of the resistor is indicated by the number of the resistor, and the number of the resistor is indicated by the following number.
I PXX The current of a port of a PMOS device is represented, wherein I represents a current symbol, P in a subscript PXX represents a PMOS transistor symbol, and the first X represents a device number, namely Arabic numerals 1, 2, 3 and the like; the second X represents the ports of the device, D (drain), G (gate) and S (source), respectively. I NXX The current of a certain port of a certain NMOS device is represented, wherein I represents a current symbol, N in a subscript NXX represents an NMOS transistor symbol, and the first X represents a device number which is an Arabic number of 1, 2, 3 and the like; the second X represents the ports of the device, D (drain), G (gate) and S (source), respectively.
V PXX Represents the voltage at a port of a PMOS device, wherein V represents a voltage sign, and P in the subscript PXX represents a PMOS type transistor The symbol, the first X represents the device number, the number is 1, 2, 3, etc. Arabic numerals; the second X represents the ports of the device, D (drain), G (gate) and S (source), respectively.
V NXX The voltage of a certain port of a certain NMOS device is represented, wherein V represents a voltage symbol, N in a subscript NXX represents an NMOS transistor symbol, and the first X represents a device number which is an Arabic number of 1, 2, 3 and the like; the second X represents the ports of the device, D (drain), G (gate) and S (source), respectively.
V GSPX The voltage between the gate and the source of a PMOS device is represented, where V represents a current symbol, G represents a gate in the subscript GSPXX, S represents a source, P represents a PMOS transistor symbol, X represents a device number, and the numbers are arabic numerals of 1, 2, 3, etc.
V GSNX The voltage between the gate and the source of an NMOS device is represented, where V represents a current symbol, G in the subscript GSNXX represents a gate, S represents a source, N represents an NMOS transistor symbol, X represents a device number, and the numbers are arabic numerals of 1, 2, 3, etc.
I QPXX Indicating the current of a port of a PNP device, wherein I indicates a current symbol, QP in a subscript QPX indicates a PNP bipolar transistor symbol, and the first X indicates a device number, and the numbers are Arabic numerals of 1, 2, 3 and the like; the second X represents the ports of the device, C (collector), B (base) and E (emitter), respectively. I QNXX The current of a certain port of an NPN device is represented, wherein I represents a current symbol, QN in a subscript QNXX represents an NPN bipolar transistor symbol, and the first X represents a device number which is an Arabic number of 1, 2, 3 and the like; the second X represents the ports of the device, C (collector), B (base) and E (emitter), respectively.
V QPXX The voltage of a certain port of a certain PNP device is represented, wherein V represents a voltage symbol, QP in a subscript QPX represents a PNP bipolar transistor symbol, and the first X represents a device number which is an Arabic number of 1, 2, 3 and the like; the second X represents the ports of the device, C (collector), B (base) and E (emitter), respectively.
V QNXX Indicating a certain end of a certain NPN deviceThe voltage at the port, where V represents the voltage sign, QN in the subscript QNXX represents the NPN bipolar transistor sign, the first X represents the device number, arabic numerals 1, 2, 3, etc.; the second X represents the ports of the device, C (collector), B (base) and E (emitter), respectively.
V BEQPX The voltage of the BE junction of a PNP device is represented, wherein V represents a voltage symbol, BE represents a BE junction in a subscript BEQPX, QP represents a PNP bipolar transistor symbol, X represents a device number, and Arabic numerals are numbered 1, 2, 3 and the like.
V BEQNX The voltage of the BE junction of an NPN device is represented, wherein V represents a voltage symbol, BE in the subscript BEQNXX represents a BE junction, QN represents an NPN bipolar transistor symbol, X represents a device number, and Arabic numerals are numbered 1, 2, 3 and the like.
I SQPX The saturation current of a PNP device is represented, where I represents a current symbol, S represents saturation in the subscript SQPX, QP represents a PNP bipolar transistor symbol, X represents a device number, and the numbers are arabic numerals of 1, 2, 3, etc.
I SQNX The saturation current of an NPN device is represented, wherein I represents a current symbol, S represents saturation in a subscript SQNX, QN represents an NPN bipolar transistor symbol, X represents a device number, and Arabic numerals of 1, 2, 3 and the like are used for solving the problem that the saturation current of the NPN device is not represented.
K XXXX Representing the ratio of the numbers of two matched MOS transistor devices, wherein the first X and the third X represent the types of the devices and are P or N respectively; the second, four X represent device numbers, being arabic numerals of 1, 2, 3, etc.
The first X in the subscript XX represents the sign of a PMOS or NMOS transistor and is P or N; the second X represents the device number, an arabic number of 1, 2, 3, etc.
K QXXXX Representing the ratio of the emitter areas of two bipolar transistor devices, wherein the first and third X represent the device type, P or N respectively; the second and the fourth X represent the number of the device, which is 1, 2. 3, etc.
V RX The voltage across a resistive element is represented, where V represents a voltage symbol, R represents a resistive symbol, X represents an element number, and the numbers are Arabic numerals 1, 2, 3, etc.
K RXRX The ratio of the resistance values of the two resistors is represented, two R in the subscript represent resistance symbols, two X represent element numbers, and Arabic numerals of 1, 2, 3 and the like are used.
Fig. 1 is a block diagram of a digital trimming circuit according to an embodiment of the present utility model, as shown in fig. 1, where the digital trimming circuit is applied to an operational amplifier, and the operational amplifier includes: the tail current source unit 210 is connected to the differential input pair unit 220, and is configured to provide an operating voltage to the differential input pair unit 220, and is characterized in that the digital trimming circuit: a current source compensation unit B0 and a trimming unit S;
the current source compensation unit B0 is connected to the tail current source unit 210, and is configured to compensate the tail current source unit 210 and generate a first compensation parameter including only a temperature coefficient of resistance;
the trimming unit S is connected to the differential input pair unit 220, and is configured to trim the input offset voltage generated by the differential input pair unit 220 and generate a second compensation parameter only including a temperature coefficient of resistance, where the temperature coefficient of resistance of the second compensation parameter counteracts the temperature coefficient of resistance of the first compensation parameter.
In this embodiment, the current source compensation unit B0 compensates the tail current source unit 210 and generates a first compensation parameter including only the temperature coefficient of resistance, the trimming unit S trims the input offset voltage, and the trimming unit S trims the input offset voltage to generate a second compensation parameter including only the temperature coefficient of resistance, and the temperature coefficient of resistance of the second compensation parameter counteracts the temperature coefficient of resistance of the first compensation parameter, so that the trimming circuit of the technical scheme does not include parameters along with temperature variation finally, thereby realizing that no additional parameters along with temperature variation are introduced, and improving trimming precision of the operational amplifier.
Specifically, fig. 2 is a schematic diagram of a digital trimming circuit according to an embodiment of the present utility model, as shown in fig. 2, in which I 0 Tail current output by the tail current unit, I 1 And I 2 A trimming current generated by the trimming unit S, and I 1 And I 2 At least one current is 0; p1 and P2 constitute a differential input pair unit 220 of the operational amplifier; transconductance of operational amplifier is
Wherein mu P 、C OX Changes with temperature;
by setting the current source compensation unit B0, the circuit is designed to make I 0 The expression of (2) can cancel out the relevant technological parameters, namely
Wherein X is an amount independent of the related process parameters of the MOS, and comprises only the first compensation parameter comprising only the temperature coefficient of resistance generated by the current source compensation unit B0, thereby
Consider the trimming current compensation parameter X, but consider V OS ＝V GP2 -V GP1 >0, in this case should be taken as I 1 Trimming, setting I 2 Is 0;
setting the input offset voltage after trimming as V' OS Then
Wherein,,
the above is a general expression for trimming voltage,the trimming operation can lead V at normal temperature within the trimming precision range TRIM As close as possible to V OS Thereby V 'at normal temperature' OS As small as possible;
i of setting trimming circuit 1 The circuit is designed to make the second compensation parameter only including the temperature coefficient of resistance
Wherein Y is a temperature insensitive parameter, then
From the above, V TRIM The temperature-sensitive parameters are not included, so that the trimming means does not additionally introduce temperature-dependent parameters.
It should be noted that, although an operational amplifier using PMOS as the differential pair is shown in the figure, the related derivation and conclusion are equally effective for an operational amplifier using NMOS as the differential pair, and the current source compensation unit B0 is not shown in fig. 2.
Fig. 3 is a circuit diagram of a first digital trimming circuit according to an embodiment of the present utility model, as shown in fig. 3, the trimming unit S includes: the trimming current source unit B1, the first digital gating unit S1 and the second digital gating unit S2; the trimming current source unit B1 is used for generating a first trimming current I1 and a second trimming current I2; the first digital gating unit S1 is connected to the trimming current source unit B1 and the non-inverting current input end of the differential input pair unit 220, respectively, and is configured to control a first trimming current I1 input by the trimming current source and generate a second compensation parameter including a temperature coefficient; the second digital gating unit S2 is connected to the trimming current source unit B1 and the negative phase current input end of the differential input pair unit 220, respectively, and is configured to control the second trimming current I2 input by the trimming current source and generate a second compensation parameter including a temperature coefficient of resistance; wherein the first digital gating unit S1 and the second digital gating unit S2 are not turned on at the same time.
In this embodiment, the trimming current source unit B1 generates the first trimming current I1 and the second trimming current I2, and the first digital gating unit S1 is used for controlling whether to direct the positive input end of the differential input pair unit 220, so as to implement the positive trimming of the operational amplifier; whether to invert the input terminal of the differential input pair unit 220 is controlled by the second digital gating unit S2 to implement inverting trimming of the operational amplifier.
As shown in fig. 3, the current source compensation unit B0 includes: a ninth PMOS tube P9, a tenth PMOS tube P10, a third resistor R3, a seventh NMOS tube N7 and an eighth NMOS tube N8; the grid electrode of the ninth PMOS tube P9 is connected with the drain electrode of the tenth PMOS tube P10, the source electrode of the ninth PMOS tube P9 is connected with the first end VDD of the first power supply, and the drain electrode of the ninth PMOS tube P9 is connected with the drain electrode of the seventh NMOS tube N7; the grid electrode of the tenth PMOS tube P10 is connected with the control end of the tail current source, the source electrode of the tenth PMOS tube P10 is connected with the first end VDD of the first power supply, and the drain electrode of the tenth PMOS tube P10 is connected with the drain electrode of the eighth NMOS tube N8 through a third resistor R3; the grid electrode of the seventh NMOS tube N7 is connected with the grid electrode of the eighth NMOS tube N8, the source electrode of the seventh NMOS tube N7 is connected with the second end VSS of the first power supply, and the grid electrode of the seventh NMOS tube N7 is connected with the drain electrode; the drain electrode of the eighth NMOS transistor N8 is connected to the second terminal VSS of the first power supply.
The trimming current source unit B1 includes: the band gap reference source VBG, the built-in operational amplifier A1, the ninth NMOS tube N9, the eighth PMOS tube P8 and the fourth resistor R4; the positive electrode of the band gap reference source VBG is connected with the non-inverting input end of the built-in operational amplifier A1, and the negative electrode of the band gap reference source VBG is connected with the second end VSS of the first power supply; the inverting input end of the built-in operational amplifier A1 is connected with the first end of the fourth resistor R4, and the output end of the built-in operational amplifier A1 is connected with the grid electrode of the ninth NMOS tube N9; the drain electrode of the ninth NMOS tube N9 is connected with the drain electrode of the eighth PMOS tube P8, and the source electrode of the ninth NMOS tube N9 is connected with the first end of the fourth resistor R4; the grid electrode of the eighth PMOS tube P8 is respectively connected with the control end of the first digital gating unit S1 and the control end of the second digital gating unit S2, the source electrode of the eighth PMOS tube P8 is connected with the first end of the first power supply end, and the drain electrode of the eighth PMOS tube P8 is connected with the grid electrode; the second end of the fourth resistor R4 is connected to the second end VSS of the first power supply.
Each digital gating unit includes: a plurality of PMOS tubes and a digital gating module; the grid electrode of each PMOS tube is connected with the grid electrode of the eighth PMOS tube P8, the source electrode of each PMOS tube is connected with the first end VDD of the first power supply, and the drain electrode of each PMOS tube is connected with the digital gating module; the digital strobe module is also connected to a differential input pair unit 220.
The operational amplifier includes: the third PMOS tube P3, the first PMOS tube P1, the second PMOS tube P2 and the active load; the grid electrode of the third PMOS tube P3 is connected with the current source compensation unit B0, the source electrode of the third PMOS tube P3 is connected with the first end VDD of the first power supply, and the drain electrode of the third PMOS tube P3 is respectively connected with the source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2; the grid electrode of the first PMOS tube P1 is used as a non-inverting input end of an input signal, and the drain electrode of the first PMOS tube P1 is connected with the active load; the grid electrode of the second PMOS tube P2 is used as an inverting input end of an input signal, and the drain electrode of the second PMOS tube P2 is connected with the active load; the active load is also connected to the second terminal VSS of the first power supply.
In the present embodiment, the current of the tenth PMOS transistor P10 in the current source compensation unit B0 is mirrored to the third PMOS transistor P3 according to a certain proportion to obtain I in fig. 2 0 ；
The seventh NMOS transistor N7 and the eighth NMOS transistor N8 form a current mirror, and the seventh NMOS transistor N7 and the eighth NMOS transistor N8 are matched and have the same size, so
I N7D ＝I N8D
Is obtained according to kirchhoff theorem
According to the characteristics of MOS
The ninth PMOS tube P9 and the tenth PMOS tube P10 are matched, the number of the actual devices of the ninth PMOS tube P9 is more than that of the tenth PMOS tube P10, and the PMOS tubes are formed by connecting a plurality of devices with the same size in parallel, namely
K P9P10 >1
Can obtain
Note that the PMOS threshold voltage and gate-source voltage are both negative, so
Because the source ends of the ninth PMOS tube P9 and the tenth PMOS tube P10 are short-circuited
Therefore, it is
Due toThe two sides are divided by->Obtaining the product
Square on both sides to obtain
The current of P10 is mirrored to P3 in proportion to obtain
Transconductance of operational amplifier
In the above, K P9P10 、K P3P10 、Are all dimensionless proportional parameters and do not change along with temperature; thus G M The temperature-dependent parameter in the expression of (2) is only the resistance R 3 The magnitude of the change with temperature varies with the process conditions.
The above description of the circuit structure and the associated analysis of the trimming current source unit B1 is only illustrative, where G can be implemented M Containing R alone 3 A circuit with a temperature-dependent parameter can be regarded as a temperature-coefficient-of-resistance compensation current source, i.e. the trimming current source unit B1.
The first digital gating unit S1 and the second digital gating unit S2 are respectively a group of PMOS tubes with equal-proportion amplified sizes, the first digital gating unit S1 and the second digital gating unit S2 are respectively used for mirroring the drain current of the eighth POMS tube, the first trimming current I1 and the second trimming current I2 which are proportional to the drain current of the eighth PMOS tube P8 can be output through the digital first digital gating unit S1 and the second digital gating unit S2, the digital gating module is used for controlling whether the trimming current flows or not, and at least one of the first trimming current I1 and the second trimming current I2 is 0 at the same time, namely
I 1 ＝KI P8D
I 2 ＝0
Or (b)
I 1 ＝0
I 2 ＝KI P8D
K is a proportionality constant obtained by digital gating circuit adjustment, and K does not change along with temperature;
can not consider V OS ＝V GP2 -V GP1 >0, the first trimming current I1 should be used for trimming and the second trimming current I2 should be set to 0 at this time
Setting the input offset voltage after trimming as V' OS Then
Wherein the method comprises the steps of
The digital trimming operation can adjust the proportion parameter K, and V is realized at normal temperature within the trimming precision range TRIM As close as possible to V OS Thereby V 'at normal temperature' OS As small as possible.
The current source compensation unit B0 enables the transconductance of the main body operational amplifier to be equal to
Thus (2)
When the circuit is designed, the third resistor R3 and the fourth resistor R4 select the same type of resistor, and the layout matching layout is ensured, so that the third resistor R3 and the fourth resistor R4 can keep the resistance values in proportion at all working temperatures, namely K R3R4 Remain unchanged at all operating temperatures, so
In the above formula, K R3R4 、K、K P9P10 、K P3P10 、Are all proportionality constants which do not change with temperature, and the band gap reference voltage V BG Is insensitive to temperature, thus obtaining trimming voltage V without additionally introducing parameters which change with temperature TRIM 。
Fig. 4 is a circuit diagram of a second digital trimming circuit according to an embodiment of the present utility model, as shown in fig. 4, the trimming current source unit B1 includes: twenty-first PMOS transistor P21, twenty-second PMOS transistor P22, third P-type transistor QP3, fourth P-type transistor QP4, sixth N-type transistor QN6, seventh N-type transistor QN7, first resistor R1, seventh resistor R7, ninth N-type transistor QN9, eighth resistor R8, eighth N-type transistor QN8, ninth resistor R9, eighth PMOS transistor P8, tenth N-type transistor QN10 and fourth resistor R4; the grid electrode of the twenty-first PMOS tube P21 is connected with the grid electrode of the twenty-second PMOS tube P22, the source electrode of the twenty-first PMOS tube P21 is connected with the first end VDD of the first power supply, and the drain electrode of the twenty-first PMOS tube P21 is respectively connected with the emitter electrode of the third P-type triode QP3, the emitter electrode of the fourth P-type triode QP4, the base electrode of the ninth N-type triode QN9 and the base electrode of the tenth N-type triode QN 10; the source electrode of the twenty-second PMOS tube P22 is connected with the first end VDD of the first power supply, the grid electrode of the twenty-second PMOS tube P22 is connected with the drain electrode, and the drain electrode of the twenty-second PMOS tube P22 is connected with the collector electrode of the eighth N-type triode QN 8; the base electrode of the third P-type triode QP3 is connected with the base electrode of the fourth P-type triode, and the collector electrode of the third P-type triode QP3 is connected with the collector electrode of the sixth N-type triode QN 6; the base electrode and the collector electrode of the fourth P-type triode QP4 are connected, and the collector electrode of the fourth P-type triode QP4 is connected with the emitter electrode of the seventh N-type triode QN 7; the base electrode of the sixth N-type triode QN6 is respectively connected with the base electrode of the seventh N-type triode QN7, and the emitter electrode of the sixth N-type triode QN6 is connected with the second end of the first resistor R1; the emitter of the seventh N-type triode QN7 is connected with the first end of the first resistor R1; a first end of the seventh resistor R7 is connected to the second end of the first resistor R1, and a second end of the seventh resistor R7 is connected to the second end VSS of the first power supply; the first end of the eighth resistor R8 is connected with the grid electrode of the seventh N-type triode QN7, and the second end of the eighth resistor R8 is connected with the second end VSS of the first power supply; the emitter of the ninth N-type triode QN9 is connected with the base of the eighth N-type triode QN 8; the grid electrode of the eighth PMOS tube P8 is respectively connected with the control ends of the first digital gating unit S1 and the second digital gating unit S2, the grid electrode of the eighth PMOS tube P8 is connected with the drain electrode, the source electrode of the eighth PMOS tube P8 is connected with the first end VDD of the first power supply, and the drain electrode of the eighth PMOS tube P8 is connected with the collector electrode of the tenth N-type triode QN 10; the emitter of the tenth N-type triode QN10 is connected to the second terminal VSS of the first power supply through the fourth resistor R4.
The operational amplifier includes: the third PMOS transistor P3, the first PMOS transistor P1, the second PMOS transistor P2, the fourth PMOS transistor P4, the eleventh N-type triode QN11, the twelfth N-type triode QN12, the thirteenth N-type triode QN13, the fourteenth N-type triode QN14, the fifteenth N-type triode QN15, the tenth resistor R10, the eleventh resistor R11 and the second capacitor C2; the grid electrode of the third PMOS tube P3 is connected with the current source compensation unit B0, the source electrode of the third PMOS tube P3 is connected with the first end VDD of the first power supply, and the drain electrode of the third PMOS tube P3 is respectively connected with the source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2; the grid electrode of the first PMOS tube P1 is used as a non-inverting input end of an input signal, and the drain electrode of the first PMOS tube P1 is respectively connected with the collector electrode of the eleventh N-type triode QN11 and the base electrode of the thirteenth N-type triode QN 13; the grid electrode of the second PMOS tube P2 is used as an inverting input end of an input signal, and the drain electrode of the second PMOS tube P2 is respectively connected with the collector electrode of the twelfth N-type triode QN12 and the base electrode of the fourteenth N-type triode QN 14; the grid electrode of the fourth PMOS tube P4 is connected with the grid electrode of the third PMOS tube P3, the source electrode of the fourth PMOS tube P4 is connected with the source electrode of the first power supply, and the emitter electrode of the fourth PMOS tube P4 is connected with the collector electrode of the fifteenth N-type triode QN 15; the base electrode of the eleventh N-type triode QN11 is connected with the base electrode of the twelfth N-type triode QN12, and the emitter electrode of the eleventh N-type triode QN11 is connected with the second end VSS of the first power supply; the emitter of the twelfth N-type triode QN12 is connected with the second end VSS of the first power supply; two ends of the tenth resistor R10 are respectively connected with the base electrode and the emitter electrode of the twelfth triode QN 12; the collector of the thirteenth N-type triode QN13 is connected with the first end VDD of the first power supply, and the emitter of the thirteenth N-type triode QN13 is connected with the base of the twelfth N-type triode QN 12; the collector of the fourteenth N-type triode QN14 is connected to the first end VDD of the first power supply, and the emitter of the fourteenth N-type triode QN14 is connected to the first end of the eleventh resistor R11; the second end of the eleventh resistor R11 is connected with the second end VSS of the first power supply; the base of the fifteenth N-type triode QN15 is connected to the emitter of the fourteenth N-type triode QN14, and the emitter of the fifteenth N-type triode QN15 is connected to the second terminal VSS of the first power supply. The structure of such an operational amplifier is often employed in BiCMOS processes to save power consumption.
In this embodiment, the fourth PMOS transistor P4 forms a second stage active load; the eleventh N-type triode QN11, the twelfth N-type triode QN12, the thirteenth N-type triode QN13 and the tenth resistor R10 form a first-stage active load; the fourteenth N-type triode QN14, the fifteenth N-type triode QN15 and the eleventh resistor R11 form a second stage input stage; the second capacitance C2 is a miller capacitance.
The current of the tenth PMOS tube P10 is mirrored to the third PMOS tube P3 to obtain the transconductance of the main operational amplifier as
The eighth N-type triode QN8, the ninth resistor R9 and the twenty-second PMOS tube P22 provide a feedback path for stabilizing the current of the twenty-first PMOS tube P21; the ninth N-type triode QN9 provides base currents of the sixth N-type triode QN6, the seventh N-type triode QN7 and the eighth N-type triode QN8, and simultaneously serves as a driving device to provide bias voltages for other circuits QN9E I.e. trimming the bandgap reference voltage output by the current source unit B1.
Due to
V BEQP3 ＝V BEQP4
Therefore, it is
I QP3C ＝I QP4C
Neglecting base current, there is
The sixth N-type triode QN6 is matched with the seventh N-type triode QN7, and the emitter area of the seventh N-type triode QN7 is larger than that of the sixth N-type triode QN6, namely
K QN7N6 >1
According to the characteristics of bipolar transistor, there are
V BEQN6 -V BEQN7 ＝V T ln(K QN7N6 )
So that
The voltage across the seventh resistor R7 is PTAT voltage, thereby obtaining
Due to V BEQP2 For NTAT voltage, V can be obtained after proper parameter design QN9E Is a bandgap reference voltage value;
the ninth N-type transistor QN9 and the tenth N-type transistor QN10 are matched and have the same emitter area, and the fourth resistor R4 and the eighth resistor R8 are matched and have the same resistance value, which is considered as
V QN10E ＝V QN9E
I.e. V QN10E Also a temperature insensitive bandgap reference voltage, thus
The first digital gating unit S1 and the second digital gating unit S2 are respectively a group of PMOS with equal-proportion amplified size and are used for mirroring the drain current of the eighth PMOS tube P8, the first digital gating unit S1 and the second digital gating unit S2 can output a first trimming current I1 and a second trimming current I2 which are proportional to the drain current of the eighth PMOS tube P8, and at the same time, at least one of the first trimming current I1 and the second trimming current I2 is 0, namely
I 1 ＝KI P8D
I 2 ＝0
Or (b)
I 1 ＝0
I 2 ＝KI P8D
K is a proportionality constant obtained by digital gating circuit adjustment, and K does not change along with temperature;
can not consider V OS ＝V GP2 -V GP1 >0, the first trimming current I1 should be used to trim and the second trimming current I2 should be set to 0 at this time
Setting the input offset voltage after trimming as V' OS Then
Wherein the method comprises the steps of
The digital trimming operation can adjust the proportion parameter K, and V is realized at normal temperature within the trimming precision range TRIM As close as possible to V OS Thereby V 'at normal temperature' OS As small as possible;
can be obtained by taking in transconductance expression
When the circuit is designed, the third resistor R3 and the fourth resistor R4 select the same type of resistor, and the layout matching layout is ensured, so that the third resistor R3 and the fourth resistor R4 can keep the resistance values in proportion at all working temperatures, namely K r3R4 Remain unchanged at all operating temperatures, so
In the above formula, K R3R4 、K、K P9P10 、K P3P10 、Are all proportionality constants which do not change with temperature, and the band gap reference voltage V QN10E Insensitive to temperature; thus, a trimming voltage V is obtained without additionally introducing a temperature-dependent parameter TRIM The method comprises the steps of carrying out a first treatment on the surface of the In summary, the adjustment means is realized without additionally introducing parameters which change along with temperature.
Fig. 5 is a block diagram of a third digital trimming circuit according to an embodiment of the present utility model, as shown in fig. 5, the current source compensation unit B0 includes: a ninth PMOS tube P9, a tenth PMOS tube P10, a third resistor R3, an eleventh PMOS tube, a twelfth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a seventh NMOS tube N7 and an eighth NMOS tube N8; the grid electrode of the ninth PMOS tube P9 is connected with the drain electrode of the tenth PMOS tube P10, the source electrode of the ninth PMOS tube P9 is connected with the first end VDD of the first power supply, and the drain electrode of the ninth PMOS tube P9 is connected with the source electrode of the eleventh PMOS tube; the grid electrode of the tenth PMOS tube P10 is connected with the control end of the tail current source, the source electrode of the tenth PMOS tube P10 is connected with the first end VDD of the first power supply, and the drain electrode of the tenth PMOS tube P10 is connected with the drain electrode of the twelfth PMOS tube through a third resistor R3; the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the twelfth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth NMOS tube; the grid electrode of the twelfth PMOS tube is connected with the drain electrode, the source electrode of the twelfth PMOS tube is connected with the second end of the third resistor R3, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the eleventh NMOS tube; the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, the drain electrode of the tenth NMOS tube is connected with the grid electrode, and the source electrode of the tenth NMOS tube is connected with the drain electrode of the seventh NMOS tube N7; the source electrode of the eleventh NMOS tube is connected with the drain electrode of the eighth NMOS tube N8; the grid electrode of the seventh NMOS tube N7 is connected with the grid electrode of the eighth NMOS tube N8, the drain electrode of the seventh NMOS tube N7 is connected with the grid electrode, the source electrode of the seventh NMOS tube N7 is connected with the second end of the first power end, and the source electrode of the eighth NMOS tube N8 is connected with the second end of the first power end.
The trimming current source unit B1 includes: thirteenth PMOS tube P13, fourteenth PMOS tube P14, fifteenth MOS tube P15, sixteenth MOS tube P16, twelfth NMOS tube N20, thirteenth NMOS tube N13, fourteenth NMOS tube N14, first capacitor C1, ninth NMOS tube N9, fifth resistor R5, sixth resistor R6, first resistor R1, first P-type triode QP1, second P-type triode QP2; the grid electrode of the thirteenth PMOS tube P13 is respectively connected with the grid electrode of the tenth PMOS tube P10 and the grid electrode of the fourteenth PMOS tube P14, the source electrode of the thirteenth PMOS tube P13 is connected with the first end VDD of the first power supply, and the drain electrode of the thirteenth PMOS tube P13 is connected with the source electrode of the fifteenth MOS tube P15 and the source electrode of the sixteenth MOS tube P16; the source electrode of the fourteenth PMOS tube P14 is connected with the first end VDD of the first power supply, and the drain electrode of the fourteenth PMOS tube P14 is connected with the drain electrode of the fourteenth NMOS tube N14 and the grid electrode of the ninth NMOS tube N9; the grid electrode of the fifteenth MOS tube P15 is connected with the second end of the fifth resistor R5 and the first end of the first resistor R1, and the drain electrode of the fifteenth MOS tube P15 is connected with the drain electrode of the twelfth NMOS tube N20; the grid electrode of the sixteenth MOS transistor P16 is respectively connected with the second end of the sixth resistor R6 and the emitter electrode of the second P-type triode QP2, and the drain electrode of the sixteenth MOS transistor P16 is connected with the drain electrode of the thirteenth NMOS transistor N13; the gate of the twelfth NMOS transistor N20 is connected to the gate of the thirteenth NMOS transistor N13, the drain of the twelfth NMOS transistor N20 is connected to the gate, and the source of the twelfth NMOS transistor N20 is connected to the second end VSS of the first power supply; the drain electrode of the thirteenth NMOS transistor N13 is further connected to the first end of the first capacitor C1 and the gate electrode of the fourteenth NMOS transistor N14, and the source electrode of the thirteenth NMOS transistor N13 is connected to the second end VSS of the first power supply; the drain electrode of the fourteenth NMOS tube N14 is also connected with the second end of the first capacitor C1, and the source electrode of the fourteenth NMOS tube N14 is also connected with the second end VSS of the first power supply; the drain electrode of the ninth NMOS tube N9 is connected with the first end VDD of the first power supply, and the source electrode of the ninth NMOS tube N9 is respectively connected with the first end of the fifth resistor R5 and the first end of the sixth resistor R6; the second end of the first resistor R1 is connected with the emitter of the first P-type triode QP 1; the base electrode and the collector electrode of the first P-type triode QP1 are connected with the second end VSS of the first power supply; the base and collector of the second P-type triode QP2 are connected to the second terminal VSS of the first power supply.
Each digital gating unit includes: the digital gating module and a plurality of trimming current control modules, each trimming current control module comprises: a PMOS tube and a trimming resistor RS; the first end of the digital gating module is connected with the differential input pair unit 220; the grid electrode of the PMOS tube is connected with the grid electrode of the ninth NMOS tube N9, the drain electrode of the PMOS tube is connected with the first end of the trimming resistor RS, and the source electrode of the PMOS tube is connected with the first end of the trimming resistor RS; the second end of the trimming resistor RS is connected with the second end VSS of the first power supply.
The operational amplifier includes: a third PMOS tube P3, a first PMOS tube P1, a second PMOS tube P2, a seventeenth MOS tube P17, an eighteenth MOS tube P18, a nineteenth MOS tube P19, a twentieth MOS tube P20, a seventeenth NMOS tube N17, an eighteenth NMOS tube N18, a fifteenth NMOS tube N15 and a sixteenth NMOS tube N16; the grid electrode of the third PMOS tube P3 is connected with the current source compensation unit B0, the source electrode of the third PMOS tube P3 is connected with the first end VDD of the first power supply, and the drain electrode of the third PMOS tube P3 is respectively connected with the source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2; the grid electrode of the first PMOS tube P1 is used as a non-inverting input end of an input signal, and the drain electrode of the first PMOS tube P1 is respectively connected with the digital gating module of the first digital gating unit S1, the drain electrode of the fifteenth NMOS tube N15 and the drain electrode of the seventeenth NMOS tube N17; the grid electrode of the second PMOS transistor P2 is used as an inverting input end of an input signal, and the drain electrode of the second PMOS transistor P2 is respectively connected with the digital gating module of the second digital gating unit S2, the drain electrode of the sixteenth NMOS transistor N16 and the drain electrode of the eighteenth NMOS transistor N18; the grid electrode of the nineteenth MOS tube P19 is respectively connected with the grid electrode of the twentieth MOS tube P20 and the drain electrode of the seventeenth MOS tube P17, the source electrode of the nineteenth MOS tube P19 is connected with the first end VDD of the first power supply, and the drain electrode of the nineteenth MOS tube P19 is connected with the source electrode of the seventeenth MOS tube P17; the source electrode of the twentieth MOS tube P20 is connected with the first end VDD of the first power supply, and the drain electrode of the twentieth MOS tube P20 is connected with the source electrode of the eighteenth MOS tube P18; the gate of the seventeenth MOS transistor P17 is connected to the third bias voltage V3 and to the gate of the eighteenth MOS transistor P18, and the drain of the seventeenth MOS transistor P17 is connected to the drain of the seventeenth NMOS transistor N17; the drain electrode of the eighteenth MOS tube P18 is connected with the drain electrode of the eighteenth NMOS tube N18; the grid electrode of the seventeenth NMOS tube N17 is connected with the second bias voltage V2 and the grid electrode of the eighteenth NMOS tube N18; the grid electrode of the fifteenth NMOS tube N15 is connected with a first bias voltage V1 and the grid electrode of the sixteenth NMOS tube N16, and the source electrode of the fifteenth NMOS tube N15 is respectively connected with the source electrode of the sixteenth NMOS tube N16 and the second end VSS of the first power supply.
In this embodiment, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a nineteenth MOS transistor P19, and a twentieth MOS transistor P20 form an active load, and a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a seventeenth MOS transistor P17, and an eighteenth MOS transistor P18 are common-gate common-source transistors of the active load;
in the current source compensation unit B0, a tenth NMOS tube, an eleventh PMOS tube and a twelfth PMOS tube form a common gate structure so as to keep the consistency of current under different power supply voltages;
the current of the tenth PMOS tube P10 is mirrored to the third PMOS tube P3 to obtain the transconductance of the main operational amplifier as
The standard CMOS technology provides parasitic PNP devices with bases of a first P-type triode QP1 and a second P-type triode QP2 connected with a negative power supply;
the thirteenth PMOS tube P13, the fourteenth PMOS tube P14, the fifteenth MOS tube P15, the sixteenth MOS tube P16, the twelfth NMOS tube N20, the thirteenth NMOS tube N13, the fourteenth NMOS tube N14 and the first capacitor C1 form a built-in operational amplifier A1, wherein the thirteenth PMOS tube P13 provides tail current, the fourteenth PMOS tube P14 provides second-stage bias current, the fifteenth MOS tube P15 and the sixteenth MOS tube P16 form a differential pair, the twelfth NMOS tube N20 and the thirteenth NMOS tube N13 form an active load, the fourteenth NMOS tube N14 is a second-stage input device, and the first capacitor C1 is a Miller compensation capacitor.
Due to the short-circuit characteristics of the built-in operational amplifier A1, there are
V GP15 ＝V GP16
The fifth resistor R5 and the sixth resistor R6 are matched and have the same resistance, and the voltages at the two ends of the fifth resistor R5 and the sixth resistor R6 are equal, so that the currents flowing through the fifth resistor R5 and the sixth resistor R6 are equal
I QP1C ＝I QP2C
Setting the first P-type triode QP1 and the second P-type triode QP2QP2 to be matched, wherein the emitter area of QP1 is larger than that of QP2, namely
K QP1P2 >1
According to the characteristics of bipolar transistor, there are
I sQP1 ＝K QP1P2 I SQP2
Calculated to obtain
V BEQP2 -V BEQP1 ＝V T ln(K QP1P2 )
Due to
V GP15 ＝V GP16 ＝V BEQP2
Therefore, it is
Thus (2)
So that
It can be seen that the voltage across the sixth resistor R6 is PTAT voltage, thereby obtaining
Due to V BEQP2 For NTAT voltage, V can be obtained after proper parameter design N9S Is a bandgap reference voltage value;
the first digital gating unit S1 and the second digital gating unit S2 are respectively formed by connecting a group of NMOS with equal-proportion amplified sizes and resistors with the same proportion in series with the sources of the corresponding NMOS;
the NMOS sizes inside the first and second digital gating units S1 and S2 are set so that the ratio of the drain current to the width-to-length ratio is equal to that of the ninth NMOS transistor N9 when the first and second digital gating units S and S2 are gated, and the ratio of the drain current to the width-to-length ratio is increased as much as possibleThis allows the source voltage of the trousers-washed NMOS in the first and second digital washing units S1 and S2 to be approximately equal to the bandgap reference voltage V SN9 ；
Let the unit current in S1, S2, i.e. the path of resistance with the smallest configuration current be R S The final arrangement current is K times the unit current, and V may be considered OS ＝V GP2 -V GP1 In the case of > 0, the first trimming current I1 should be used to trim and the second trimming current 12 should be set to 0 at this time, so
Setting the input offset voltage after trimming as V' OS Then
Wherein the method comprises the steps of
The digital trimming operation can adjust the proportion parameter K, and V is realized at normal temperature within the trimming precision range TRIM As close as possible to V OS Thereby V 'at normal temperature' OS As small as possible.
Can be obtained by taking in transconductance expression
When the circuit is designed, the third resistor R3 and the trimming resistor RS select the same type of resistor, and the layout matching layout is ensured, so that the third resistor R3 and the trimming resistor RS can keep the resistance values in proportion at all working temperatures, namely K R3RS Remain unchanged at all operating temperatures, so
In the above formula, K R3RS 、K、K P9P10 、K P3P10 、Are all proportionality constants which do not change with temperature, and the band gap reference voltage V N9S Is insensitive to temperature, thus obtaining trimming voltage V without additionally introducing parameters which change with temperature TRIM 。
It should be noted that, the current source compensation unit B0, the trimming current source unit B1 and the digital gating unit in the specification may be combined with each other, and the combination method is not limited to the combination method of the present utility model, and may be set according to actual needs when in use.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above embodiments are only for illustrating the technical solution of the present utility model and not for limiting the same, and although the present utility model has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present utility model, which is intended to be covered by the scope of the claims of the present utility model.

Claims (12)

1. A digital trimming circuit for use in an operational amplifier, the operational amplifier comprising: the tail current source unit is connected with the differential input pair unit and is used for providing working voltage for the differential input pair unit, and the digital trimming circuit is characterized in that: a current source compensation unit and a trimming unit;
the current source compensation unit is connected with the tail current source unit and is used for compensating the tail current source unit and generating a first compensation parameter only comprising a temperature coefficient of resistance;
the trimming unit is connected with the differential input pair unit and is used for trimming the input offset voltage generated by the differential input pair unit and generating a second compensation parameter only comprising a temperature coefficient of resistance, and the temperature coefficient of resistance of the second compensation parameter counteracts the temperature coefficient of resistance of the first compensation parameter.
2. The digital trimming circuit of claim 1, wherein the trimming unit comprises: the trimming current source unit, the first digital gating unit and the second digital gating unit;
the trimming current source unit is used for generating a first trimming current and a second trimming current;
The first digital gating unit is respectively connected with the trimming current source unit and the normal-phase current input end of the differential input pair unit, and is used for controlling a first trimming current input by the trimming current source and generating a second compensation parameter comprising a temperature coefficient of resistance;
the second digital gating unit is respectively connected with the trimming current source unit and the negative-phase current input end of the differential input pair unit, and is used for controlling the second trimming current input by the trimming current source and generating a second compensation parameter comprising a temperature coefficient of resistance;
wherein the first digital gating unit and the second digital gating unit are not turned on at the same time.
3. The digital trimming circuit of claim 1, wherein the current source compensation unit comprises: a ninth PMOS tube, a tenth PMOS tube, a third resistor, a seventh NMOS tube and an eighth NMOS tube;
the grid electrode of the ninth PMOS tube is connected with the drain electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the ninth PMOS tube is connected with the drain electrode of the seventh NMOS tube;
the grid electrode of the tenth PMOS tube is connected with the control end of the tail current source, the source electrode of the tenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the eighth NMOS tube through a third resistor;
The grid electrode of the seventh NMOS tube is connected with the grid electrode of the eighth NMOS tube, the source electrode of the seventh NMOS tube is connected with the second end of the first power supply, and the grid electrode of the seventh NMOS tube is connected with the drain electrode;
and the drain electrode of the eighth NMOS tube is connected with the second end of the first power supply.
4. The digital trimming circuit of claim 1, wherein the current source compensation unit comprises: a ninth PMOS tube, a tenth PMOS tube, a third resistor, an eleventh PMOS tube, a twelfth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a seventh NMOS tube and an eighth NMOS tube;
the grid electrode of the ninth PMOS tube is connected with the drain electrode of the tenth PMOS tube, the source electrode of the ninth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the ninth PMOS tube is connected with the source electrode of the eleventh PMOS tube;
the grid electrode of the tenth PMOS tube is connected with the control end of the tail current source, the source electrode of the tenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the tenth PMOS tube is connected with the drain electrode of the twelfth PMOS tube through a third resistor;
the grid electrode of the eleventh PMOS tube is connected with the grid electrode of the twelfth PMOS tube, and the drain electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth NMOS tube;
The grid electrode of the twelfth PMOS tube is connected with the drain electrode, the source electrode of the twelfth PMOS tube is connected with the second end of the third resistor, and the drain electrode of the twelfth PMOS tube is connected with the drain electrode of the eleventh NMOS tube;
the grid electrode of the tenth NMOS tube is connected with the grid electrode of the eleventh NMOS tube, the drain electrode of the tenth NMOS tube is connected with the grid electrode, and the source electrode of the tenth NMOS tube is connected with the drain electrode of the seventh NMOS tube;
the source electrode of the eleventh NMOS tube is connected with the drain electrode of the eighth NMOS tube;
the grid electrode of the seventh NMOS tube is connected with the grid electrode of the eighth NMOS tube, the drain electrode of the seventh NMOS tube is connected with the grid electrode, and the source electrode of the seventh NMOS tube is connected with the second end of the first power end
And the source electrode of the eighth NMOS tube is connected with the second end of the first power supply end.
5. The digital trimming circuit of claim 2, wherein the trimming current source unit comprises: the band gap reference source, the built-in operational amplifier, the ninth NMOS tube, the eighth PMOS tube and the fourth resistor;
the positive electrode of the band gap reference source is connected with the non-inverting input end of the built-in operational amplifier, and the negative electrode of the band gap reference source is connected with the second end of the first power supply;
The inverting input end of the built-in operational amplifier is connected with the first end of the fourth resistor, and the output end of the built-in operational amplifier is connected with the grid electrode of the ninth NMOS tube;
the drain electrode of the ninth NMOS tube is connected with the drain electrode of the eighth PMOS tube, and the source electrode of the ninth NMOS tube is connected with the first end of the fourth resistor;
the grid electrode of the eighth PMOS tube is respectively connected with the control end of the first digital gating unit and the control end of the second digital gating unit, the source electrode of the eighth PMOS tube is connected with the first end of the first power supply end, and the drain electrode of the eighth PMOS tube is connected with the grid electrode;
the second end of the fourth resistor is connected with the second end of the first power supply.
6. The digital trimming circuit of claim 2, wherein the trimming current source unit comprises: a twenty-first PMOS transistor, a twenty-second PMOS transistor, a third P-type triode, a fourth P-type triode, a sixth N-type triode, a seventh N-type triode, a first resistor, a seventh resistor, a ninth N-type triode, an eighth resistor, an eighth N-type triode, a ninth resistor, an eighth PMOS transistor, a tenth N-type triode and a fourth resistor;
the grid electrode of the twenty-first PMOS tube is connected with the grid electrode of the twenty-second PMOS tube, the source electrode of the twenty-first PMOS tube is connected with the first end of the first power supply, and the drain electrode of the twenty-first PMOS tube is respectively connected with the emitter electrode of the third P-type triode, the emitter electrode of the fourth P-type triode, the base electrode of the ninth N-type triode and the base electrode of the tenth N-type triode;
The source electrode of the twenty-second PMOS tube is connected with the first end of the first power supply, the grid electrode of the twenty-second PMOS tube is connected with the drain electrode, and the drain electrode of the twenty-second PMOS tube is connected with the collector electrode of the eighth N-type triode;
the base electrode of the third P-type triode is connected with the base electrode of the fourth P-type triode, and the collector electrode of the third P-type triode is connected with the collector electrode of the sixth N-type triode;
the base electrode and the collector electrode of the fourth P-type triode are connected, and the collector electrode of the fourth P-type triode is connected with the emitter electrode of the seventh N-type triode;
the base electrode of the sixth N-type triode is respectively connected with the base electrode of the seventh N-type triode, and the emitter electrode of the sixth N-type triode is connected with the second end of the first resistor;
the emitter of the seventh N-type triode is connected with the first end of the first resistor;
the first end of the seventh resistor is connected with the second end of the first resistor, and the second end of the seventh resistor is connected with the second end of the first power supply;
the first end of the eighth resistor is connected with the grid electrode of the seventh N-type triode, and the second end of the eighth resistor is connected with the second end of the first power supply;
The emitter of the ninth N-type triode is connected with the base of the eighth N-type triode;
the grid electrode of the eighth PMOS tube is respectively connected with the control ends of the first digital gating unit and the second digital gating unit, the grid electrode of the eighth PMOS tube is connected with the drain electrode, the source electrode of the eighth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the eighth PMOS tube is connected with the collector electrode of the tenth N-type triode;
and the emitter of the tenth N-type triode is connected with the second end of the first power supply through the fourth resistor.
7. A digital trimming circuit according to claim 5 or 6, wherein each digital gating cell comprises: a plurality of PMOS tubes and a digital gating module;
the grid electrode of each PMOS tube is connected with the grid electrode of the eighth PMOS tube, the source electrode of each PMOS tube is connected with the first end of the first power supply, and the drain electrode of each PMOS tube is connected with the digital gating module;
the digital gating module is also connected with the differential input pair unit.
8. The digital trimming circuit of claim 2, wherein the trimming current source unit comprises: a thirteenth PMOS tube, a fourteenth PMOS tube, a fifteenth PMOS tube, a sixteenth PMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a first capacitor, a ninth NMOS tube, a fifth resistor, a sixth resistor, a first P-type triode and a second P-type triode;
The grid electrode of the thirteenth PMOS tube is respectively connected with the grid electrodes of the current source compensation unit and the fourteenth PMOS tube, the source electrode of the thirteenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the thirteenth PMOS tube is connected with the source electrode of the fifteenth PMOS tube and the source electrode of the sixteenth PMOS tube;
the source electrode of the fourteenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the fourteenth PMOS tube is connected with the drain electrode of the fourteenth NMOS tube and the grid electrode of the ninth NMOS tube;
the grid electrode of the fifteenth PMOS tube is connected with the second end of the fifth resistor and the first end of the first resistor, and the drain electrode of the fifteenth PMOS tube is connected with the drain electrode of the twelfth NMOS tube;
the grid electrode of the sixteenth PMOS tube is respectively connected with the second end of the sixth resistor and the emitter electrode of the second P-type triode, and the drain electrode of the sixteenth PMOS tube is connected with the drain electrode of the thirteenth NMOS tube;
the grid electrode of the twelfth NMOS tube is connected with the grid electrode of the thirteenth NMOS tube, the drain electrode of the twelfth NMOS tube is connected with the grid electrode, and the source electrode of the twelfth NMOS tube is connected with the second end of the first power supply;
The drain electrode of the thirteenth NMOS tube is also connected with the first end of the first capacitor and the grid electrode of the fourteenth NMOS tube respectively, and the source electrode of the thirteenth NMOS tube is connected with the second end of the first power supply;
the drain electrode of the fourteenth NMOS tube is also connected with the second end of the first capacitor, and the source electrode of the fourteenth NMOS tube is also connected with the second end of the first power supply;
the drain electrode of the ninth NMOS tube is connected with the first end of the first power supply, and the source electrode of the ninth NMOS tube is respectively connected with the first end of the fifth resistor and the first end of the sixth resistor;
the second end of the first resistor is connected with the emitter of the first P-type triode;
the base electrode and the collector electrode of the first P-type triode are connected with the second end of the first power supply;
and the base electrode and the collector electrode of the second P-type triode are connected with the second end of the first power supply.
9. The digital trimming circuit of claim 7, wherein each digital gating cell comprises: the digital gating module and a plurality of trimming current control modules, each trimming current control module comprises: PMOS tube and trimming resistor;
the first end of the digital gating module is connected with the differential input pair unit;
The grid electrode of the PMOS tube is connected with the trimming current source, the drain electrode of the PMOS tube is connected with the first end of the trimming resistor, and the source electrode of the PMOS tube is connected with the first end of the trimming resistor;
the second end of the trimming resistor is connected with the second end of the first power supply.
10. An operational amplifier comprising the digital trimming circuit of any one of claims 1-9, the operational amplifier comprising: the third PMOS tube, the first PMOS tube, the second PMOS tube and the active load;
the grid electrode of the third PMOS tube is connected with the current source compensation unit, the source electrode of the third PMOS tube is connected with the first end of the first power supply, and the drain electrode of the third PMOS tube is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube;
the grid electrode of the first PMOS tube is used as a non-inverting input end of an input signal, and the drain electrode of the first PMOS tube is connected with the active load;
the grid electrode of the second PMOS tube is used as an inverting input end of an input signal, and the drain electrode of the second PMOS tube is connected with the active load;
the active load is also connected to the second terminal of the first power supply.
11. An operational amplifier comprising the digital trimming circuit of any one of claims 1-9, the operational amplifier comprising: the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the eleventh N-type triode, the twelfth N-type triode, the thirteenth N-type triode, the fourteenth N-type triode, the fifteenth N-type triode, the tenth resistor, the eleventh resistor and the second capacitor;
The grid electrode of the third PMOS tube is connected with the current source compensation unit, the source electrode of the third PMOS tube is connected with the first end of the first power supply, and the drain electrode of the third PMOS tube is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube;
the grid electrode of the first PMOS tube is used as a non-inverting input end of an input signal, and the drain electrode of the first PMOS tube is respectively connected with the collector electrode of the eleventh N-type triode and the base electrode of the thirteenth N-type triode;
the grid electrode of the second PMOS tube is used as an inverting input end of an input signal, and the drain electrode of the second PMOS tube is respectively connected with the collector electrode of the twelfth N-type triode and the base electrode of the fourteenth N-type triode;
the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, the source electrode of the fourth PMOS tube is connected with the source electrode of the first power supply, and the emitter electrode of the fourth PMOS tube is connected with the collector electrode of the fifteenth N-type triode;
the base electrode of the eleventh N-type triode is connected with the base electrode of the twelfth N-type triode, and the emitter electrode of the eleventh N-type triode is connected with the second end of the first power supply;
the emitter of the twelfth N-type triode is connected with the second end of the first power supply; two ends of the tenth resistor are respectively connected with the base electrode and the emitter electrode of the twelfth N-type triode;
The collector of the thirteenth N-type triode is connected with the first end of the first power supply, and the emitter of the thirteenth N-type triode is connected with the base of the twelfth N-type triode;
the collector of the fourteenth N-type triode is connected with the first end of the first power supply, and the emitter of the fourteenth N-type triode is connected with the first end of the eleventh resistor;
the second end of the eleventh resistor is connected with the second end of the first power supply;
the base electrode of the fifteenth N-type triode is connected with the emitter electrode of the fourteenth N-type triode, and the emitter electrode of the fifteenth N-type triode is connected with the second end of the first power supply.
12. An operational amplifier comprising the digital trimming circuit of any one of claims 2-9, the operational amplifier comprising: a first PMOS tube, a second PMOS tube, a third PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a fifteenth NMOS tube and a sixteenth NMOS tube;
the grid electrode of the third PMOS tube is connected with the current source compensation unit, the source electrode of the third PMOS tube is connected with the first end of the first power supply, and the drain electrode of the third PMOS tube is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube;
The grid electrode of the first PMOS tube is used as a non-inverting input end of an input signal, and the drain electrode of the first PMOS tube is respectively connected with the digital gating module of the first digital gating unit, the drain electrode of the fifteenth NMOS tube and the drain electrode of the seventeenth NMOS tube;
the grid electrode of the second PMOS tube is used as an inverting input end of an input signal, and the drain electrode of the second PMOS tube is respectively connected with the digital gating module of the second digital gating unit, the drain electrode of the sixteenth NMOS tube and the drain electrode of the eighteenth NMOS tube;
the grid electrode of the nineteenth PMOS tube is respectively connected with the grid electrode of the twentieth PMOS tube and the drain electrode of the seventeenth PMOS tube, the source electrode of the nineteenth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the nineteenth PMOS tube is connected with the source electrode of the seventeenth PMOS tube;
the source electrode of the twentieth PMOS tube is connected with the first end of the first power supply, and the drain electrode of the twentieth PMOS tube is connected with the source electrode of the eighteenth PMOS tube;
the grid electrode of the seventeenth PMOS tube is connected with a third bias voltage and is connected with the grid electrode of the eighteenth PMOS tube, and the drain electrode of the seventeenth PMOS tube is connected with the drain electrode of the seventeenth NMOS tube;
The drain electrode of the eighteenth PMOS tube is connected with the drain electrode of the eighteenth NMOS tube;
the grid electrode of the seventeenth NMOS tube is connected with the second bias voltage and the grid electrode of the eighteenth NMOS tube;
the grid electrode of the fifteenth NMOS tube is connected with a first bias voltage and the grid electrode of the sixteenth NMOS tube, and the source electrode of the fifteenth NMOS tube is respectively connected with the source electrode of the sixteenth NMOS tube and the second end of the first power supply.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116805859A (en) * 2023-08-28 2023-09-26 江苏润石科技有限公司 Operational amplifier offset voltage regulation circuit and method
CN118100816A (en) * 2024-04-22 2024-05-28 基合半导体（宁波）有限公司 Operational amplifier structure and integrated circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116805859A (en) * 2023-08-28 2023-09-26 江苏润石科技有限公司 Operational amplifier offset voltage regulation circuit and method
CN116805859B (en) * 2023-08-28 2023-11-07 江苏润石科技有限公司 Operational amplifier offset voltage regulation circuit and method
CN118100816A (en) * 2024-04-22 2024-05-28 基合半导体（宁波）有限公司 Operational amplifier structure and integrated circuit
CN118100816B (en) * 2024-04-22 2024-07-12 基合半导体（宁波）有限公司 Operational amplifier structure and integrated circuit

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