CN219162686U - I2C test control circuit - Google Patents
I2C test control circuit Download PDFInfo
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- CN219162686U CN219162686U CN202223002498.4U CN202223002498U CN219162686U CN 219162686 U CN219162686 U CN 219162686U CN 202223002498 U CN202223002498 U CN 202223002498U CN 219162686 U CN219162686 U CN 219162686U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The utility model provides an I2C test control circuit which comprises an IO interface unit and a plurality of voltage sources, wherein an SDA terminal of the IO interface unit is grounded through a zeroth resistor, an SDAI terminal of the IO interface unit is grounded through a first resistor, the IO interface unit comprises an LVS_LH unit, a zeroth MOS tube, a first buffer, a second buffer and a third buffer which are mutually connected in series, an SDAO terminal is externally connected to an input end of the LVS_LH unit through a first inverter, an output end of the LVS_LH unit is connected with a grid electrode of the zeroth MOS tube, an SDA terminal is externally connected to an input end of the first buffer, an output end of the first buffer is connected with an input end of the second buffer, an output end of the second buffer is connected with an input end of the third buffer, and an SDAI terminal is externally connected to an output end of the third buffer. The utility model realizes the testing process of the I2C signal, and has simple circuit structure.
Description
Technical Field
The utility model relates to the technical field of electronics, in particular to an I2C test control circuit.
Background
I2C is a simple, bi-directional two-wire synchronous serial bus. It requires only two wires to transfer information between devices connected to the bus. The master device is used to initiate the bus transfer of data and generate a clock to open the transfer device, where any addressed device is considered a slave device. If the host computer is to send data to the slave device, the host computer firstly addresses the slave device, then actively sends the data to the slave device, and finally the host computer terminates the data transmission; if the host is to receive data from the slave, the slave is addressed by the master first, then the host receives data sent by the slave, and finally the host terminates the receiving process. In this case, the host is responsible for generating the timing clock and terminating the data transfer.
Disclosure of Invention
In view of the above, the present utility model provides an I2C test control circuit.
In order to solve the technical problems, the utility model adopts the following technical scheme: the utility model provides an I2C test control circuit, includes IO interface unit and a plurality of voltage source, the SDA terminal of IO interface unit passes through zero resistance ground connection, the SDAI terminal of IO interface unit passes through first resistance ground connection, IO interface unit includes LVS_LH unit, zeroth MOS pipe, first buffer, second buffer and the third buffer of concatenating each other, the input of LVS_LH unit has the SDAO terminal through the external connection of first phase inverter, the output of LVS_LH unit links to each other with the grid of zeroth MOS pipe, the external connection of the input of first buffer has the SDA terminal, the output of first buffer with the input of second buffer links to each other, the output of second buffer with the input of third buffer links to each other, the output of third buffer has the SDAI terminal.
In the present utility model, preferably, the first buffer includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor, wherein the gate of the eighth MOS transistor is connected to the drain of the first MOS transistor, the drain of the eighth MOS transistor is connected to the source of the second MOS transistor, the drain of the eighth MOS transistor is connected to the source of the sixth MOS transistor, the drain of the sixth MOS transistor is connected to the drain of the seventh MOS transistor, the drain of the second MOS transistor is connected to the drain of the third MOS transistor, the source of the third MOS transistor is connected to the drain of the first MOS transistor, the drain of the first MOS transistor is connected to the source of the seventh MOS transistor, the gate of the first MOS transistor is connected to the gate of the third MOS transistor, the drain of the seventh MOS transistor is connected to the drain of the fifth MOS transistor, and the drain of the fifth MOS transistor is connected to the drain of the fifth MOS transistor.
In the present utility model, preferably, the first MOS transistor, the third MOS transistor, the fourth MOS transistor, and the seventh MOS transistor are all N-type MOS transistors.
In the present utility model, preferably, the second MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are all P-type MOS transistors.
In the present utility model, preferably, the lvs_lh unit includes a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, a second inverter, and a third inverter, wherein a gate of the tenth MOS transistor is connected to a drain of the eleventh MOS transistor, a drain of the tenth MOS transistor is connected to a drain of the thirteenth MOS transistor, a drain of the eleventh MOS transistor is connected to a drain of the twelfth MOS transistor, a source of the twelfth MOS transistor is connected to a drain of the sixteenth MOS transistor, a gate of the sixteenth MOS transistor is connected to a gate of the seventeenth MOS transistor, a gate of the seventeenth MOS transistor is connected to an output terminal of the second inverter, an input terminal of the second inverter is connected to an output terminal of the third inverter, an input terminal of the third inverter is used as an input terminal of the lvs_lh unit, a gate of the thirteenth MOS transistor is connected to a drain of the thirteenth MOS transistor, a drain of the fifteenth MOS transistor is connected to a drain of the seventeenth MOS transistor, and a drain of the seventeenth MOS transistor is connected to a drain of the seventeenth MOS transistor.
In the present utility model, preferably, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, and the sixteenth MOS transistor are N-type MOS transistors.
In the present utility model, preferably, the tenth MOS transistor, the eleventh MOS transistor, the fifteenth MOS transistor, and the seventeenth MOS transistor are P-type MOS transistors.
The utility model has the advantages and positive effects that: the input end of the LVS_LH unit is externally connected with an SDAO terminal through a first inverter, the output end of the LVS_LH unit is connected with the grid electrode of the zeroth MOS tube, the input end of the first buffer is externally connected with an SDA terminal, the output end of the first buffer is connected with the input end of the second buffer, the output end of the second buffer is connected with the input end of the third buffer, the output end of the third buffer is externally connected with an SDAI terminal, and the I2C signal testing process is realized through the mutual matching between the LVS_LH unit and the voltage sources.
Drawings
The accompanying drawings are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate the utility model and together with the embodiments of the utility model, serve to explain the utility model. In the drawings:
FIG. 1 is an overall block diagram of an I2C test control circuit of the present utility model;
FIG. 2 is a schematic diagram of an IO interface unit of an I2C test control circuit of the present utility model;
FIG. 3 is a schematic diagram of a first buffer of an I2C test control circuit of the present utility model;
fig. 4 is a schematic diagram of an lvs_lh cell of an I2C test control circuit of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When a component is considered to be "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1 and fig. 2, the utility model provides an I2C test control circuit, which comprises an IO interface unit and a plurality of voltage sources, wherein an SDA terminal of the IO interface unit is grounded through a zeroth resistor, an SDA terminal of the IO interface unit is grounded through a first resistor, the IO interface unit comprises an lvs_lh unit, a zeroth MOS tube, a first buffer, a second buffer and a third buffer which are mutually connected in series, an input end of the lvs_lh unit is externally connected with an SDA terminal through a first inverter, an output end of the lvs_lh unit is connected with a gate of the zeroth MOS tube, an input end of the first buffer is externally connected with an SDA terminal, an output end of the first buffer is connected with an input end of the second buffer, and an output end of the third buffer is externally connected with an SDA terminal.
As shown in fig. 3, in this embodiment, further, the first buffer includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube, the gate of the eighth MOS tube and the gate of the second MOS tube are all connected to the input terminal of the lvs_lh unit, the drain of the eighth MOS tube is connected to the source of the second MOS tube, the drain of the eighth MOS tube is connected to the source of the sixth MOS tube, the gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, the drain of the second MOS tube is connected to the drain of the third MOS tube and is connected to the gate of the seventh MOS tube, the source of the first MOS tube is connected to the source of the seventh MOS tube, the gate of the first MOS tube is connected to the gate of the third MOS tube, the source of the eighth MOS tube, the drain of the seventh MOS tube, the source of the fifth MOS tube is connected to the drain of the fifth MOS tube, the gate of the fifth MOS tube is connected to the drain of the fourth MOS tube, and the drain of the fifth MOS tube is connected to the drain of the fifth MOS tube.
In this embodiment, further, the first MOS transistor, the third MOS transistor, the fourth MOS transistor, and the seventh MOS transistor are all N-type MOS transistors.
In this embodiment, further, the second MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are all P-type MOS transistors.
As shown in fig. 4, in this embodiment, the lvs_lh unit further includes a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, a second inverter, and a third inverter, the gate of the tenth MOS transistor is connected to the drain of the eleventh MOS transistor, the drain of the tenth MOS transistor is connected to the drain of the thirteenth MOS transistor, the drain of the eleventh MOS transistor is connected to the drain of the twelfth MOS transistor, the source of the twelfth MOS transistor is connected to the drain of the sixteenth MOS transistor, the gate of the sixteenth MOS transistor is connected to the gate of the seventeenth MOS transistor, the gate of the seventeenth MOS transistor is connected to the output terminal of the second inverter, the input terminal of the second inverter is connected to the output terminal of the third inverter, the input terminal of the third inverter is used as the input terminal of the lvs_lh unit, the gate of the thirteenth MOS transistor is connected to the drain of the thirteenth MOS transistor, the drain of the fifteenth MOS transistor is connected to the drain of the fifteenth MOS transistor, the drain of the seventeenth MOS transistor is connected to the drain of the seventeenth MOS transistor, and the drain of the seventeenth MOS transistor is connected to the drain of the seventeenth MOS transistor.
In this embodiment, further, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, and the sixteenth MOS transistor are set as N-type MOS transistors.
In this embodiment, further, the tenth MOS transistor, the eleventh MOS transistor, the fifteenth MOS transistor, and the seventeenth MOS transistor are set as P-type MOS transistors.
In hardware, the I2C bus only needs one data line and one clock line, the bus interface is integrated in the chip, a special interface circuit is not needed, and a filter of the on-chip interface circuit can filter burrs on bus data. Therefore, the I2C bus simplifies the PCB wiring of the hardware circuit, reduces the system cost and improves the system reliability. Because the I2C chip has no connection wire with the system except the two wires and a small number of interrupt wires, the common IC for users can be easily standardized and modularized, and is convenient for recycling.
According to the utility model, the SDA terminal of the IO interface unit is grounded through the zeroth resistor, the SDAI terminal of the IO interface unit is grounded through the first resistor, the IO interface unit comprises the LVS_LH unit, the zeroth MOS tube, the first buffer, the second buffer and the third buffer which are mutually connected in series, the SDAO terminal is externally connected to the input end of the LVS_LH unit through the first inverter, the output end of the LVS_LH unit is connected with the grid electrode of the zeroth MOS tube, the SDA terminal is externally connected to the input end of the first buffer, the output end of the first buffer is connected with the input end of the second buffer, the output end of the second buffer is connected with the input end of the third buffer, the SDAI terminal is externally connected to the output end of the third buffer, and the I2C signal testing process is realized through the mutual matching between the LVS_LH unit and the plurality of voltage sources, the circuit structure is simple, and the signal transmission process is more convenient and accurate.
The foregoing describes the embodiments of the present utility model in detail, but the description is only a preferred embodiment of the present utility model and should not be construed as limiting the scope of the utility model. All equivalent changes and modifications within the scope of the present utility model are intended to be covered by this patent.
Claims (7)
1. The I2C test control circuit is characterized by comprising an IO interface unit and a plurality of voltage sources, wherein an SDA terminal of the IO interface unit is grounded through a zeroth resistor, an SDAI terminal of the IO interface unit is grounded through a first resistor, the IO interface unit comprises an LVS_LH unit, a zeroth MOS tube, a first buffer, a second buffer and a third buffer which are connected in series with each other, an SDAO terminal is externally connected to an input end of the LVS_LH unit through a first inverter, an output end of the LVS_LH unit is connected with a grid electrode of a zeroth MOS tube, an SDA terminal is externally connected to an input end of the first buffer, an output end of the first buffer is connected with an input end of the second buffer, an output end of the second buffer is connected with an input end of the third buffer, and an SDAI terminal is externally connected to an output end of the third buffer.
2. The I2C test control circuit of claim 1, wherein the first buffer comprises a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube and an eighth MOS tube, wherein the gate of the eighth MOS tube and the gate of the second MOS tube are all connected to the input terminal of the lvs_lh unit, the drain of the eighth MOS tube is connected to the source of the second MOS tube, the drain of the eighth MOS tube is connected to the source of the sixth MOS tube, the gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, the drain of the second MOS tube is connected to the drain of the third MOS tube and is connected to the gate of the seventh MOS tube, the source of the third MOS tube is connected to the drain of the first MOS tube, the drain of the first MOS tube is connected to the source of the seventh MOS tube, the gate of the eighth MOS tube is connected to the drain of the seventh MOS tube, the drain of the fifth MOS tube is connected to the drain of the fifth MOS tube, the drain of the fifth MOS tube is connected to the drain of the seventh MOS tube, and the drain of the fifth MOS tube is connected to the drain of the fifth MOS tube.
3. The I2C test control circuit of claim 2, wherein the first MOS transistor, the third MOS transistor, the fourth MOS transistor, and the seventh MOS transistor are all N-type MOS transistors.
4. The I2C test control circuit of claim 2, wherein the second MOS transistor, the fifth MOS transistor, the sixth MOS transistor, and the eighth MOS transistor are all P-type MOS transistors.
5. The I2C test control circuit of claim 1, wherein the lvs_lh unit comprises a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, a second inverter, and a third inverter, wherein a gate of the tenth MOS transistor is connected to a drain of the eleventh MOS transistor, a drain of the tenth MOS transistor is connected to a drain of the thirteenth MOS transistor, a gate of the eleventh MOS transistor is connected to a drain of the tenth MOS transistor, a source of the twelfth MOS transistor is connected to a drain of the sixteenth MOS transistor, a gate of the sixteenth MOS transistor is connected to a gate of the seventeenth MOS transistor, a gate of the seventeenth MOS transistor is externally connected to a prosa terminal, a gate of the twelfth MOS transistor is connected to an output of the second inverter, an input of the second inverter is connected to an output of the eleventh inverter, an input of the third inverter is connected to an output of the drain of the thirteenth inverter, and an input of the drain of the thirteenth MOS transistor is connected to a drain of the thirteenth MOS transistor, a drain of the seventeenth MOS transistor is connected to a drain of the seventeenth MOS transistor.
6. The I2C test control circuit of claim 5, wherein the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, and the sixteenth MOS transistor are N-type MOS transistors.
7. The I2C test control circuit of claim 5, wherein the tenth MOS transistor, the eleventh MOS transistor, the fifteenth MOS transistor, and the seventeenth MOS transistor are P-type MOS transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223002498.4U CN219162686U (en) | 2022-11-08 | 2022-11-08 | I2C test control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223002498.4U CN219162686U (en) | 2022-11-08 | 2022-11-08 | I2C test control circuit |
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| Publication Number | Publication Date |
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| CN219162686U true CN219162686U (en) | 2023-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223002498.4U Active CN219162686U (en) | 2022-11-08 | 2022-11-08 | I2C test control circuit |
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| CN (1) | CN219162686U (en) |
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