CN214474979U - I2C communication circuit and device - Google Patents
I2C communication circuit and device Download PDFInfo
- Publication number
- CN214474979U CN214474979U CN202120718930.6U CN202120718930U CN214474979U CN 214474979 U CN214474979 U CN 214474979U CN 202120718930 U CN202120718930 U CN 202120718930U CN 214474979 U CN214474979 U CN 214474979U
- Authority
- CN
- China
- Prior art keywords
- resistor
- interface module
- mos transistor
- control module
- mos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000126 substance Substances 0.000 claims description 21
- 230000015654 memory Effects 0.000 claims description 6
- 238000006243 chemical reaction Methods 0.000 abstract description 10
- 230000005540 biological transmission Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Landscapes
- Logic Circuits (AREA)
Abstract
The utility model belongs to the technical field of electronic circuit, a I2C communication circuit and device is disclosed. The circuit comprises a main control module, a first I2C interface module and a second I2C interface module; when receiving a high-level enable signal output by the master control module, the first I2C interface module conducts an I2C communication channel between the master control module and the first slave device; and the second I2C interface module is configured to, when receiving the high-level enable signal output by the master control module, turn on the I2C communication channel between the master control module and the second slave device. The utility model discloses well host system disposes above-mentioned interface module, host system's control pin draws high transmission high level enable signal to the interface module who corresponds, enables the passageway of first I2C interface module or second I2C interface module, realizes the low level communication during the low level, and all equipment keep the high level during the high level, and master-slave equipment sends and receives high level signal, need not the voltage conversion chip and realizes communication.
Description
Technical Field
The utility model relates to an electronic circuit technical field especially relates to a I2C communication circuit and device.
Background
At present, referring to fig. 1, the scheme requires configuring 2 eeprom (24C 02(1) and 24C02(2) through a set of I2C by using a master chip (hi3531av100), so that the video source 1 and the video source 2 output the video content required by the master chip (hi3531av 100).
In the application in fig. 1, there are also problems to be solved: in the video industry, the I2C address of a video source reading display device is fixed, and the I2C protocol standard does not allow a bus to mount I2C slave devices with the same address at the same time; if the I2C channel switching dedicated chip and the voltage conversion chip are used, the circuit is complicated and the cost is high.
The above is only for the purpose of assisting understanding of the technical solutions of the present invention, and does not represent an admission that the above is the prior art.
SUMMERY OF THE UTILITY MODEL
The utility model discloses a main aim at provides a I2C communication circuit and device, aims at solving current when not allowing the bus to mount the same I2C slave unit of address simultaneously, uses I2C voltage conversion chip to cause the circuit complicated and with high costs technical problem.
To achieve the above object, the present invention provides an I2C communication circuit, wherein the I2C communication circuit includes a main control module, a first I2C interface module and a second I2C interface module; the master control module is respectively connected with the first I2C interface module and the second I2C interface module, and the first I2C interface module is connected with the second I2C interface module; the first I2C interface module is connected with a first slave device, and the second I2C interface module is connected with a second slave device; wherein the content of the first and second substances,
the first I2C interface module is configured to, when receiving a high-level enable signal output by the master control module, turn on an I2C communication channel between the master control module and the first slave device;
the second I2C interface module is configured to, when receiving a high-level enable signal output by the master control module, turn on the I2C communication channel between the master control module and the second slave device.
Optionally, the main control module includes a main control chip, and an enable end of the main control chip is connected to the first I2C interface module and the second I2C interface module, respectively; wherein the content of the first and second substances,
the master control chip is configured to output a low-level enable signal to the first I2C interface module and the second I2C interface module, respectively, so that the I2C communication channels between the master control module and the first slave device and between the master control module and the second slave device are closed.
Optionally, the first I2C interface module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor; wherein the content of the first and second substances,
the grid electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected with the enabling end of the main control chip;
the drain electrode of the first MOS tube and the drain electrode of the second MOS tube are connected with a first end of the first resistor, and a second end of the first resistor is connected with a first power supply; the drain electrode of the third MOS tube and the drain electrode of the fourth MOS tube are connected with the first end of the second resistor, and the second end of the second resistor is connected with a first power supply;
the source electrode of the second MOS tube and the source electrode of the fourth MOS tube are respectively connected with the second I2C interface module, the source electrode of the first MOS tube is connected with the first end of the third resistor, the second end of the third resistor is connected with the first power supply, the source electrode of the third MOS tube is connected with the first end of the fourth resistor, and the second end of the fourth resistor is connected with the first power supply.
Optionally, the first I2C interface module further includes a fifth resistor; wherein the content of the first and second substances,
the first end of the fifth resistor is connected with the enabling end of the main control module, and the second end of the fifth resistor is connected with the second power supply.
Optionally, the first power supply is 5V, and the second power supply is 1.8V.
Optionally, the second I2C interface module includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor; wherein the content of the first and second substances,
the grid electrodes of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are connected with the enabling end of the main control chip;
the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are connected with the first end of the sixth resistor, and the second end of the sixth resistor is connected with a third power supply; the drain electrode of the seventh MOS tube and the drain electrode of the eighth MOS tube are connected with the first end of the seventh resistor, and the second end of the seventh resistor is connected with a third power supply;
a source electrode of the fifth MOS transistor and a source electrode of the seventh MOS transistor are respectively connected to the first I2C interface module, the source electrode of the fifth MOS transistor is connected to a first end of the eighth resistor, a second end of the eighth resistor is connected to a second power supply, the source electrode of the seventh MOS transistor is connected to a first end of the ninth resistor, and a second end of the ninth resistor is connected to the second power supply;
the source electrode of the sixth MOS tube is connected with the first end of the tenth resistor, the second end of the tenth resistor is connected with the third power supply, the source electrode of the eighth MOS tube is connected with the first end of the eleventh resistor, and the second end of the eleventh resistor is connected with the third power supply.
Optionally, the second I2C interface module further includes a twelfth resistor; wherein the content of the first and second substances,
and the first end of the twelfth resistor is connected with the enabling end of the main control module, and the second end of the twelfth resistor is connected with a second power supply.
Optionally, the third power supply is 3.3V, and the second power supply is 1.8V.
In addition, in order to achieve the above object, the present invention further provides an I2C communication device, wherein the I2C communication device includes the I2C communication circuit as described above.
Optionally, the I2C communication device further comprises one or more read only memories and one or more bus slave interfaces; wherein the content of the first and second substances,
the read-only memory is connected with the I2C communication circuit and the bus slave interface, the I2C communication circuit is connected with a master device through an I2C master bus, and the bus slave interface is connected with a slave device through an I2C slave bus.
The utility model provides an I2C communication circuit, I2C communication circuit includes main control module, first I2C interface module and second I2C interface module; the master control module is respectively connected with the first I2C interface module and the second I2C interface module, and the first I2C interface module is connected with the second I2C interface module; the first I2C interface module is connected with a first slave device, and the second I2C interface module is connected with a second slave device; the first I2C interface module is configured to, when receiving a high-level enable signal output by the master control module, turn on an I2C communication channel between the master control module and the first slave device; the second I2C interface module is configured to, when receiving a high-level enable signal output by the master control module, turn on the I2C communication channel between the master control module and the second slave device. The utility model discloses in, when master control module need dispose first I2C interface module or second I2C interface module, master control module's control pin draws high and sends high level enable signal to the interface module who corresponds, and the passageway of the first I2C interface module of messenger's ability or second I2C interface module accomplishes a low level communication from master to slave. During the high level period, all the devices are kept at the high level, the master device and the slave device can normally send and receive high level signals, I2C communication is realized without a voltage conversion chip, and the technical problems of complex circuit and high cost caused by the use of an I2C voltage conversion chip when the bus is not allowed to mount I2C slave devices with the same address at the same time are solved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a diagram illustrating an output video display content of a conventional video source;
fig. 2 is a functional block diagram of an embodiment of the communication circuit of the present invention I2C;
fig. 3 is a schematic circuit diagram of an embodiment of the communication circuit of the present invention I2C;
fig. 4 is a schematic circuit structure diagram of a pull-up resistor of a main control module according to an embodiment of the I2C communication circuit of the present invention.
The reference numbers illustrate:
the objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
The utility model provides a I2C communication circuit.
Referring to fig. 2, in the embodiment of the present invention, the I2C communication circuit includes a main control module 100, a first I2C interface module 200, and a second I2C interface module 300; the master control module 100 is respectively connected to the first I2C interface module 200 and the second I2C interface module 300, and the first I2C interface module 200 is connected to the second I2C interface module 300; the first I2C interface module 200 is connected with a first slave device, and the second I2C interface module 300 is connected with a second slave device; wherein the content of the first and second substances,
the first I2C interface module 200 is configured to, when receiving a high-level enable signal output by the master module 100, turn on the I2C communication channel between the master module 100 and the first slave device. In this embodiment, referring to fig. 1, fig. 1 is a schematic diagram of a conventional video source outputting video display content, in fig. 1, 2 eeprom (24C 02(1) and 24C02(2) are configured by a set of I2C using a master control chip (hi3531av100), so that the video source 1 and the video source 2 output the video content required by the master control chip (hi3531av100), but in the above manner, in the video industry, the I2C address of the video source reading display device is fixed (0xa0), and the I2C protocol standard does not allow a bus to simultaneously mount I2C slave devices with the same address; the chip special for switching the I2C channel and the voltage conversion chip are high in cost and complex in circuit.
It should be noted that, in order to overcome the above problems, this embodiment provides an I2C communication circuit, where the I2C communication circuit includes a main control module 100, a first I2C interface module 200, and a second I2C interface module 300, for example, when the main control module 100 needs to configure the eeprom 24C02(1), at this time, a control pin of the main control module 100 is set to an open-drain mode, a high-level enable signal output by the main control module 100 is sent to the first I2C interface module, and an enable control pin in the first I2C interface module is pulled up, so that the channel of the eeprom 24C02(1) is enabled.
The second I2C interface module 300 is configured to, when receiving a high-level enable signal output by the master module 100, turn on the I2C communication channel between the master module 100 and the second slave device. In this embodiment, the I2C communication circuit may include a main control module 100 and a second I2C interface module 300, for example, when the main control module 100 needs to configure the eeprom 24C02(2), at this time, a control pin of the main control module 100 is set to an open-drain mode, a high-level enable signal output by the main control module 100 is sent to the second I2C interface module, and an enable control pin in the second I2C interface module is pulled high, so that the channel of the eeprom 24C02(2) is enabled.
It is easy to understand that the control pin of the main control module 100 can be set to an open-drain mode, the TTL circuit has an OC gate with an open collector, the MOS transistor also has an OD gate with an open drain corresponding to the collector, and its output is called an open-drain output.
The present embodiment proposes an I2C communication circuit, the I2C communication circuit includes a main control module 100, a first I2C interface module 200 and a second I2C interface module 300; the master control module 100 is respectively connected to the first I2C interface module 200 and the second I2C interface module 300, and the first I2C interface module 200 is connected to the second I2C interface module 300; the first I2C interface module 200 is connected with a first slave device, and the second I2C interface module 300 is connected with a second slave device; the first I2C interface module 200 is configured to, when receiving a high-level enable signal output by the master control module 100, turn on an I2C communication channel between the master control module 100 and the first slave device; the second I2C interface module 300 is configured to, when receiving a high-level enable signal output by the master module 100, turn on the I2C communication channel between the master module 100 and the second slave device. In this embodiment, when the main control module needs to configure the first I2C interface module or the second I2C interface module, the control pin of the main control module is pulled high to send a high level enable signal to the corresponding interface module, so that the channel of the first I2C interface module or the second I2C interface module is enabled, and a low level communication from the master device to the slave device is completed. During the high level period, all the devices are kept at the high level, the master device and the slave device can normally send and receive high level signals, I2C communication is realized without a voltage conversion chip, and the technical problems of complex circuit and high cost caused by the use of an I2C voltage conversion chip when the bus is not allowed to mount I2C slave devices with the same address at the same time are solved.
Further, the main control module 100 includes a main control chip, and an enable end EN of the main control chip is connected to the first I2C interface module 200 and the second I2C interface module 300 respectively; wherein the content of the first and second substances,
the master control chip is configured to output a low-level enable signal to the first I2C interface module 200 and the second I2C interface module 300, respectively, so that the I2C communication channels between the master control module 100 and the first slave device and the second slave device are closed.
It should be noted that the main control module 100 may include a main control chip, when the main control chip is idle, neither of the 2 eeprom devices 24C02(1) and 24C02(2) needs to be configured, and at this time, the main control chip pulls down the enable control pin connected to the first I2C interface module 200 and the enable control pin connected to the second I2C interface module 300, so that the gate voltages of the MOS transistors in the first I2C interface module 200 and the second I2C interface module 300 are 0V, because of the V of the MOS transistorsgsBelow the MOS transistor turn-on voltage, the 2 eeprom channels 24C02(1) and 24C02(2) are turned off.
Further, referring to fig. 3, the first I2C interface module 200 includes a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; wherein the content of the first and second substances,
the gates of the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3 and the fourth MOS transistor Q4 are connected with an enable end EN of the main control chip;
the drain electrode of the first MOS transistor Q1 and the drain electrode of the second MOS transistor Q2 are connected with a first end of the first resistor R1, and a second end of the first resistor R1 is connected with a first power supply VCC _ 5V; the drain electrode of the third MOS transistor Q3 and the drain electrode of the fourth MOS transistor Q4 are connected to a first end of the second resistor R2, and a second end of the second resistor R2 is connected to a first power source VCC _ 5V;
the source of second MOS pipe Q2 with the source of fourth MOS pipe Q4 respectively with second I2C interface module 300 connects, the source of first MOS pipe Q1 with the first end of third resistance R3 is connected, the second end and the first power VCC _5V of third resistance R3 are connected, the source of third MOS pipe Q3 with the first end of fourth resistance R4 is connected, the second end and the first power VCC _5V of fourth resistance R4 are connected.
It is easy to understand that the first I2C interface module 200 may include a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, where when the main control module 100 needs to configure the eeprom 24C02(1), at this time, the control pin of the main control module 100 is set to the open-drain mode, the high-level enable signal output by the main control module 100 is sent to the first I2C interface module 200, and the enable control pin in the first I2C interface module 200 is pulled high, so that the channel of the eeprom 24C02 (351) is enabled.
Specifically, when the master device initiates the I2C signal, during the low level (0V), the gate voltage and the source voltage V of the second MOS transistor Q2 and the fourth MOS transistor Q4 are appliedgsIs 1.8V, is greater than the MOS transistor turn-on voltage, at this time, the second MOS transistor Q2 and the fourth MOS transistor Q4 are turned on, the drains of the second MOS transistor Q2 and the fourth MOS transistor Q4 are at low level, and meanwhile, because the MOS transistors have parasitic diodes, the first MOS transistor Q1 and the third MOS transistor Q3 have parasitic diodesThe source will be pulled low, thus completing a low communication from the master to the slave 24C02 (1). When the slave device initiates an acknowledge signal, the relevant I2C communication principle is as described above. During the high level period, all the devices are kept at the high level on the respective pull-up level standards (such as 1.8V, 3.3V and 5V), and at this time, the master device and the slave device can normally send and receive high level signals, so that the purpose of not needing a level conversion chip is achieved.
Further, referring to fig. 4, the first I2C interface module 200 further includes a fifth resistor R5; wherein the content of the first and second substances,
the first end of the fifth resistor R5 is connected to the enable end EN of the main control module 100, and the second end of the fifth resistor R5 is connected to the second power VCC _1V 8.
It should be noted that the first end of the fifth resistor R5 is connected to the enable end EN of the main control module 100, and the first end of the fifth resistor R5 is further connected to the gates of the first MOS transistor Q1, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4. The first I2C interface module 200 and the corresponding first slave device may use a 5V level standard, and the master control module 100 may use a 1.8V level standard, which is not limited in this embodiment. The first I2C interface module 200 may further include a fifth resistor R5, a first end of the fifth resistor R5 is connected to an enable end of the main control module 100, a second end of the fifth resistor R5 is connected to a second power source VCC _1V8, the second power source VCC _1V8 is 1.8V, and meets a level standard that the main control module 100 uses 1.8V.
Further, with continued reference to fig. 3, the first power VCC _5V is 5V, and the second power VCC _1V8 is 1.8V.
It is easily understood that, referring to fig. 1, fig. 1 is a schematic diagram of a conventional video source outputting video display content, in fig. 1, 2 eeprom, i.e., 24C02(1) and 24C02(2), are configured through a set of I2C by using a main control chip (hi3531av100), so that the video source 1 and the video source 2 output video content required by the main control chip (hi3531av100), but in the above manner, in the video industry, if the voltage used by the video source 1 is 5V, the voltage used by the video source 2 is 3.3V, and the voltage used by the main control chip (hi3531av100) is 1.8V, and the voltages of the three are different, there is a problem that normal communication cannot be performed.
It should be noted that, in order to overcome the above problem, this embodiment provides an I2C communication circuit, where the I2C communication circuit includes a master control module 100, a first I2C interface module 200, and a second I2C interface module 300, the first I2C interface module 200 and a corresponding first slave device can use a 5V level standard, and the master control module 100 can use a 1.8V level standard, and then the first power VCC _5V can be set to be 5V, the second power VCC _1V8 can be set to be 1.8V, and specific values of the first power VCC _5V and the second power VCC _1V8 can be set according to practical situations, which is not limited in this embodiment.
Further, with continued reference to fig. 3, the second I2C interface module 300 includes a fifth MOS transistor Q5, a sixth MOS transistor Q6, a seventh MOS transistor Q7, an eighth MOS transistor Q8, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11; wherein the content of the first and second substances,
the gates of the fifth MOS transistor Q5, the sixth MOS transistor Q6, the seventh MOS transistor Q7 and the eighth MOS transistor Q8 are connected with an enable end EN of the main control chip;
the drain electrode of the fifth MOS transistor Q5 and the drain electrode of the sixth MOS transistor Q6 are connected to a first end of the sixth resistor R6, and a second end of the sixth resistor R6 is connected to a third power source VCC _3V 3; the drain electrode of the seventh MOS transistor Q7 and the drain electrode of the eighth MOS transistor Q8 are connected to a first end of the seventh resistor R7, and a second end of the seventh resistor R7 is connected to a third power source VCC _3V 3;
a source of the fifth MOS transistor Q5 and a source of the seventh MOS transistor Q7 are respectively connected to the first I2C interface module 200, a source of the fifth MOS transistor Q5 is connected to a first end of the eighth resistor R8, a second end of the eighth resistor R8 is connected to a second power VCC _1V8, a source of the seventh MOS transistor Q7 is connected to a first end of the ninth resistor R9, and a second end of the ninth resistor R9 is connected to a second power VCC _1V 8;
the source of sixth MOS pipe Q6 with the first end of tenth resistance R10 is connected, the second end and the third power VCC _3V3 of tenth resistance R10 are connected, the source of eighth MOS pipe Q8 with the first end of eleventh resistance R11 is connected, the second end and the third power VCC _3V3 of eleventh resistance R11 are connected.
It should be noted that the second I2C interface module 300 may include a fifth MOS transistor Q5, a sixth MOS transistor Q6, a seventh MOS transistor Q7, an eighth MOS transistor Q8, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11, where when the main control module 100 needs to configure the eeprom 24C02(2), at this time, the control pin of the main control module 100 is set to the open-drain mode, the high-level enable signal output by the main control module 100 is sent to the second I2C interface module 300, and the enable control pin in the second I2C interface module 300 is pulled up, so that the eeprom 24C02(2) channel can be provided.
Specifically, when the master device initiates the I2C signal, during the low level (0V), the gate voltage and the source voltage V of the fifth MOS transistor Q5 and the seventh MOS transistor Q7 are appliedgsThe voltage is 1.8V and is greater than the MOS transistor turn-on voltage, at this time, the fifth MOS transistor Q5 and the seventh MOS transistor Q7 are turned on, the drains of the fifth MOS transistor Q5 and the seventh MOS transistor Q7 are at a low level, and at the same time, due to the parasitic diodes existing in the MOS transistors, the sources of the sixth MOS transistor Q6 and the eighth MOS transistor Q8 are pulled low, so that low level communication from the master device to the slave device 24C02(2) is completed. When the slave device initiates an acknowledge signal, the relevant I2C communication principle is as described above. During the high level period, all the devices are kept at the high level on the respective pull-up level standards (such as 1.8V, 3.3V and 5V), and at this time, the master device and the slave device can normally send and receive high level signals, so that the purpose of not needing a level conversion chip is achieved.
Further, with continued reference to fig. 4, the second I2C interface module 300 further includes a twelfth resistor R12; wherein the content of the first and second substances,
a first end of the twelfth resistor R12 is connected to the enable end EN of the main control module 100, and a second end of the twelfth resistor R12 is connected to a second power VCC _1V 8.
It should be noted that a first end of the twelfth resistor R12 is connected to the enable end EN of the main control module 100, and a first end of the twelfth resistor R12 is further connected to gates of the fifth MOS transistor Q5, the sixth MOS transistor Q6, the seventh MOS transistor Q7, and the eighth MOS transistor Q8. The second I2C interface module 300 and the corresponding second slave device may use a level standard of 3.3V, and the master control module 100 may use a level standard of 1.8V, which is not limited in this embodiment. The second I2C interface module 300 may further include a twelfth resistor R12, a first end of the twelfth resistor R12 is connected to the enable end EN output in the main control module 100, another end of the twelfth resistor R12 is connected to a second power source VCC _1V8, the second power source VCC _1V8 is 1.8V, and meets the level standard that the main control module 100 uses 1.8V.
Further, with continued reference to fig. 3, the third power VCC _3V3 is 3.3V, and the second power VCC _1V8 is 1.8V.
It should be understood that, referring to fig. 1, in the video industry, if the voltage used by the video source 1 is 5V, the voltage used by the video source 2 is 3.3V, and the voltage used by the main control chip (hi3531av100) is 1.8V, the voltages of the three are different, and there is a problem that normal communication cannot be performed.
It should be noted that, in order to overcome the above problem, this embodiment provides an I2C communication circuit, where the I2C communication circuit includes a master control module 100, a first I2C interface module 200, and a second I2C interface module 300, the second I2C interface module 300 and a corresponding second slave device can use a level standard of 3.3V, and the master control module 100 can use a level standard of 1.8V, and then the third power VCC _3V3 can be set to 3.3V, the second power VCC _1V8 can be set to 1.8V, and specific values of the third power VCC _3V3 and the second power VCC _1V8 can be set according to practical situations, which this embodiment is not limited thereto.
To achieve the above object, the present invention further proposes an I2C communication device, wherein the I2C communication device comprises the I2C communication circuit as described above. The specific structure of the I2C communication circuit refers to the above embodiments, and since the I2C communication apparatus adopts all technical solutions of all the above embodiments, at least all beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.
Further, the I2C communication device also includes one or more read only memories and one or more bus slave interfaces; wherein the content of the first and second substances,
the read-only memory is connected with the I2C communication circuit and the bus slave interface, the I2C communication circuit is connected with a master device through an I2C master bus, and the bus slave interface is connected with a slave device through an I2C slave bus.
The above only is the preferred embodiment of the present invention, not so limiting the patent scope of the present invention, all under the concept of the present invention, the equivalent structure transformation made by the contents of the specification and the drawings is utilized, or the direct/indirect application is included in other related technical fields in the patent protection scope of the present invention.
Claims (10)
1. An I2C communication circuit, wherein the I2C communication circuit comprises a master control module, a first I2C interface module and a second I2C interface module; the master control module is respectively connected with the first I2C interface module and the second I2C interface module, and the first I2C interface module is connected with the second I2C interface module; the first I2C interface module is connected with a first slave device, and the second I2C interface module is connected with a second slave device; wherein the content of the first and second substances,
the first I2C interface module is configured to, when receiving a high-level enable signal output by the master control module, turn on an I2C communication channel between the master control module and the first slave device;
the second I2C interface module is configured to, when receiving a high-level enable signal output by the master control module, turn on the I2C communication channel between the master control module and the second slave device.
2. The I2C communication circuit of claim 1, wherein the master control module includes a master control chip having an enable terminal connected to the first I2C interface module and the second I2C interface module, respectively; wherein the content of the first and second substances,
the master control chip is configured to output a low-level enable signal to the first I2C interface module and the second I2C interface module, respectively, so that the I2C communication channels between the master control module and the first slave device and between the master control module and the second slave device are closed.
3. The I2C communication circuit of claim 2, wherein the first I2C interface module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor; wherein the content of the first and second substances,
the grid electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected with the enabling end of the main control chip;
the drain electrode of the first MOS tube and the drain electrode of the second MOS tube are connected with a first end of the first resistor, and a second end of the first resistor is connected with a first power supply; the drain electrode of the third MOS tube and the drain electrode of the fourth MOS tube are connected with the first end of the second resistor, and the second end of the second resistor is connected with a first power supply;
the source electrode of the second MOS tube and the source electrode of the fourth MOS tube are respectively connected with the second I2C interface module, the source electrode of the first MOS tube is connected with the first end of the third resistor, the second end of the third resistor is connected with the first power supply, the source electrode of the third MOS tube is connected with the first end of the fourth resistor, and the second end of the fourth resistor is connected with the first power supply.
4. The I2C communication circuit of claim 3, wherein the first I2C interface module further includes a fifth resistor; wherein the content of the first and second substances,
the first end of the fifth resistor is connected with the enabling end of the main control module, and the second end of the fifth resistor is connected with the second power supply.
5. The I2C communication circuit of claim 4, wherein the first power supply is 5V and the second power supply is 1.8V.
6. The I2C communication circuit of claim 2, wherein the second I2C interface module includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, and an eleventh resistor; wherein the content of the first and second substances,
the grid electrodes of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are connected with the enabling end of the main control chip;
the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube are connected with the first end of the sixth resistor, and the second end of the sixth resistor is connected with a third power supply; the drain electrode of the seventh MOS tube and the drain electrode of the eighth MOS tube are connected with the first end of the seventh resistor, and the second end of the seventh resistor is connected with a third power supply;
a source electrode of the fifth MOS transistor and a source electrode of the seventh MOS transistor are respectively connected to the first I2C interface module, the source electrode of the fifth MOS transistor is connected to a first end of the eighth resistor, a second end of the eighth resistor is connected to a second power supply, the source electrode of the seventh MOS transistor is connected to a first end of the ninth resistor, and a second end of the ninth resistor is connected to the second power supply;
the source electrode of the sixth MOS tube is connected with the first end of the tenth resistor, the second end of the tenth resistor is connected with the third power supply, the source electrode of the eighth MOS tube is connected with the first end of the eleventh resistor, and the second end of the eleventh resistor is connected with the third power supply.
7. The I2C communication circuit of claim 6, wherein the second I2C interface module further includes a twelfth resistor; wherein the content of the first and second substances,
and the first end of the twelfth resistor is connected with the enabling end of the main control module, and the second end of the twelfth resistor is connected with a second power supply.
8. The I2C communication circuit of claim 7, wherein the third power supply is 3.3V and the second power supply is 1.8V.
9. An I2C communication device, characterized in that the I2C communication device comprises the I2C communication circuit according to any one of claims 1-8.
10. The I2C communication apparatus of claim 9, wherein the I2C communication apparatus further comprises one or more read only memories and one or more bus slave interfaces; wherein the content of the first and second substances,
the read-only memory is connected with the I2C communication circuit and the bus slave interface, the I2C communication circuit is connected with a master device through an I2C master bus, and the bus slave interface is connected with a slave device through an I2C slave bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120718930.6U CN214474979U (en) | 2021-04-08 | 2021-04-08 | I2C communication circuit and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120718930.6U CN214474979U (en) | 2021-04-08 | 2021-04-08 | I2C communication circuit and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214474979U true CN214474979U (en) | 2021-10-22 |
Family
ID=78177990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120718930.6U Expired - Fee Related CN214474979U (en) | 2021-04-08 | 2021-04-08 | I2C communication circuit and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214474979U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117201222A (en) * | 2023-08-16 | 2023-12-08 | 天津瑞发科半导体技术有限公司 | I2C interface system, data writing method and data reading method |
-
2021
- 2021-04-08 CN CN202120718930.6U patent/CN214474979U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117201222A (en) * | 2023-08-16 | 2023-12-08 | 天津瑞发科半导体技术有限公司 | I2C interface system, data writing method and data reading method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7849244B2 (en) | Apparatus for resolving conflicts happened between two I2C slave devices with the same addressed address in computer system | |
| CN109509422B (en) | Display panel drive circuit and display device | |
| US5559996A (en) | Level converter including wave-shaping circuit and emulator microcomputer incorporating the level converter | |
| CN101849358A (en) | Semiconductor device and display device | |
| US7755412B2 (en) | Bi-directional level shifted interrupt control | |
| CN105931595A (en) | Shift register unit, driving method, grid drive circuit, and display device | |
| CN101539900A (en) | Device for solving conflict generated between two I<2>C slave devices with same addressing address | |
| WO2021196958A1 (en) | Capacitive isolation circuit, interface module, chip, and system | |
| CN214474979U (en) | I2C communication circuit and device | |
| US10748470B2 (en) | Level shifter and projector | |
| CN117280406A (en) | Display hot plug detection circuit, working method, integrated circuit and electronic equipment | |
| US10673436B1 (en) | Failsafe device | |
| CN218162431U (en) | Bidirectional level conversion circuit | |
| CN216817392U (en) | Docking station equipment access detection circuit and equipment | |
| CN202602615U (en) | Control circuit of rail-to-rail enable signals and electric level conversion circuit | |
| CN100359502C (en) | Mixed logic level bidirectional bus converter and connection method thereof | |
| CN103199845B (en) | Bidirectional buffer based on open drain bus | |
| CN212256299U (en) | HDMI interface circuit and equipment compatible with serial debugging | |
| CN113900983A (en) | Signal transmission circuit based on serial bus and electronic equipment | |
| CN209949101U (en) | 485 communication is from receiving and dispatching circuit | |
| CN113342726A (en) | I2C bus system, chip with applied voltage working mode and method | |
| CN219162686U (en) | I2C test control circuit | |
| CN103312313A (en) | rail to rail enable signal and level conversion circuit | |
| WO1981001781A1 (en) | Buffer circuitry | |
| CN216057310U (en) | Interface card power supply circuit and set-top box |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20211022 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |