CN219123241U

CN219123241U - Low-voltage low-leakage diode

Info

Publication number: CN219123241U
Application number: CN202223362482.4U
Authority: CN
Inventors: 王立伟; 陈宇
Original assignee: Chaoyang Microelectronics Technology Co ltd
Current assignee: Chaoyang Microelectronics Technology Co ltd
Priority date: 2022-12-15
Filing date: 2022-12-15
Publication date: 2023-06-02
Anticipated expiration: 2032-12-15

Abstract

The utility model discloses a low-voltage low-leakage diode, which comprises a silicon wafer, wherein the upper part of the silicon wafer is an active area, the thickness of the silicon wafer is 2-3 microns, polysilicon is arranged on the active area, a Ti/Ni/Ag metal film is arranged on the polysilicon, the Ti/Ni/Ag metal film is a top surface electrode of the diode, the lower part of the polysilicon is a P-type silicon wafer, the thickness of the polysilicon is 300 microns, and the bottom surface of the P-type silicon wafer is provided with a Ti/Ni/Ag metal film which is a bottom surface electrode of the diode; an annular isolation groove is etched on the periphery of the upper part of the silicon wafer, and photoresist glass powder is filled in the isolation groove. The beneficial effects of the utility model are as follows: the low-voltage low-leakage diode has the advantages of low voltage, low leakage current, high reliability and the like, and can be widely applied to various environment and quality grade requirements.

Description

Low-voltage low-leakage diode

Technical Field

The utility model relates to the field of electronic elements, in particular to a small-capacitance guide rectifying tube.

Background

A semiconductor refers to a material with conductivity between that of a conductor and an insulator at normal temperature. Semiconductors have wide application in various electronic instruments in life.

Currently, in the field of electronic component chips, most low voltage diodes generally exhibit a situation of large leakage. The common low-voltage diode chip is manufactured by adding a passivation layer to achieve the purpose of reducing leakage current, but the effect of reducing the leakage current is not obvious. But in many particular fields it is desirable to use low voltage low leakage diodes that further reduce leakage current.

Disclosure of Invention

The utility model aims to solve the technical problems and designs a low-voltage low-leakage diode.

The technical scheme adopted for solving the technical problems is as follows:

the low-voltage low-leakage diode comprises a silicon wafer, wherein the upper part of the silicon wafer is an active region, the thickness of the silicon wafer is 2-3 microns, polysilicon is arranged on the active region, a first Ti/Ni/Ag metal film is arranged on the polysilicon, and the first Ti/Ni/Ag metal film is one electrode of the diode; the lower part is a P-type silicon wafer with the thickness of 300-350 microns, the bottom surface of the P-type silicon wafer is provided with a second Ti/Ni/Ag metal film, and the second Ti/Ni/Ag metal film is the other electrode of the diode; an annular isolation groove is etched on the periphery of the upper part of the silicon wafer, and photoresist glass powder is filled in the isolation groove.

The low voltage low leakage diode has the deposition thickness of polysilicon on the upper part of the silicon wafer of

The low voltage low leakage diode has a top electrode formed by a first Ti/Ni/Ag metal film having thickness of

The low voltage low leakage diode has a bottom electrode formed by a second Ti/Ni/Ag metal film having thickness of

The annular isolation groove is a groove with the depth of 20 microns, which is formed by ICP plasma etching.

The beneficial effects of the utility model are as follows: the low-voltage low-leakage diode has the advantages of low voltage, low leakage current, high reliability and the like, and can be widely applied to various environment and quality grade requirements.

Drawings

FIG. 1 is a schematic diagram of a low voltage low leakage diode according to the present utility model in a longitudinal cross-sectional configuration;

fig. 2 is a schematic diagram of the upper surface structure of the low-voltage low-leakage diode according to the present utility model.

Detailed Description

The utility model will be further described with reference to the drawings and examples.

As shown in fig. 1 and 2, the low-voltage low-leakage diode of the present utility model comprises a silicon wafer 1, wherein an active region 2 is arranged at the upper part of the silicon wafer 1, the thickness of the active region is 2-3 micrometers, polysilicon 3 is arranged on the active region 2, a first Ti/Ni/Ag metal film 4 is arranged on the polysilicon 3, and the first Ti/Ni/Ag metal film 4 is one electrode of the diode; the lower part is a P-type silicon wafer with the thickness of 300-350 microns, the bottom surface of the P-type silicon wafer is provided with a second Ti/Ni/Ag metal film 5, and the second Ti/Ni/Ag metal film 5 is the other electrode of the diode; an annular isolation groove 6 is etched on the periphery of the upper part of the silicon wafer, and photoresist glass powder 7 is filled in the isolation groove 6.

The deposition thickness of the polysilicon 3 at the upper part of the silicon wafer 1 is that

The low voltage low leakage diode has a top electrode formed by a first Ti/Ni/Ag metal film 4, the first Ti/Ni/Ag metal film 4 having a thickness of

The low voltage and low leakage diode has a bottom electrode formed by a second Ti/Ni/Ag metal film 5, the second Ti/Ni/Ag metal film 5 having a thickness of

The annular isolation groove 6 is a groove with the depth of 20 microns formed after ICP plasma etching.

The low-voltage low-leakage diode is manufactured by the following implementation steps:

step one: the silicon wafer is cleaned: cleaning the silicon wafer by adopting a chemical reaction and melting and washing method to obtain the silicon wafer with the high-cleanliness surface; the chemical reaction and melting and washing method comprises the following steps: firstly, adopting sulfuric acid and hydrogen peroxide mixed solution to melt and wash for 10 minutes, cleaning with DI water for 10 minutes, and then using 1:20, washing with DI water for 10 min, finally, washing with mixed solution of ammonia water and hydrogen peroxide for 10 min, washing with DI water for 10 min, and spin-drying for 10 min.

Step two: the deposited polysilicon: performing polysilicon deposition on the front surface of the silicon wafer treated in the first step by adopting a POLY process; the POLY process is as follows: the gas adopted is silane, ventilation is carried out for 20 minutes at 650 ℃, then the temperature is raised to 780 ℃, the deposition is carried out for 1 hour, and the thickness of the formed polysilicon is

Step three: the active region implant: ion implantation is carried out in the front area of the silicon wafer treated in the second step, so that the monocrystalline material obtains prescribed doping ions in a limited area to form an active area; the ion implantation is: PH3 was used as the implantation source with an implantation energy of 120Kev and an implantation dose of 2E16.

Step four: the redistribution: and (3) in the dry oxygen atmosphere with the temperature of 1150 ℃, the oxygen flow is 8L/min, and the time is 30 minutes, so that the doped ions injected into the active region are diffused and distributed into the silicon wafer, and finally the active region with the junction depth of 2-3 microns is formed.

Step five: the isolation groove photoetching comprises the following steps: coating a layer of photoresist on the front surface of a silicon wafer by adopting a spin coating method, and etching a spacer ring window on a photoresist film by adopting a method of localized sensitization and mask corrosion on the front surface of the silicon wafer by using a spacer groove photoetching plate; the spin coating method means: the photoresist is selected from BN308-450, the rotating speed is 2000 rpm, and the photoresist coating operation is carried out for 20 seconds.

Step six: and etching the isolation groove: and fifthly, etching the isolation groove on the front surface of the silicon wafer by adopting an ICP plasma etching method to form the isolation groove with the depth of 20 micrometers.

Step seven: the photoresistance glass powder is sintered and melted: after the first to sixth steps are completed, the photoresistance glass powder is sintered and melted, and the isolation groove is filled with glass powder after the sintered and melted; the burning-in is performed at the presintering temperature of 570 ℃, the oxygen flow is 8L/min, and the presintering time is 15 minutes; then, at a burning temperature of 740 ℃, the oxygen flow rate of 8L/min, and the continuous burning time of 15 minutes.

Step eight: the secondary photolithography: and seventhly, carrying out secondary photoetching, coating a layer of photoresist on the front surface of the silicon wafer by adopting a spin coating method, selecting a secondary photoetching plate, and etching an electrode window on the photoresist by adopting a method of localized photosensitive and masking corrosion.

Step nine: and (3) metalizing the front surface of the silicon wafer: after the eighth step, forming a metal film on the front surface of the silicon wafer by adopting an evaporation process; the method for manufacturing the low-voltage low-leakage diode comprises the following steps: bombarding Ti/Ni/Ag material in vacuum environment with electron beam to produce Ti/Ni/Ag metal vapor to splash onto the surface of silicon chip with Ti/Ni/Ag metal film thickness of respectively

Step ten: the back-etching metal: and step nine, coating a layer of photoresist on the front surface of the silicon wafer by adopting a spin coating method, and etching an electrode on the photoresist film by adopting a method of localized photosensitive and masking corrosion on the front surface of the silicon wafer by using an anti-etching metal photoetching plate.

Step eleven: and cleaning the back surface of the silicon wafer: after the step ten, the back of the silicon wafer is chemically cleaned, and 1:20 is soaked in hydrofluoric acid for 10 seconds, DI water is used for cleaning for 10 minutes, then acetone is used for cleaning for 10 minutes, DI water is used for cleaning for 10 minutes, then ethanol is used for cleaning for 10 minutes, and finally isopropanol is used for cleaning for 10 minutes, so that the silicon wafer with the back surface with high cleanliness is obtained.

Step twelve: and (3) metallization of the back surface of the silicon wafer: and step elevationly, forming a metal film on the bottom surface of the silicon wafer by adopting an evaporation process.

Step thirteen: the dicing: and step twelve, cutting the silicon wafer by adopting a diamond grinding wheel to obtain a finished chip.

The finished chip with the structure can lead the electric leakage of the diode with the voltage within 5V to reach the nA level, and the characteristic curve of the chip is excellent.

The present utility model is not limited to the above-described preferred embodiments, and any other products which are the same as or similar to the present utility model, which are obtained by any person in the light of the present utility model, fall within the scope of the present utility model.

Claims

1. A low voltage low leakage diode, characterized by: the low-voltage low-leakage diode comprises a silicon wafer (1), wherein an active region (2) is arranged at the upper part of the silicon wafer (1), the thickness of the active region is 2-3 microns, polycrystalline silicon (3) is arranged on the active region (2), a first Ti/Ni/Ag metal film (4) is arranged on the polycrystalline silicon (3), and the first Ti/Ni/Ag metal film (4) is one electrode of the diode; the lower part is a P-type silicon wafer with the thickness of 300-350 microns, the bottom surface of the P-type silicon wafer is provided with a second Ti/Ni/Ag metal film (5), and the second Ti/Ni/Ag metal film (5) is the other electrode of the diode; an annular isolation groove (6) is etched on the periphery of the upper part of the silicon wafer, and photoresist glass powder (7) is filled in the annular isolation groove (6).

2. A low voltage low leakage diode according to claim 1, wherein: the deposition thickness of the polysilicon (3) at the upper part of the silicon wafer (1) is

3. A low voltage low leakage diode according to claim 1, wherein: the first Ti/Ni/Ag metal film (4) forms a top electrode, and the thickness of the first Ti/Ni/Ag metal film (4) is respectively

4. A low voltage low leakage diode according to claim 1, wherein: the second Ti/Ni/Ag metal film (5) forms a bottom electrode, and the thickness of the second Ti/Ni/Ag metal film (5) is respectively

5. A low voltage low leakage diode according to claim 1, wherein: the annular isolation groove (6) is a groove with the depth of 20 microns formed after ICP plasma etching.