CN218451113U

CN218451113U - Display device

Info

Publication number: CN218451113U
Application number: CN202222286991.7U
Authority: CN
Inventors: 金仁玉; 李相宪; 金赞洙; 吴根灿; 李角锡; 李苏玧; 张智恩; 张昶顺
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2021-08-30
Filing date: 2022-08-30
Publication date: 2023-02-03
Anticipated expiration: 2032-08-30
Also published as: CN115734689A; US20230060722A1; EP4142452A2; KR20230033181A; EP4142452A3

Abstract

A display device is provided. The display device may include: a transistor substrate including a driving element and having a display region and a non-display region surrounding the display region; a bank layer on the non-display region of the transistor substrate and exposing an outer region of the non-display region of the transistor substrate opposite to the display region; an inorganic insulating layer covering an upper surface of the bank layer, a side surface of the bank layer, and an outer region of the transistor substrate; a low refractive layer on the inorganic insulating layer; and a first color filter layer on the non-display area to cover a portion of an upper surface of the inorganic insulating layer and a side surface of the inorganic insulating layer.

Description

Display device

Technical Field

Embodiments relate to a display device capable of displaying an image and a method of manufacturing the display device.

Background

Display devices are manufactured and used in various ways. The display device may display light to provide visual information to a user. Such display devices may include liquid crystal display devices that emit light using a liquid crystal layer, inorganic light emitting display devices that emit light using an inorganic light emitting material, and organic light emitting display devices that emit light using an organic light emitting material.

Luminescent materials may be sensitive to moisture or heat. Accordingly, the sealing member may be located outside the display device to protect the light emitting material. The sealing member may reduce or prevent moisture or heat from penetrating into the display device, and at the same time, may serve to protect the display device from external impact.

SUMMERY OF THE UTILITY MODEL

Embodiments may provide a display device having improved durability.

Embodiments may provide a method of manufacturing a display device having improved durability.

Some embodiments of a display device may include: a transistor substrate including a driving element and having a display region and a non-display region surrounding the display region; a bank layer on the non-display region of the transistor substrate and exposing an outer region of the non-display region of the transistor substrate opposite to the display region; an inorganic insulating layer covering an upper surface of the bank layer, a side surface of the bank layer, and an outer region of the transistor substrate; a low refractive layer on the inorganic insulating layer; and a first color filter layer on the non-display area to cover a portion of an upper surface of the inorganic insulating layer and a side surface of the inorganic insulating layer.

The first color filter layer may seal the bank layer, wherein a side surface of the first color filter layer is exposed to the outside.

The display device may further include: and a second color filter layer on the first color filter layer on the non-display area.

The display device may further include: and a third color filter layer on the second color filter layer on the non-display area.

The first color filter layer may seal the bank layer, and side surfaces of the first to third color filter layers are exposed to the outside.

The inorganic insulating layer may cover an outer region of the transistor substrate.

The low refractive layer may overlap the bank layer on an upper surface of the inorganic insulating layer.

The display device may further include: and a light emitting element on and connected to the driving element.

The display device may further include: a color conversion layer on the light emitting element to overlap the light emitting element; a second color filter layer on the color conversion layer; and a third color filter layer on the first color filter layer, wherein the second color filter layer is in the same layer as one of the first color filter layer and the third color filter layer.

Some embodiments of a display device may include: a transistor substrate including a driving element and having a display region and a non-display region surrounding the display region; a bank layer on the non-display region of the transistor substrate and exposing an outer region of the non-display region of the transistor substrate opposite to the display region; and a first color filter layer on an outer region of the transistor substrate, sealing the bank layer, and having a side surface exposed to the outside.

The display device may further include: a second color filter layer on the first color filter layer; and a third color filter layer on the second color filter layer.

The display device may further include: a color conversion layer overlapping the light emitting element; and a fourth color filter layer on the color conversion layer, wherein the fourth color filter layer is in the same layer as one of the first, second, and third color filter layers.

The first color filter layer may overlap an upper surface of the bank layer.

The display device may further include: and an inorganic insulating layer between the first color filter layer and the bank layer.

Some embodiments of a method of manufacturing a display device may include: forming a first bank layer on a non-display area of a transistor substrate, the transistor substrate including a driving element and having a display area and the non-display area surrounding the display area; removing a portion of the first bank layer to form a second bank layer spaced apart from the display area and to define a trench; forming a first inorganic insulating layer on the first bank layer, on the second bank layer, and on portions of the first bank layer and the second bank layer defining the trench; forming a low refractive layer on the first inorganic insulating layer to overlap at least a portion of the first bank layer; forming a first color filter layer on the first inorganic insulating layer to fill the trench; and cutting between the first bank layer and the second bank layer.

The method may further comprise: forming a second color filter layer on the first color filter layer; and forming a third color filter layer on the second color filter layer.

The method may further comprise: a light emitting element connected to the driving element is provided on the driving element.

The method may further comprise: disposing a color conversion layer on the light emitting element to overlap the light emitting element; disposing a second color filter layer on the color conversion layer; and disposing a third color filter layer on the first color filter layer, wherein the second color filter layer is deposited simultaneously with one of the first color filter layer and the third color filter layer.

The first color filter layer may be exposed to the outside.

Accordingly, in the display device, the color filter layer may reduce or prevent external moisture or heat from penetrating into the display device, and may protect an outer region of the display device from external impact.

Drawings

The illustrative, non-limiting embodiments will be best understood from the following detailed description when read in conjunction with the accompanying drawings.

Fig. 1 is a plan view illustrating a display device according to some embodiments.

Fig. 2A and 2B are cross-sectional views illustrating some embodiments taken along line I-I' of fig. 1.

Fig. 3 is a cross-sectional view illustrating some embodiments in which a pixel included in the display device of fig. 1 is cut along a line II-II' of fig. 1.

Fig. 4 to 13 are views illustrating a method of manufacturing the display device of fig. 1.

Fig. 14 is a block diagram illustrating an electronic device according to some embodiments.

FIG. 15 is a diagram illustrating some embodiments in which the electronic device of FIG. 14 is implemented as a computer monitor.

Fig. 16 is a diagram illustrating some embodiments in which the electronic device of fig. 14 is implemented as a smartphone.

Detailed Description

Aspects of some embodiments of the disclosure and methods of accomplishing the same may be understood more readily by reference to the detailed description of embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may have various modifications and may be embodied in various different forms, and should not be construed as being limited to only the embodiments illustrated herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey aspects of the disclosure to those skilled in the art, and it is to be understood that this disclosure covers all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure. Accordingly, processes, elements, and techniques may not be described that are not necessary for a complete understanding of aspects of the present disclosure by those of ordinary skill in the art.

Unless otherwise indicated, throughout the drawings and written description, the same reference numerals, characters, or combinations thereof denote the same elements, and thus the description thereof will not be repeated. In addition, portions irrelevant or unrelated to the description of the embodiments may not be shown to clarify the description.

In the drawings, the relative sizes of elements, layers and regions may be exaggerated for clarity. In addition, the use of cross-hatching and/or shading in the figures is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise indicated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated elements, and/or any other characteristic, attribute, property, etc. of an element.

Various embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. Thus, for example, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Furthermore, the specific structural or functional descriptions disclosed herein are merely illustrative for the purposes of describing embodiments according to the concepts of the present disclosure. Thus, embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing.

For example, an implanted region illustrated as a rectangle will typically have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs.

Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. In addition, as those of ordinary skill in the art will appreciate, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

In the detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the various embodiments. It may be evident, however, that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments.

Spatially relative terms, such as "below," "lower," "beneath," "above," and "upper" may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the example terms "below" and "beneath" can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Similarly, when a first component is described as being disposed "on" a second component, this indicates that the first component is disposed on the upper side or the lower side of the second component, and is not limited to being on the upper side of the second component based on the direction of gravity.

Further, in the present specification, the phrase "on a plane" or "plan view" means that the target portion is viewed from the top, and the phrase "on a cross section" means that a cross section formed by perpendicularly cutting the target portion is viewed from the side.

It will be understood that when an element, layer, region or component is referred to as being "formed on," "connected to" or "coupled to" another element, layer, region or component, it can be directly formed on, directly connected to or coupled to the other element, layer, region or component, directly on, directly connected to or coupled to the other element, layer, region or component, or indirectly formed on, indirectly connected to or coupled to the other element, layer, region or component, such that one or more intervening elements, layers, regions or components may be present. Further, this may be referred to collectively as direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or coupled to the other layer, region and/or component, or intervening layers, regions or components may be present. However, "directly connected/directly coupled" or "directly on. Meanwhile, other expressions describing a relationship between components such as "between.... Times", "directly between.. Times", or "adjacent to.. Times" and "directly adjacent to.. Times" may be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit and scope of the present disclosure. The description of an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," and the like may also be used herein to distinguish different classes or groups of elements. For the sake of simplicity, the terms "first", "second", etc. may denote "a first category (or first group)", "a second category (or second group)", etc., respectively.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

While one or more embodiments may be implemented differently, the particular process sequence may be performed differently than described. For example, two processes described in succession may be executed substantially concurrently, or may be executed in the reverse order to that described.

As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation rather than degree and are intended to account for inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. As used herein, "about" or "approximately" includes the stated value and is meant to be within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art, taking into account the measurement in question and the error associated with measurement of the specified quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value. Furthermore, the use of "may" when describing an embodiment of the disclosure refers to "one or more embodiments of the disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Referring to fig. 1, the display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may be disposed to surround the display area DA. However, in some embodiments, the non-display area NDA may be disposed only at least one side of the display area DA.

A plurality of pixels PX may be disposed in the display area DA. The plurality of pixels PX may include a driving element and a light emitting element connected to the driving element. The display device DD may display an image by emitting light from a plurality of pixels PX. For this reason, a plurality of pixels PX may be generally disposed in the display area DA. For example, a plurality of pixels PX may be arranged in a matrix form in the display area DA.

A driver for driving the plurality of pixels PX may be disposed in the non-display area NDA. The driver may include a data driver, a gate driver, a light emitting driver, a power voltage generator, a timing controller, and the like. The plurality of pixels PX may emit light based on a signal received from the driver.

Referring to fig. 1 and 2A, the display device DD may include a transistor substrate SUB, a VIA insulating layer VIA, a first light emitting element ED1, a pixel defining layer PDL, an encapsulation layer TFE, a first color conversion layer CVL1, a first bank layer BK1, a first inorganic insulating layer IIL1, a low refractive layer LR, a second inorganic insulating layer IIL2, a first color filter layer CF1, a second color filter layer CF2, a third color filter layer CF3, and an overcoat layer OC.

The first light emitting element ED1 may include a first anode electrode ANO1, a first intermediate layer ML1, and a first cathode electrode CATH1. The encapsulation layer TFE may include a first inorganic encapsulation layer IL1, an organic encapsulation layer OL, and a second inorganic encapsulation layer IL2.

The transistor substrate SUB may include a base substrate and a driving element disposed on the base substrate. The base substrate may comprise a flexible material or a rigid material.

A VIA insulating layer VIA may be provided on the transistor substrate SUB. The VIA insulating layer VIA may have a flat top surface to be disposed flat with the first light emitting elements ED1 (e.g., under the bottom surface of the first light emitting elements ED1 or coplanar with the bottom surface of the first light emitting elements ED 1). The VIA insulating layer VIA may include an organic insulating material. The VIA insulating layer VIA may be generally disposed in the display area DA and the non-display area NDA. The VIA insulating layer VIA may partially expose the transistor substrate SUB in the non-display region NDA.

The transistor substrate SUB may be connected to the first light emitting element ED1. The first anode electrode ANO1 of the first light emitting element ED1 may be connected to the transistor substrate SUB through a contact hole penetrating the VIA insulating layer VIA. The first light emitting element ED1 may emit light from the first interlayer ML1 using a voltage applied to the first anode electrode ANO1 and using a voltage applied to the first cathode electrode CATH1.

The pixel defining layer PDL may be disposed on the VIA insulating layer VIA. The pixel defining layer PDL may be used to divide the pixels PX. The pixel defining layer PDL may divide the pixels PX by dividing the light emitting elements. Further, the pixel defining layer PDL may function as a dam together with the VIA insulating layer VIA in the non-display area NDA. The dam may reduce or prevent an organic material constituting the organic encapsulation layer OL from being excessively spread in a process of forming the organic encapsulation layer OL.

The first inorganic encapsulation layer IL1 may be formed to cover the first light emitting element ED1, the pixel defining layer PDL, and the VIA insulating layer VIA. The organic encapsulation layer OL may be formed on the first inorganic encapsulation layer IL1, and may be relatively thickly formed to achieve a flat top surface in the display area DA. The second inorganic encapsulation layer IL2 may be formed on the organic encapsulation layer OL. The second inorganic encapsulation layer IL2 may be disposed to cover the first inorganic encapsulation layer IL1 in the non-display area NDA.

The first color conversion layer CVL1 may be disposed on the second inorganic encapsulation layer IL2 to overlap the first light emitting element ED1. The first color conversion layer CVL1 may be used to convert the wavelength of light emitted from the first light emitting element ED1. To this end, the first color conversion layer CVL1 may include one or more wavelength conversion materials and resins.

The first bank layer BK1 may be disposed to have a flat top surface in the non-display area NDA. The first bank layer BK1 may be disposed in the non-display area NDA, and in this case, the first bank layer BK1 may be disposed to expose an outer area EXA disposed in the non-display area NDA and may be opposite to the display area DA.

The first inorganic insulating layer IIL1 may be disposed to cover the first color conversion layer CVL1 and the first bank layer BK1. The first inorganic insulating layer IIL1 may be disposed to cover the top surface and the side surfaces of the first bank layer BK1 and the top surface of the transistor substrate SUB. The first inorganic insulating layer IIL1 may include an inorganic insulating material.

The low refractive layer LR may be disposed on the first inorganic insulating layer IIL 1. The low refractive layer LR may have a relatively lower refractive index than that of the first color conversion layer CVL 1. Accordingly, the low refractive layer LR may recover at least a portion of the light emitted from the first light emitting element ED1 to improve light utilization efficiency. As a result, the light efficiency of the display device DD may be improved.

The low refractive layer LR may be disposed in the display area DA and the non-display area NDA. The low refractive layer LR may be disposed on the first inorganic insulating layer ill 1 in the non-display area NDA and may overlap the first bank layer BK1. In this case, the low refractive layer LR may be disposed so as not to overlap the outer region EXA. The second inorganic insulating layer IIL2 may be disposed to cover the low refractive layer LR. The second inorganic insulating layer IIL2 may include an inorganic insulating material.

The first color filter layer CF1 may be disposed in the non-display area NDA to cover the first and second inorganic insulating layers IIL1 and IIL2. The first color filter layer CF1 may serve to seal the first bank layer BK1 together with the first inorganic insulating layer IIL 1. The first color filter layer CF1 may be disposed at an outermost portion of the display device DD, and thus the first color filter layer CF1 may be exposed to the outside.

The second color filter layer CF2 may be disposed in the non-display area NDA to cover the first color filter layer CF1. The second color filter layer CF2 may also be disposed to overlap the first light emitting elements ED1 in the display area DA.

The third color filter layer CF3 may be disposed on the second color filter layer CF2 in the non-display area NDA.

In some embodiments, the first to third color filter layers CF1, CF2, and CF3 may each correspond to a color filter layer of a different color. For example, the first color filter layer CF1 may be a green color filter layer, the second color filter layer CF2 may be a red color filter layer, and the third color filter layer CF3 may be a blue color filter layer.

In the region where the first to third color filter layers CF1, CF2, and CF3 overlap, the first to third color filter layers CF1, CF2, and CF3 may alternatively function as or as a black matrix, which will be described later. Therefore, it is not necessary to provide a separate black matrix in the region where the first to third color filter layers CF1, CF2 and CF3 overlap.

The overcoat layer OC may be disposed throughout the display area DA and the non-display area NDA. The overcoat layer OC may be disposed on the color filter layer to have a flat top surface.

In an embodiment, a protective film may be attached on the overcoat layer OC. In this case, in order to attach the protective film properly, the overcoat layer OC must be formed to have a flat top surface. In the display device DD according to some embodiments, since the first bank layer BK1 is disposed to have a flat top surface in the non-display area NDA, the overcoat layer OC may be disposed to have a flat top surface.

In addition, in the display device DD according to some embodiments, the first to third color filter layers CF1, CF2, and CF3 are disposed to overlap the non-display area NDA, so that the first to third color filter layers CF1, CF2, and CF3 may function as a light blocking member.

Further, in the display device DD according to some embodiments, since the first color filter layer CF1 is disposed while the first bank layer BK1 is sealed in the outer area EXA of the display device DD, it is possible to block external moisture or heat from penetrating into the outer area EXA of the display device DD.

Conventionally, the low refractive layer LR is disposed up to the outer region EXA, and is disposed while the first bank layer BK1 is sealed in the outer region EXA of the display device DD. Therefore, in this case, defects such as cracks may have occurred in the outer region EXA of the display device DD due to the characteristics of the low refractive layer LR, which may be generally weak against external impacts. However, in the display device DD according to some embodiments, since the first color filter layer CF1 is disposed while the first bank layer BK1 is sealed in the outer area EXA of the display device DD, the display device DD may have characteristics of external impact resistance or external impact resistance.

Fig. 2B may be substantially the same as fig. 2A except that a bank pattern DM is additionally formed. Therefore, description of the overlapping configuration will be omitted.

Referring to fig. 2B, a bank pattern DM may be formed on or at the first bank layer BK1. In the formation of the trench TC illustrated in fig. 6, the bank pattern DM may be formed through the same process as that of forming the trench TC, which will be described later. The bank pattern DM may be defined as a space for accommodating an erroneously deposited or erroneously placed ink when the first color conversion layer CVL1 is formed. Accordingly, it is possible to reduce or prevent the possibility of occurrence of cracks, gap defects, and the like in the first inorganic insulating layer IIL1 formed on the first bank layer BK1 due to erroneous ink or erroneously deposited ink.

Referring to fig. 1 and 3, the display device DD may include a base substrate BS, a buffer layer BUF, first to third transistors TFT1, TFT2 and TFT3, a gate insulating layer GI, an interlayer insulating layer ILD, a VIA hole insulating layer VIA, a pixel defining layer PDL, second to fourth light emitting elements ED2, ED3 and ED4, an encapsulation layer TFE, a first bank layer BK1, a second color conversion layer CVL2 and a third color conversion layer CVL3, a light transmitting layer ETL, a first inorganic insulating layer IIL1, a low refractive layer LR, a second inorganic insulating layer IIL2, a black matrix BM, fourth to sixth color filter layers CF4, CF5 and CF6, and an overcoat layer OC.

The first transistor TFT1 may include a first active layer ACT1, a first gate electrode GAT1, a first source electrode SE1, and a first drain electrode DE1. The second transistor TFT2 may include a second active layer ACT2, a second gate electrode GAT2, a second source electrode SE2, and a second drain electrode DE2. The third transistor TFT3 may include a third active layer ACT3, a third gate electrode GAT3, a third source electrode SE3, and a third drain electrode DE3.

The second light emitting element ED2 may include a second anode electrode ANO2, a second intermediate layer ML2, and a second cathode electrode CATH2. The third light emitting element ED3 may include a third anode electrode ANO3, a third intermediate layer ML3, and a third cathode electrode CATH3. The fourth light emitting element ED4 may include a fourth anode electrode ANO4, a fourth intermediate layer ML4, and a fourth cathode electrode CATH4.

The base substrate BS may include a flexible material or a rigid material. For example, the base substrate BS may have a flexible characteristic by including a polymer material such as polyimide. Alternatively, for example, the base substrate BS may have a rigid characteristic by including a material such as glass.

The buffer layer BUF may be disposed on the base substrate BS. The buffer layer BUF may include an inorganic insulating material. Examples of materials that may be used as the buffer layer BUF may include silicon oxide ("SiO _x "), silicon nitride (" SiN _x ") and silicon oxynitride (" SiON "), and the like. These materials may be used alone or in combination with each other. The buffer layer BUF may reduce or prevent diffusion of metal atoms or impurities into the first to third active layers ACT1, ACT2, and ACT3. In addition, the buffer layer BUF may control the rate of heat supplied to the first to third active layers ACT1, ACT2, and ACT3 during a crystallization process for forming the first to third active layers ACT1, ACT2, and ACT3.

The first to third active layers ACT1, ACT2, and ACT3 may be disposed on the buffer layer BUF. In some embodiments, the first to third active layers ACT1, ACT2, and ACT3 may include a silicon semiconductor. For example, the first to third active layers ACT1, ACT2, and ACT3 may include amorphous silicon, polycrystalline silicon, or the like. Alternatively, in some embodiments, the first to third active layers ACT1, ACT2, and ACT3 may include an oxide semiconductor. For example, the first to third active layers ACT1, ACT2, and ACT3 may include Indium Gallium Zinc Oxide (IGZO), indium Gallium Oxide (IGO), indium Zinc Oxide (IZO), or the like.

The gate insulating layer GI may be disposed on the buffer layer BUF. The gate insulating layer GI may be disposed to cover the first to third active layers ACT1, ACT2, and ACT3. The gate insulating layer GI may include an insulating material. Examples of materials that may be used as the gate insulating layer GI may include silicon oxide ("SiO _x "), silicon nitride (" SiN _x ") and silicon oxynitride (" SiON "), and the like. These materials may be used alone or in combination with each other.

The first to third gate electrodes GAT1, GAT2, and GAT3 may be disposed on the gate insulating layer GI. The first to third gate electrodes GAT1, GAT2, and GAT3 may overlap the first to third active layers ACT1, ACT2, and ACT3, respectively. Signals and/or voltages may flow through the first to third active layers ACT1, ACT2, and ACT3 in response to gate signals supplied to the first to third gate electrodes GAT1, GAT2, and GAT3. In some embodiments, the first to third gate electrodes GAT1, GAT2, and GAT3 may include a metal, an alloy, a metal oxide, a transparent conductive material, or the like. For example, the first to third gate electrodes GAT1, GAT2, and GAT3 may include silver ("Ag"), a silver-containing alloy, molybdenum ("Mo"), a molybdenum-containing alloy, aluminum ("Al"), an aluminum-containing alloy, aluminum nitride ("AlN"), tungsten ("W"), tungsten nitride ("WN"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), chromium nitride ("CrN"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), scandium ("Sc"), indium Tin Oxide (ITO), or Indium Zinc Oxide (IZO), and the like.

An interlayer insulating layer ILD may be disposed on the gate insulating layer GI. An interlayer insulating layer ILD may be disposed to cover the first to third gate electrodes GAT1, GAT2, and GAT3. In some embodiments, the interlayer insulating layer ILD may include an insulating material. Examples of a material that may be used as the interlayer insulating layer ILD may include silicon oxide ("SiO _x "), silicon nitride (" SiN _x ") and silicon oxynitride (" SiON "), and the like. These materials may be used alone or in combination with each other.

The first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3 may be disposed on the interlayer insulating layer ILD. The first source electrode SE1 and the first drain electrode DE1 may contact the first active layer ACT1. The second source electrode SE2 and the second drain electrode DE2 may contact the second active layer ACT2. The third source electrode SE3 and the third drain electrode DE3 may contact the third active layer ACT3. In some embodiments, the first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3 may include a metal, an alloy, a metal oxide, a transparent conductive material, or the like. For example, each of the first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3 may include silver ("Ag"), a silver-containing alloy, molybdenum ("Mo"), a molybdenum-containing alloy, aluminum ("Al"), an aluminum-containing alloy, aluminum nitride ("AlN"), tungsten ("W"), tungsten nitride ("WN"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), chromium nitride ("CrN"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), scandium ("Sc"), indium Tin Oxide (ITO), or Indium Zinc Oxide (IZO), and the like.

The VIA insulating layer VIA may be disposed on the interlayer insulating layer ILD. The VIA insulating layer VIA may be disposed to cover the first to third source electrodes SE1, SE2, and SE3 and the first to third drain electrodes DE1, DE2, and DE3. In some embodiments, the VIA insulating layer VIA may include an organic insulating material. For example, the VIA insulating layer VIA may include a photoresist, a polyacrylate resin, a polyimide resin, an acrylic resin, or the like. The VIA insulating layer VIA may have a substantially flat top surface.

The second to fourth anode electrodes ANO2, ANO3, and ANO4 may be disposed on the VIA insulating layer VIA. The second to fourth anode electrodes ANO2, ANO3, and ANO4 may contact the first to third drain electrodes DE1, DE2, and DE3, respectively. In some embodiments, each of the second to fourth anode electrodes ANO2, ANO3, and ANO4 may include a metal, an alloy, a metal oxide, a transparent conductive material, or the like. For example, each of the second to fourth anode electrodes ANO2, ANO3, and ANO4 may include silver ("Ag"), a silver-containing alloy, molybdenum ("Mo"), a molybdenum-containing alloy, aluminum ("Al"), an aluminum-containing alloy, aluminum nitride ("AlN"), tungsten ("W"), tungsten nitride ("WN"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), chromium nitride ("CrN"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), scandium ("Sc"), indium Tin Oxide (ITO), or Indium Zinc Oxide (IZO), and the like.

The pixel defining layer PDL may be disposed on the VIA insulating layer VIA. Openings exposing the second to fourth anode electrodes ANO2, ANO3, and ANO4 may be formed in the pixel defining layer PDL. In some embodiments, the pixel defining layer PDL may include an organic material. For example, the pixel defining layer PDL may include a photoresist, a polyacrylate resin, a polyimide resin, an acrylic resin, or the like.

The second to fourth intermediate layers ML2, ML3 and ML4 may be disposed on the second to fourth anode electrodes ANO2, ANO3 and ANO4, respectively. The second to fourth intermediate layers ML2, ML3 and ML4 may include organic materials that emit light of corresponding colors (e.g., predetermined colors). The second to fourth intermediate layers ML2, ML3, and ML4 may emit light based on potential differences between the second to fourth anode electrodes ANO2, ANO3, and ANO4 and the second to fourth cathode electrodes CATH2, CATH3, and CATH4, respectively.

The second to fourth light emitting elements ED2, ED3, and ED4 may emit light having the same color as each other. For example, all of the second to fourth light emitting elements ED2, ED3 and ED4 may emit blue light. Alternatively, the second to fourth light emitting elements ED2, ED3 and ED4 may emit different respective colors of light. For example, the second to fourth light emitting elements ED2, ED3 and ED4 may emit red, green and blue light, respectively.

The second to fourth cathode electrodes CATH2, CATH3, and CATH4 may be disposed on the second to fourth intermediate layers ML2, ML3, and ML4, respectively. The second to fourth cathode electrodes CATH2, CATH3 and CATH4 may include a metal, an alloy, a metal oxide, a transparent conductive material, or the like. For example, the second to fourth cathode electrodes CATH2, CATH3 and CATH4 may include silver ("Ag"), silver-containing alloy, molybdenum ("Mo"), molybdenum-containing alloy, aluminum ("Al"), aluminum-containing alloy, aluminum nitride ("AlN"), tungsten ("W"), tungsten nitride ("WN"), copper ("Cu"), nickel ("Ni"), chromium ("Cr"), chromium nitride ("CrN"), titanium ("Ti"), tantalum ("Ta"), platinum ("Pt"), scandium ("Sc"), indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), and the like. For convenience of description, the cathode electrodes have been described as being divided into or identified as the second to fourth cathode electrodes CATH2, CATH3 and CATH4, but the second to fourth cathode electrodes CATH2, CATH3 and CATH4 may be integrally formed.

The encapsulation layer TFE may be disposed on the second to fourth cathode electrodes CATH2, CATH3, and CATH4. The encapsulation layer TFE may have a structure in which an inorganic encapsulation layer and an organic encapsulation layer are stacked.

The first bank layer BK1, the second and third color conversion layers CVL2 and CVL3, and the light transmissive layer ETL may be disposed on the encapsulation layer TFE. The first bank layer BK1 may include an organic material. The first bank layer BK1 may block light emitted from below. The first bank layer BK1 may include an opening through which the encapsulation layer TFE is exposed. The second and third color conversion layers CVL2 and CVL3 and the light transmissive layer ETL may be disposed in the openings. In some embodiments, the bank pattern DM illustrated in fig. 2B may be formed on the first bank layer BK1. Accordingly, the bank pattern DM may accommodate the erroneously deposited ink when the second and third color conversion layers CVL2 and CVL3 and the light transmissive layer ETL are formed.

The second color conversion layer CVL2 may be disposed to overlap the second light emitting element ED 2. The second color conversion layer CVL2 may convert a wavelength of light emitted from the second light emitting element ED 2. To this end, the second color conversion layer CVL2 may include phosphors, scatterers, and quantum dots. For example, blue light emitted from the second light emitting element ED2 may be converted into red light by passing through the second color conversion layer CVL 2.

The third color conversion layer CVL3 may be disposed to overlap the third light emitting element ED 3. The third color conversion layer CVL3 may convert a wavelength of light emitted from the third light emitting element ED 3. To this end, the third color conversion layer CVL3 may include phosphors, scatterers, and quantum dots. For example, blue light emitted from the third light emitting element ED3 may be converted into green light by passing through the third color conversion layer CVL 3.

The light-transmissive layer ETL may be disposed to overlap the fourth light-emitting element ED 4. The light-transmissive layer ETL may transmit light emitted from the fourth light-emitting element ED 4. To this end, the light transmissive layer ETL may include a transparent polymer material and a diffuser. For example, blue light emitted from the fourth light emitting element ED4 may pass through the light transmissive layer ETL as it is.

The first inorganic insulating layer IIL1 may be providedAnd is disposed on the first bank layer BK1, the second and third color conversion layers CVL2 and CVL3, and the light transmissive layer ETL. The first inorganic insulating layer IIL1 may reduce or prevent penetration of impurities such as moisture and air from the outside. Examples of the material that can be used as the first inorganic insulating layer IIL1 may include silicon oxide ("SiO") _x "), silicon nitride (" SiN _x ") and silicon oxynitride (" SiON "), and the like. These materials may be used alone or in combination with each other.

The low refractive layer LR may be disposed on the first inorganic insulating layer IIL 1. The low refractive layer LR may have a relatively lower refractive index than the refractive indices of the second color conversion layer CVL2, the third color conversion layer CVL3, and the light transmissive layer ETL. Accordingly, the low refractive layer LR may recover at least a portion of light emitted from the second to fourth light emitting elements ED2, ED3, and ED4, thereby improving light use efficiency. As a result, the light efficiency of the display device DD may be improved.

The second inorganic insulating layer IIL2 may be disposed on the low refractive layer LR. The second inorganic insulating layer IIL2 may reduce or prevent penetration of impurities such as moisture and air from the outside. Examples of the material that can be used as the second inorganic insulating layer IIL2 may include silicon oxide ("SiO _x "), silicon nitride (" SiN _x ") and silicon oxynitride (" SiON "), and the like. These materials may be used alone or in combination with one another.

The black matrix BM and the fourth to sixth color filter layers CF4, CF5 and CF6 may be disposed on the second inorganic insulating layer IIL2. The black matrix BM may include a material capable of blocking light. For example, the black matrix BM may be formed of a material including an organic pigment of a suitable color (e.g., black). Accordingly, the black matrix BM may shield some of the light emitted from below the black matrix BM.

The fourth color filter layer CF4 may be disposed to overlap the second color conversion layer CVL 2. The fourth color filter layer CF4 may transmit only a part of wavelengths of light among the light transmitted from the second color conversion layer CVL 2. For example, the fourth color filter layer CF4 may transmit only light having a wavelength corresponding to red light.

The fifth color filter layer CF5 may be disposed to overlap the third color conversion layer CVL 3. The fifth color filter layer CF5 may transmit only a part of wavelengths of light among the light transmitted from the third color conversion layer CVL 3. For example, the fifth color filter layer CF5 may transmit only light having a wavelength corresponding to green light.

The sixth color filter layer CF6 may be disposed to overlap the light transmissive layer ETL. The sixth color filter layer CF6 may transmit only a part of wavelengths of light among the light transmitted from the light transmissive layer ETL. For example, the sixth color filter layer CF6 may transmit only light having a wavelength corresponding to blue light.

In an embodiment, the fourth to sixth color filter layers CF4, CF5 and CF6 may each correspond to one of the first to third color filter layers CF1, CF2 and CF3 of fig. 2A, for example, may each be in the same layer as one of the first to third color filter layers CF1, CF2 and CF3. For example, the fifth color filter layer CF5 may correspond to the first color filter layer CF1 of fig. 2A, the fourth color filter layer CF4 may correspond to the second color filter layer CF2 of fig. 2A, and the sixth color filter layer CF6 may correspond to the third color filter layer CF3 of fig. 2A.

The overcoat layer OC may be disposed on the black matrix BM and the fourth to sixth color filter layers CF4, CF5 and CF 6. An overcoat layer OC may be disposed on the black matrix BM and the fourth to sixth color filter layers CF4, CF5 and CF6 to have a substantially flat top surface. The overcoat layer OC may include an insulating material, and may be formed by an inkjet printing method.

Fig. 4 to 13 are views illustrating a method of manufacturing the display device of fig. 1. Fig. 4-13 may correspond to views illustrating the fabrication of some embodiments of region a in the cross-sectional view of fig. 2A.

Referring to fig. 4, 5, and 6, a trench TC may be formed in the first bank layer BK1 disposed on the transistor substrate SUB and having a flat top surface. Thereby, the first bank layer BK1 and the second bank layer BK2 can be formed. The trench TC may be formed in a portion of the non-display area NDA.

Referring to fig. 7, the first inorganic insulating layer IIL1 may be formed to cover the first bank layer BK1, the second bank layer BK2 and the trench TC (e.g., a side of the trench TC, or a side of the first bank layer BK1 and the second bank layer BK2 defining the trench TC). The first inorganic insulating layer IIL1 may be formed by chemical vapor deposition.

Referring to fig. 8, the low refractive layer LR may be formed on the first inorganic insulating layer IIL 1. The low refractive layer LR may be formed by an inkjet printing method and may be formed only on the upper portion of the first bank layer BK1 so as not to fill the trench TC.

Referring to fig. 9, the second inorganic insulating layer IIL2 may be formed to cover the low refractive layer LR. The second inorganic insulating layer IIL2 may be formed by chemical vapor deposition.

Referring to fig. 10, a first color filter layer CF1 may be provided to fill the trenches TC, and a second color filter layer CF2 and a third color filter layer CF3 may be formed on the first color filter layer CF1. They may be formed sequentially. The region where the first to third color filter layers CF1, CF2 and CF3 overlap may play the same role as the aforementioned black matrix BM.

Referring to fig. 11 to 13, in the method of manufacturing the display device DD, after the overcoat layer OC is formed on the sorting units, the sorting units may be separated by a scribing process. Thereby, the second bank layer BK2 in the outer region EXA may be exposed to the outside. That is, the scribing process may scribe the classification unit to expose the second bank layer BK2. Thereafter, grinding may be carried out up to line III-III'. By grinding, the portion to the left of line III-III' can be removed. Thereby, the first color filter layer CF1 may be exposed to the outside of the display device DD. Since the first color filter layer CF1 seals the first bank layer BK1, the first color filter layer CF1 may block external moisture or heat from penetrating into the inside of the display device DD. The second and third color filter layers CF2 and CF3 may also be exposed to the outside of the display device DD and may block external moisture or heat from penetrating into the inside of the display device DD.

Fig. 14 is a block diagram illustrating an electronic device according to some embodiments, fig. 15 is a view illustrating some embodiments in which the electronic device of fig. 14 is implemented as a computer monitor, and fig. 16 is a view illustrating some embodiments in which the electronic device of fig. 14 is implemented as a smartphone.

Referring to fig. 14, 15, and 16, some embodiments of an electronic device EA may include a processor 510, a memory device 520, a storage device 530, an input/output device 540, a power supply 550, and a display device 560. In some such embodiments, the display device 560 may correspond to the display device DD described above with reference to the above figures. The electronic device EA may further comprise several ports capable of communicating with video cards, sound cards, memory cards, USB devices, etc. In some embodiments, as illustrated in fig. 15, the electronic device EA may be implemented as a computer monitor. In other embodiments, as illustrated in fig. 16, the electronic apparatus EA may be implemented as a smartphone. However, the electronic apparatus EA is not limited thereto, and for example, the electronic apparatus EA includes a mobile phone, a video phone, a smart tablet, a smart watch, a tablet PC, a car navigation system, which may be implemented as a television, a notebook computer, or a head mounted display ("HMD"), or the like.

Processor 510 may perform specific calculations or tasks. In some embodiments, processor 510 may be a microprocessor, a central processing unit ("CPU"), or an application processor ("AP"), among others. The processor 510 may be connected to other components by an address bus, a control bus, a data bus, or the like. In some embodiments, processor 510 may also be connected to an expansion bus, such as a peripheral component interconnect ("PCI") bus.

The memory device 520 may store data for the operation of the electronic device EA. In some embodiments, for example, the memory device 520 may include a non-volatile memory device such as an erasable programmable read only memory ("EPROM") device, an electrically erasable programmable read only memory ("EEPROM") device, a flash memory device, a phase change random access memory ("PRAM") device, a resistive random access memory ("RRAM") device, a nano floating gate memory ("NFGM") device, a polymer random access memory ("ponam") device, a magnetic random access memory ("MRAM") device, a ferroelectric random access memory ("FRAM") device, and/or a volatile memory device such as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a mobile DRAM device.

The storage device 530 may include a solid state drive ("SSD"), a hard disk drive ("HDD"), a CD-ROM, or the like. The input/output devices 540 may include input devices such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and output devices such as speakers and printers.

The power supply 550 may provide power required for the operation of the electronic device EA. The display device 560 may be coupled to the other components via a bus or other communication link. According to some embodiments, the display device 560 may be included in the input/output device 540.

Embodiments of the display device may be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart tablet, a personal media player ("PMP"), a personal digital assistant ("PDA"), or an MP3 player, etc.

The present disclosure should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the disclosure to those skilled in the art.

While embodiments of the present disclosure have been particularly shown and described with reference to embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit or scope of the present disclosure as defined by the following claims, with functional equivalents thereof being included in the following claims.

Claims

1. A display device, comprising:

a transistor substrate including a driving element and having a display region and a non-display region surrounding the display region;

a bank layer on the non-display area of the transistor substrate and exposing an outer area of the non-display area of the transistor substrate opposite to the display area;

an inorganic insulating layer covering an upper surface of the bank layer, a side surface of the bank layer, and the outer region of the transistor substrate; and

a first color filter layer on the non-display area to cover a portion of an upper surface of the inorganic insulating layer and a side surface of the inorganic insulating layer.

2. The display device of claim 1, wherein the first color filter layer seals the bank layer, and

wherein a side surface of the first color filter layer is exposed to the outside.

3. The display device according to claim 1, further comprising:

a second color filter layer on the first color filter layer on the non-display area; and

a third color filter layer on the second color filter layer on the non-display area,

wherein the first color filter layer seals the bank layer, and side surfaces of the first to third color filter layers are exposed to the outside.

4. The display device according to claim 1, further comprising:

a low refractive layer on the inorganic insulating layer,

wherein the low refractive layer overlaps the bank layer on the upper surface of the inorganic insulating layer.

5. The display device according to claim 1, further comprising:

a light emitting element on and connected to the driving element;

a color conversion layer on the light emitting element to overlap with the light emitting element;

a second color filter layer on the color conversion layer; and

a third color filter layer on the first color filter layer,

wherein the second color filter layer is in the same layer as one of the first color filter layer and the third color filter layer.

6. A display device, comprising:

a bank layer on the non-display area of the transistor substrate and exposing an outer area of the non-display area of the transistor substrate opposite to the display area; and

a first color filter layer on the outer region of the transistor substrate, sealing the bank layer, and having a side surface exposed to the outside.

7. The display device according to claim 6, further comprising:

a second color filter layer on the first color filter layer; and

a third color filter layer on the second color filter layer.

8. The display device according to claim 7, further comprising:

a light emitting element on and connected to the driving element;

a color conversion layer overlapping the light emitting element; and

a fourth color filter layer on the color conversion layer,

wherein the fourth color filter layer is in the same layer as one of the first, second, and third color filter layers.

9. The display device of claim 6, wherein the first color filter layer is disposed on an upper surface of the bank layer,

wherein the first color filter layer overlaps the upper surface of the bank layer.

10. The display device according to any one of claims 6 to 9, further comprising:

an inorganic insulating layer between the first color filter layer and the bank layer.