CN218413458U

CN218413458U - Communication device adopting three serial peripheral interfaces to replace SSI (Small Scale integration) multiple slaves

Info

Publication number: CN218413458U
Application number: CN202222758020.8U
Authority: CN
Inventors: 俞志祥; 丁旭; 张鸿瑜
Original assignee: CRSC Communication and Information Group Shanghai Co Ltd
Current assignee: CRSC Communication and Information Group Shanghai Co Ltd
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2023-01-31
Anticipated expiration: 2032-10-19

Abstract

The utility model relates to an adopt three serial peripheral interface to replace communication device of many slaves of SSI, including an SSI host computer and respectively with many SPI slaves of SSI host computer communication, wherein every SPI slave computer including the first SPI interface that is used for realizing data transmission, the second SPI interface that is used for controlling the data transmission time of first SPI interface, be used for controlling the third SPI interface that first SPI interface transmission and stop and be used for avoiding many three state gate buffers of sending data conflict from the computer. Compared with the prior art, the utility model has the advantages of realize with low costs, avoid many to produce the conflict when sending data simultaneously from the machine.

Description

Communication device adopting three serial peripheral interfaces to replace SSI (Small network interface) multi-slave machine

Technical Field

The utility model relates to a communication device especially relates to an adopt three serial peripheral hardware interface to replace communication device of many slaves of SSI.

Background

Serial communication is a common communication mode in the field of modern electronic communication, and common Serial communication interfaces include an SPI (Serial Peripheral Interface) Interface and an SSI (Synchronous Serial Interface) Interface.

SSI is a full duplex serial interface featuring fast communication rates, typically up to 2Mbps and above. The SSI multi-slave schematic diagram is shown in fig. 1, and the SSI protocol timing diagram is shown in fig. 2.

SPI is also a full-duplex synchronous communication bus interface, the schematic diagram of SPI multi-slave is shown in fig. 3, and the timing diagram of SPI protocol is shown in fig. 4.

The existing mainstream chips such as 51 series, STM32 series and domestic chips thereof do not support SSI protocol, and because the communication speed is fast, analog communication cannot be performed by adopting an IO port analog mode generally. And chips supporting the SSI protocol are fewer, such as SAM4S series of Atmel corporation, and the price is also higher. The chip has low selectivity, and the purchase and use of the chip are also easily limited, so that the use platform is inconvenient to transplant and replace.

Therefore, how to replace the expensive SSI with the cheaper SPI for the master and slave devices and implement SSI communication becomes a technical problem to be solved.

SUMMERY OF THE UTILITY MODEL

The present invention is directed to overcome the above-mentioned drawbacks of the prior art, and provides a communication device using three serial peripheral interfaces instead of multiple SSI slaves.

The purpose of the utility model can be realized through the following technical scheme:

according to an aspect of the utility model provides an adopt three serial peripheral interface to replace communication device of many slaves of SSI, including an SSI host computer and respectively with many SPI slaves of SSI host computer communication, wherein every SPI slave computer is including the first SPI interface that is used for realizing data transmission, the second SPI interface that is used for controlling the data transmission time of first SPI interface, the third SPI interface that is used for controlling first SPI interface transmission and stops and the three state gate buffer that is used for avoiding many slaves to send data conflict.

As a preferred technical solution, the first SPI interface includes a first signal input pin SPI1 MOSI, a first signal output pin SPI1 MISO, a first Clock signal input pin SPI1 Clock, and a control pin SPI1CS.

As a preferred technical scheme, the first signal input pin SPI1 MOSI is connected to a signal output interface Data Out of an SSI host; the first signal output pin SPI1 MISO is connected with a signal input interface Data In of the SSI host through a tri-state gate buffer; the first Clock signal input pin SPI1 Clock is connected to a Clock signal output interface SSI Clock of the SSI host.

As a preferred technical solution, the second SPI interface includes a second signal output pin SPI2MISO and a second Clock signal input pin SPI2Clock, the second signal output pin SPI2MISO is connected to the control pin SPI1CS and the control pin of the tri-state gate buffer, respectively, and the second Clock signal input pin SPI2Clock is connected to the Clock signal output interface SSI Clock of the SSI host.

As a preferred technical solution, the third SPI interface includes a Frame synchronization signal receiving pin SPI3 CS and a third Clock signal input pin SPI1 Clock, the Frame synchronization signal receiving pin SPI3 CS is connected to a Frame synchronization signal output interface Frame Sync of the SSI host, and the third Clock signal input pin SPI1 Clock is connected to a Clock signal output interface SSI Clock of the SSI host.

As a preferred technical solution, the frame synchronization signal receiving pin SPI3 CS is a receiving pin capable of capturing a pulse signal in a frame synchronization signal.

As a preferred technical solution, an input pin of the tri-state gate buffer is connected to the first signal output pin SPI1 MISO, and an output pin of the tri-state gate buffer is connected to the signal input interface Data In of the SSI host.

As a preferred technical solution, the third SPI interface is an SPI supporting the TI mode, and the first SPI interface and the second SPI interface are general SPIs.

As a preferred technical solution, the first SPI interface is an SPI using a DMA transfer mode.

As a preferred technical solution, the first SPI interface is an SPI using an interrupted or blocked transmission mode.

Compared with the prior art, the utility model has the advantages of it is following:

1) Compare in using special chip of SSI, the utility model discloses only need increase 4 interfaces and 1 tristate gate device just can realize with the effect that SSI communication is the same, to most chips, interface resources are more, increase 4 interfaces far more than change the chip convenient many.

2) The three-state gate buffer can avoid the collision when multiple slaves send data simultaneously, and the size of the device is only about 2.4mm x 2.15mm, the size is small, the price does not exceed 2 yuan usually, and the cost is low. Meanwhile, the device is also a universal device and is easy to purchase and replace.

3) Support the SPI of TI mode usually transmission data length and do not exceed 32 bit BITS, can not support the SSI protocol data of longer data length, the utility model discloses a 1 SPI and 2 general SPIs that support the TI mode of combination alright with the various condition in self-defining data reception length, the compatible SSI agreement.

Drawings

Fig. 1 is a diagram of conventional SSI multi-slave hardware;

fig. 2 is a timing diagram of SSI protocol signals;

FIG. 3 is a schematic diagram of a SPI multiple slave;

FIG. 4 is a timing diagram of SPI protocol signals

Fig. 5 is a schematic structural view of the present invention;

fig. 6 is a specific circuit diagram of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, of the embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall fall within the protection scope of the present invention.

As shown in fig. 5 and 6, the utility model relates to an adopt three serial peripheral interface to replace communication device of many slaves of SSI, including an SSI host computer and respectively with many SPI slaves of SSI host computer communication, wherein every SPI slave computer is including the first SPI interface SPI1 that is used for realizing data transmission, the second SPI interface SPI2 that is used for controlling the data transmission time of first SPI interface, the third SPI interface SPI3 that is used for controlling first SPI interface transmission and stops and the three state gate buffer that is used for avoiding many slaves to send data conflict. The utility model discloses make up 3 SPI, SPI3 through 1 support TI (Texas Instruments) mode provides the frame synchronization function, carries out data transmission through SPI1, through SPI2 control SPI 1's transmission, avoids many from the machine transmission data conflict through three state gate buffers. The communication mode that SSI replaces a plurality of slave machines is realized.

The first SPI interface comprises a first signal input pin SPI1 MOSI, a first signal output pin SPI1 MISO, a first Clock signal input pin SPI1 Clock and a control pin SPI1CS. The first signal input pin SPI1 MOSI is connected with a signal output interface Data Out of the SSI host; the first signal output pin SPI1 MISO is connected with a signal input interface Data In of the SSI host through a tri-state gate buffer; the first Clock signal input pin SPI1 Clock is connected to a Clock signal output interface SSI Clock of the SSI host.

The second SPI interface comprises a second signal output pin SPI2MISO and a second Clock signal input pin SPI2Clock, the second signal output pin SPI2MISO is respectively connected with a control pin SPI1CS and a control pin of the tri-state gate buffer, and the second Clock signal input pin SPI2Clock is connected with a Clock signal output interface SSI Clock of the SSI host.

The third SPI interface comprises a Frame synchronization signal receiving pin SPI3 CS and a third Clock signal input pin SPI1 Clock, the Frame synchronization signal receiving pin SPI3 CS is connected with a Frame synchronization signal output interface Frame Sync of the SSI host, and the third Clock signal input pin SPI1 Clock is connected with a Clock signal output interface SSI Clock of the SSI host. The frame synchronization signal receiving pin SPI3 CS is a receiving pin capable of capturing a pulse signal in the frame synchronization signal, and is configured to capture the pulse signal in the frame synchronization signal, so that the third SPI interface tracks the frame synchronization signal, and then controls transmission and stop of the first SPI interface through the third SPI interface. And an input pin of the tri-state gate buffer is connected with a first signal output pin SPI1 MISO, and an output pin of the tri-state gate buffer is connected with a signal input interface Data In of the SSI host.

The utility model discloses a data transmission process as follows:

clock signals of the SSI protocol are sent to the SPI1 Clock, the SPI2Clock and the SPI3 Clock of each slave; frame synchronization signals of the SSI protocol are sent to the SPI3 CS of each slave; pulse signals in the frame synchronization signals are captured through the SPI3 supporting the TI mode, the SPI3 can track the frame synchronization signals, and then the SPI3 controls the transmission and stop of the SPI1, so that the synchronism of the slave is guaranteed. And a data output signal of the SSI protocol is sent to the SPI1 MOSI of each slave, and the SPI1 MISO is connected with an input pin of the three-state gate buffer and carries out data communication through the SPI 1. And a data input signal of the SSI protocol is connected with the output end of the tri-state gate buffer of each slave. The SPI2MISO of each slave outputs control signals of corresponding time slots of different slaves, the control signals are sent to the control pins of the SPI1CS and the three-state gate buffer, the data sending time of the SPI1 is controlled, and data sending conflicts of different slaves are avoided.

The third SPI interface is SPI supporting TI mode, and the first SPI interface and the second SPI interface are general SPI. Support the SPI of TI mode usually transmission data length and do not exceed 32 bit BITS, can not support the SSI protocol data of longer data length, the utility model discloses a 1 SPI and 2 general SPIs that support the TI mode of combination alright with the various condition in self-defining data reception length, the compatible SSI agreement.

The first SPI interface is an SPI adopting a DMA transmission mode. Not only can reduce the expenditure of chip CPU resources, but also can realize the continuous output of the clock. DMA can also be in single (Normal) or round robin (Circular) mode, which is re-enabled after each interrupt and does not need to be re-enabled.

In another embodiment, the SPI of the present invention is not limited to the DMA transfer mode, and can also be in the interrupted or blocked transfer mode.

The utility model discloses can select for use common ST (meaning semiconductor), GD (the easy innovation of megaly), SH (well glume electron), chip that 51 singlechips etc. supported the SPI communication is not being confine to the chip and must support SSI communication protocol, greatly reduced development cost and transplantation cost, alternative increase by a wide margin, the price is also cheaper. At present, the chip in the international market is in short supply, and the chip is easier to obtain by selecting a domestic chip, and the cost can be greatly reduced. The SPI agreement is similar with SSI agreement part, so can't directly replace, nevertheless pass through the utility model discloses the improvement of scheme back, just can replace SSI agreement through SPI and communicate.

As shown in fig. 6, the communication device further includes an MCU connected to the first SPI interface SPI1, the second SPI interface SP2, and the third SPI interface, respectively, and the MCU is further connected to a power supply circuit, a crystal oscillator circuit, and the like.

The utility model discloses a special noun explanation

SSI (Synchronous Serial Interface);

SPI (Serial Peripheral Interface);

DMA (Direct Memory Access);

CS (Select Chip Select from device);

MISO (slave device data out);

MOSI (slave device data input);

NSS (Negative Slave Select selected from device);

frame Sync (Frame Sync signal);

TI (Texas Instruments).

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A communication device adopting three serial peripheral interfaces to replace SSI multiple slave machines is characterized by comprising an SSI host machine and a plurality of SPI slave machines which are respectively communicated with the SSI host machine, wherein each SPI slave machine comprises a first SPI interface used for realizing data transmission, a second SPI interface used for controlling the data sending time of the first SPI interface, a third SPI interface used for controlling the transmission and the stop of the first SPI interface and a tri-state gate buffer used for avoiding the data conflict sent by the multiple slave machines.

2. The communication device as claimed in claim 1, wherein the first SPI interface comprises a first signal input pin SPI1 MOSI, a first signal output pin SPI1 MISO, a first Clock signal input pin SPI1 Clock and a control pin SPI1CS.

3. The communication device of claim 2, wherein the first signal input pin SPI1 MOSI is connected to a signal output interface Data Out of the SSI master; the first signal output pin SPI1 MISO is connected with a signal input interface Data In of the SSI host through a tri-state gate buffer; and the first Clock signal input pin SPI1 Clock is connected with a Clock signal output interface SSI Clock of the SSI host.

4. The communication device of claim 2, wherein the second SPI interface comprises a second signal output pin SPI2MISO and a second Clock signal input pin SPI2Clock, the second signal output pin SPI2MISO is connected to the control pin SPI1CS and the control pin of the tri-state gate buffer, respectively, and the second Clock signal input pin SPI2Clock is connected to the Clock signal output interface SSI Clock of the SSI master.

5. The communication device of claim 2, wherein the third SPI interface comprises a Frame synchronization signal receiving pin SPI3 CS and a third Clock signal input pin SPI1 Clock, the Frame synchronization signal receiving pin SPI3 CS is connected to a Frame synchronization signal output interface Frame Sync of the SSI master, and the third Clock signal input pin SPI1 Clock is connected to a Clock signal output interface SSI Clock of the SSI master.

6. The communication device as claimed in claim 5, wherein the frame synchronization signal receiving pin SPI3 CS is a receiving pin for capturing a pulse signal in the frame synchronization signal.

7. The communication device of claim 2, wherein an input pin of the tri-state gate buffer is connected to the first signal output pin SPI1 MISO, and an output pin of the tri-state gate buffer is connected to the signal input interface Data In of the SSI master.

8. The communication device of claim 1, wherein the third SPI interface is an SPI supporting TI mode, and the first SPI interface and the second SPI interface are general purpose SPIs.

9. The communication device according to claim 1, wherein the first SPI interface is an SPI using a DMA transfer mode.

10. The communication device according to claim 1, wherein the first SPI interface is an SPI using an interrupted or blocked transmission mode.