CN218071453U

CN218071453U - High-power PIN limiter chip

Info

Publication number: CN218071453U
Application number: CN202222893100.4U
Authority: CN
Inventors: 李佳瑶; 罗力伟; 王祁钰
Original assignee: Sichuan Yifeng Electronic Science & Technology Co ltd
Current assignee: Sichuan Yifeng Electronic Science & Technology Co ltd
Priority date: 2022-11-01
Filing date: 2022-11-01
Publication date: 2022-12-16
Anticipated expiration: 2032-11-01

Abstract

The utility model discloses a high-power PIN amplitude limiter chip, which comprises an amplitude limiter chip, wherein one end of the amplitude limiter chip is connected with a radio frequency port RFin, and the other end of the amplitude limiter chip is connected with a radio frequency port RFout through a blocking capacitor C1; the limiter chip comprises a three-stage PIN geminate transistor limiting circuit, a circular inductor L1 is arranged between a first-stage circuit and a second-stage circuit, and the second-stage circuit and the third-stage circuit are single-stage geminate transistor limiting circuits with the same structure; the utility model discloses a high-power PIN amplitude limiter chip, wherein the first level equally divides the total input power into two paths by adopting a double-input method, so that the power resistance is doubled; the pair transistors are adopted to replace inductance coils to provide a direct current network, so that the power capacity of the circuit is improved; the cascaded multistage amplitude limiting circuit can further improve the power capacity and the isolation degree of the circuit.

Description

High-power PIN limiter chip

Technical Field

The utility model belongs to the technical field of electronic communication, especially, relate to a high-power PIN amplitude limiter chip.

Background

The high-power amplitude limiter is a common microwave control device in a wireless transceiving system, particularly a high-power radar system, is generally used at the front end of a receiving system, and prevents large signals such as leakage power of a transmitter, irradiation of adjacent radar, scattering of a near-distance target and the like from entering a receiver and burning sensitive devices such as low-noise amplifier and the like. The output power of a GaAs monolithic power amplifier is about 10W, and with the rapid development of electronic warfare systems in recent years, the radar transmission power increases rapidly, which puts a severe demand on the power-tolerant performance of the limiter. Therefore, the development of a limiter of higher power is urgent.

SUMMERY OF THE UTILITY MODEL

The utility model provides a high-power PIN limiter chip aims at solving the above-mentioned problem that exists.

The utility model discloses a realize like this, a high-power PIN limiter chip, including the limiter chip, one end of limiter chip is connected with radio frequency port RFin, and the other end passes through blocking capacitor C1 and is connected with radio frequency port RFout; the limiter chip comprises a three-level PIN geminate transistor limiter circuit, a circular inductor L1 is arranged between a first-level circuit and a second-level circuit, and the second-level circuit and the third-level circuit are single-level geminate transistor limiter circuits with the same structure;

the first-stage circuit adopts double inputs and divides the total input power into two paths; the upper half part and the lower half part of the first-stage circuit are completely the same and comprise a microstrip line TL2, a microstrip line TL3, a pair of PIN tubes D1, a microstrip line TL4 and a microstrip line TL5 which are connected in sequence;

the second-stage circuit is composed of a pair of PIN tubes D2, and the third-stage circuit is composed of a pair of PIN tubes D3.

Further, the front end of the first-stage circuit is connected with a microstrip line TL1, and the other end of the microstrip line TL1 is connected with a radio frequency port RFin; the rear end of the first-stage circuit is connected with a microstrip line TL6, and the other end of the microstrip line TL6 is connected with a circular inductor L1.

Further, a microstrip line TL7 is arranged between the second-stage circuit and the third-stage circuit, and a microstrip line TL8 is connected to the rear end of the third-stage circuit; one end of the microstrip line TL8 is connected with the third-stage circuit, and the other end of the microstrip line TL8 is connected with the blocking capacitor C1.

Further, a pair of the PIN diode D1, the PIN diode D2, and the PIN diode D3 are connected oppositely.

Further, the anode of one of the PIN diodes D1 is connected to ground, the cathode is connected to the anode of the other PIN diode D1, and the cathode of the other PIN diode D1 is grounded.

Further, the rf port RFin and the rf port RFout both match 50 ohm impedance.

Compared with the prior art, the beneficial effects of the utility model are that: the utility model discloses a high-power PIN amplitude limiter chip, wherein the first level equally divides the total input power into two paths by adopting a double-input method, so that the power resistance is doubled; the pair transistors are adopted to replace inductance coils to provide a direct current network, so that the power capacity of the circuit is improved; the cascaded multistage amplitude limiting circuit can further improve the power capacity and the isolation degree of the circuit; in the utility model, the frequency range is 1.2-1.4GHz, and the input/output port matching impedance is 50 omega; the output end is provided with a blocking capacitor.

Drawings

FIG. 1 is a schematic structural view of the present invention;

FIG. 2 is an assembly view of the present invention;

fig. 3 is an insertion loss test curve of the present invention;

fig. 4 is a standing wave test curve of the present invention;

fig. 5 is a test curve of the slice level of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.

In the description of the present invention, it is to be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are merely for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. In addition, in the description of the present invention, "a plurality" means two or more unless specifically limited otherwise.

As shown in fig. 1-5, a high-power PIN limiter chip includes a three-stage PIN pair tube limiter circuit, where the first-stage circuit 1 adopts dual input to divide the total input power into two paths, a circular inductor is indirectly connected between the first-stage circuit 1 and the second-stage circuit 2, the second-stage circuit 2 and the third-stage circuit 3 are single-stage pair tube limiter circuits with the same structure, one end of the limiter chip is connected with a radio frequency port RFin, and the other end is connected with a dc blocking capacitor and a radio frequency port RFout;

the upper half part and the lower half part of the first-stage circuit 1 are completely the same and comprise a microstrip line TL2, a microstrip line TL3, a pair of PIN tubes D1, a microstrip line TL4 and a microstrip line TL5 which are connected in sequence; the second-stage circuit 2 consists of a pair of PIN tubes D2, and the third-stage circuit 3 consists of a pair of PIN tubes D3;

one end of the microstrip line TL1 is connected with a radio frequency port RFin, and the other end of the microstrip line TL1 is connected with a first-stage circuit 1; one end of the microstrip line TL6 is connected with the first-stage circuit 1, and the other end of the microstrip line TL6 is connected with the circular inductor L1; the microstrip line TL7 is positioned between the second-stage circuit 2 and the third-stage circuit 3; one end of the microstrip line TL8 is connected with the third-stage circuit 3, and the other end is connected with the blocking capacitor C1, and the blocking capacitor C1 is connected with the radio frequency port RFout;

the PIN diodes D1, D2 and D3 are connected oppositely, wherein the anode of one diode is connected with the ground, the cathode of the diode is connected with the anode of the other diode, and the cathode of the diode is grounded;

as shown in fig. 2, a proposed assembly of the limiter chip is given, with an input/output port matching impedance of 50 Ω; one end of the chip is connected with the radio frequency port RFin, and the other end of the chip is connected with the radio frequency port RFout; the chip is provided with a plurality of grounding ends, so that good radio frequency grounding connection can be kept;

as shown in fig. 3, the insertion loss of the limiter chip is given, when the power of the incident signal is lower than the trigger threshold of the limiter circuit, the circuit does not perform the limiting function, the incident signal is attenuated during transmission, the attenuation value is referred to as the insertion loss of the limiter, and the microwave limiter with good performance requires small insertion loss. At 1.2-1.4GHz, the insertion loss of the limiter chip is not more than-0.3 dB.

As shown in fig. 4, a standing wave of the limiter chip is given, and the smaller the standing wave ratio, the larger the incident power, and the higher the transmission efficiency.

As shown in fig. 5, the slice level of the slice chip is given, and when the input power is greater than the threshold level of the slice, the output power of the slice circuit is maintained at a nearly constant value, which is called the slice level, and the magnitude of the constant output power depends on the flat leakage power of the slice circuit. When the amplitude limiter is used, the amplitude limiting level of the amplitude limiter can be slightly larger than (or a plurality of protective gaps are set) the maximum input power of a post-stage device of the amplitude limiter.

The above description is only exemplary of the present invention and should not be construed as limiting the present invention, and any modifications, equivalents and improvements made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. The utility model provides a high-power PIN limiter chip, includes the limiter chip, its characterized in that: one end of the limiter chip is connected with the radio frequency port RFin, and the other end of the limiter chip is connected with the radio frequency port RFout through the blocking capacitor C1; the limiter chip comprises a three-level PIN geminate transistor limiter circuit, a circular inductor L1 is arranged between a first-level circuit and a second-level circuit, and the second-level circuit and the third-level circuit are single-level geminate transistor limiter circuits with the same structure;

2. The high power PIN slicer chip as claimed in claim 1 wherein: the front end of the first-stage circuit is connected with a microstrip line TL1, and the other end of the microstrip line TL1 is connected with a radio frequency port RFin; the rear end of the first-stage circuit is connected with a microstrip line TL6, and the other end of the microstrip line TL6 is connected with the circular inductor L1.

3. The high power PIN slicer chip as claimed in claim 1, wherein: a microstrip line TL7 is arranged between the second-stage circuit and the third-stage circuit, and the rear end of the third-stage circuit is connected with a microstrip line TL8; one end of the microstrip line TL8 is connected with the third-stage circuit, and the other end of the microstrip line TL8 is connected with the blocking capacitor C1.

4. The high power PIN slicer chip as claimed in claim 1, wherein: and the PIN tube D1, the PIN tube D2 and the PIN tube D3 are connected oppositely.

5. The high power PIN slicer chip of claim 4 wherein: the anode of one PIN tube D1 is connected with the ground, the cathode of the other PIN tube D1 is connected with the anode of the other PIN tube D1, and the cathode of the other PIN tube D1 is grounded.

6. The high power PIN slicer chip as claimed in claim 1 wherein: the radiofrequency port RFin and the radiofrequency port RFout both match a 50 ohm impedance.