CN217767435U - Profibus bus double-channel redundant communication module - Google Patents
Profibus bus double-channel redundant communication module Download PDFInfo
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- CN217767435U CN217767435U CN202123351611.5U CN202123351611U CN217767435U CN 217767435 U CN217767435 U CN 217767435U CN 202123351611 U CN202123351611 U CN 202123351611U CN 217767435 U CN217767435 U CN 217767435U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The utility model relates to a redundant communication module of Profibus bus binary channels, including data receiving and sending unit, still include the main circuit and the backup circuit that are electrified to operate and communicate with the system main website simultaneously; the master circuit comprises a master circuit level and differential conversion unit, a master circuit central control CPU unit and a master circuit communication protocol analysis FPGA unit which are sequentially connected; the backup circuit comprises a backup circuit level and difference conversion unit, a backup circuit central control CPU unit and a backup circuit communication protocol analysis FPGA unit which are sequentially connected; the data receiving and sending unit is respectively connected with the master circuit and the backup circuit; the master circuit is connected with the backup circuit; when a fault occurs in the communication process of the automation system and the field signal unit and other working modes must be switched or the maintenance must be carried out, the system does not need to be shut down, the communication cannot be interfered, the continuous work can be carried out, and the production efficiency is not influenced.
Description
Technical Field
The utility model belongs to the technical field of it is automatic, concretely relates to redundant communication module of Profibus bus binary channels.
Background
The Profibus bus is a leading industrial automation field bus in the global market, is suitable for communication between an automation system and a field signal unit, can also be directly connected with a transmitter with an interface, an actuator, a transmission device and other field instruments and equipment to collect and monitor field signals, replaces a large number of traditional transmission cables with a pair of twisted-pair wires, greatly saves the cost of the cables, and correspondingly saves the maintenance time and cost after construction debugging and system operation. However, once a fault occurs in the communication process, other operation modes must be switched or the system must be overhauled, and at this time, the system must be stopped, which may cause interference to the communication and result in the failure of continuous operation, thereby affecting the production efficiency.
Disclosure of Invention
An object of the utility model is to provide a redundant communication module of Profibus bus binary channels.
In order to achieve the above purpose, the technical scheme of the utility model is that: the system comprises a data receiving and sending unit, a master circuit and a backup circuit, wherein the master circuit and the backup circuit are powered on and operate simultaneously and communicate with a system master station; the master circuit comprises a master circuit communication protocol analysis FPGA unit; the backup circuit comprises a backup circuit communication protocol analysis FPGA unit; the data receiving and sending unit is respectively connected with the master circuit and the backup circuit; the master circuit is connected with the backup circuit.
As a further improvement, the master circuit further comprises a master circuit level and differential conversion unit and a master circuit central control CPU unit which are connected in sequence; and the master circuit communication protocol analysis FPGA unit is connected with the master circuit central control CPU unit.
As a further improvement, the backup circuit further comprises a backup circuit level and differential conversion unit and a backup circuit central control CPU unit which are connected in sequence; the backup circuit communication protocol analysis FPGA unit is connected with the backup circuit central control CPU unit.
As a further improvement, the master circuit further comprises a master circuit power supply unit; the master circuit power supply unit is respectively connected with the master circuit central control CPU unit, the master circuit communication protocol analysis FPGA unit and the master circuit level and differential conversion unit.
As a further improvement, the backup circuit further comprises a backup circuit power supply unit; the backup circuit power supply unit is respectively connected with the backup circuit central control CPU unit, the backup circuit communication protocol analysis FPGA unit and the backup circuit level and differential conversion unit.
As a further improvement, a data sending and receiving circuit is arranged in the data receiving and sending unit; the data transmitting and receiving circuit is connected with the wired driver receiver chip.
As a further improvement, a master circuit protocol chip is arranged in the master circuit communication protocol analysis FPGA unit; and a backup circuit protocol chip is arranged in the backup circuit communication protocol analysis FPGA unit.
As a further improvement, a master isolation conversion circuit is arranged in the master circuit level and differential conversion unit; the master isolation conversion circuit is connected with a master circuit isolator chip; and a master circuit control chip is arranged in the master circuit central control CPU unit.
As a further improvement, a backup isolation conversion circuit is arranged in the backup circuit level and differential conversion unit; the backup isolation conversion circuit is connected with a backup circuit isolator chip; and a backup circuit control chip is arranged in the backup circuit central control CPU unit.
As a further improvement, the data receiving and sending unit accesses a profibus dp bus.
The above technical scheme of the utility model following beneficial effect has: when the communication process of the automation system and the field signal unit breaks down and other working modes are required to be switched or maintained, the system does not need to be shut down, cannot interfere communication, can continuously work, and does not influence the production efficiency.
Drawings
FIG. 1 is a schematic diagram of a communication module;
fig. 2 is a diagram of the access effect of the communication module;
FIG. 3 is a circuit diagram of a data receiving/transmitting unit;
FIG. 4 is a circuit diagram of a first part of a central control CPU unit of a master circuit;
FIG. 5 is a circuit diagram of a second part of a central control CPU unit of a master circuit;
FIG. 6 is a view showing the structure of the first plug connector;
FIG. 7 is a view showing a second plug connector;
FIG. 8 is a circuit diagram of a master circuit level and differential conversion unit;
fig. 9 is a circuit diagram of a master circuit communication protocol analysis FPGA unit.
Detailed Description
The following describes embodiments of the present invention in detail with reference to the accompanying drawings and examples.
Referring to fig. 1, the communication module includes a data receiving and transmitting unit 3, and further includes a primary circuit 1 and a backup circuit 2 that are powered on and operate simultaneously and communicate with a system master station; the master circuit 1 comprises a master circuit level and difference conversion unit 14, a master circuit central control CPU unit 11 and a master circuit communication protocol analysis FPGA unit 12 which are connected in sequence;
the master circuit 1 further comprises a master circuit power supply unit 13; the master circuit power supply unit 13 is respectively connected with the master circuit central control CPU unit 11, the master circuit communication protocol analysis FPGA unit 12 and the master circuit level and difference conversion unit 14; the master circuit power supply unit 13 provides power for the master circuit central control CPU unit 11, the master circuit communication protocol analysis FPGA unit 12 and the master circuit level and difference conversion unit 14;
the backup circuit 2 comprises a backup circuit level and difference conversion unit 24, a backup circuit central control CPU unit 21 and a backup circuit communication protocol analysis FPGA unit 22 which are connected in sequence;
the backup circuit 2 further includes a backup circuit power supply unit 23; the backup circuit power supply unit 23 is respectively connected with the backup circuit central control CPU unit 21, the backup circuit communication protocol analysis FPGA unit 22, and the backup circuit level and difference conversion unit 24; the backup circuit power supply unit 23 supplies power to the backup circuit central control CPU unit 21, the backup circuit communication protocol analysis FPGA unit 22, and the backup circuit level and difference conversion unit 24;
the data receiving and sending unit 3 is respectively connected with the master circuit 1 and the backup circuit 2;
referring to fig. 1 and fig. 2, the system master station and the central controller access the profibus dp bus; the central controller can control various types of sensors or actuators and can monitor the running states and specific parameters of the sensors or actuators in all distributed nodes in real time; a communication module is arranged in each sensor or actuator; when the system master station and the actuator are powered on and operated, the master circuit 1 works in a default state; the master circuit 1 is communicated with a system master station and performs data interaction, receives control and query instructions of the system master station, and feeds back state information and data information of a sensor or an actuator to the system master station to ensure normal work. Under the condition that the master circuit 1 works normally, the backup circuit 2 is used as a hot backup working state, and the working state of the master circuit is periodically monitored. When the primary circuit 1 breaks down, the backup circuit 2 is automatically switched to work, and seamless handover of work tasks is realized;
the master circuit central control CPU unit 11 in the master circuit 1 is responsible for communication between the central controller and the system master station, forwards a control or query instruction of the system master station to the central controller, receives status and data information returned by the central controller, and uploads the status and data information to the system master station. The master circuit communication protocol analysis FPGA unit 12 analyzes the Profibus DP protocol, and performs protocol analysis on Profibus DP format data issued by a system master station, converts the Profibus DP format data into a data format which can be read and understood by the master circuit central control CPU unit 11 and stores the data format for the master circuit central control CPU unit 11 to read; carrying out protocol conversion on data uploaded by a master circuit central control CPU unit 11, converting the data into a Profibus DP protocol, and uploading the data to a Profibus DP bus for calling and monitoring by a system master station;
when the master circuit 1 fails, the backup circuit 2 is automatically switched to work, and the working principle of the backup circuit level and difference conversion unit 24, the backup circuit central control CPU unit 21 and the backup circuit communication protocol analysis FPGA unit 22 in the backup circuit 2 is the same as that of the master circuit level and difference conversion unit 14, the master circuit central control CPU unit 11 and the master circuit communication protocol analysis FPGA unit 12 in the master circuit 1.
Referring to fig. 3, the data receiving/transmitting unit 3 is provided with a data receiving/transmitting circuit; the data transmitting and receiving circuit is connected with a wired driver receiver chip; the line driver receiver chip is provided with a plurality of pins; the BUS-RXD pins and the BUS-TXD pins are used for receiving BUS data and sending the data to the BUS; STM32-RXD and STM32-TXD pins are connected with a master circuit control chip and used for receiving and sending data;
the type of the line driver receiver chip is not unique, and a MAX3232IDR type chip is preferably selected.
Referring to fig. 1, 4, 5 and 6, a master circuit control chip is disposed in the master circuit central control CPU unit 11; the master circuit control chip is provided with a plurality of pins; wherein, the pins of MASTER-TXD and MASTER-RXD are connected with J3 in the first plug connector; the JTDO pin is used for testing the inside of the chip; STM32-RXD and STM32-TXD pins are connected with a line driver receiver chip;
the MASTER circuit 1 is connected with the backup circuit 2 through a serial transceiving data line connected with two pins of MASTER _ RXD and MASTER _ TXD. The master circuit 1 and the backup circuit 2 periodically receive monitoring signals sent by the other party, and if the monitoring signals are not received, one party can be judged to have a fault. When the master circuit 1 is repaired, the master circuit 1 is switched to work.
The model of the master circuit control chip is not unique, and an STM32F103ZET6 model chip is preferably selected.
Referring to FIG. 7, pins 486-A S and 486-B S of the second plug connector are connected to the backup circuit isolator chip; and pins of MASTER-TXD and MASTER-RXD in the J2_ S in the second plug connector are connected with the backup circuit control chip.
Referring to fig. 8, a master isolation converting circuit is disposed in the master circuit level and differential converting unit; the master isolation conversion circuit is connected with a master circuit isolator chip; the master circuit isolator chip is provided with a plurality of pins; wherein 486-B and 486-A are connected with J2 in the first plug connector;
the type of the master circuit isolator chip is not unique, and an ADM2486BRWZ type chip is preferably selected.
Specifically, referring to fig. 9, a master circuit protocol chip is disposed in the master circuit communication protocol parsing FPGA unit 12; the master circuit protocol chip is provided with a plurality of pins; pins of L _ REQ, L _ STA, R _ REQ and R _ STA are connected with a master circuit control chip;
the master circuit protocol chip is not unique in model, and a DSDPv1-1 reference chip is preferably selected.
In some embodiments of the Profibus bus dual-channel redundant communication module, the backup circuit protocol chip, the backup circuit isolator chip and the backup circuit control chip in the backup circuit 2 are located in the same circuit as the selected model and the master circuit.
The above-mentioned embodiments are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art without departing from the spirit of the present invention should fall within the scope of the present invention defined by the claims.
Claims (10)
1. A Profibus bus double-channel redundant communication module comprises a primary circuit (1) and a backup circuit (2) which are electrified and operated simultaneously and are communicated with a system main station; the device is characterized by also comprising a data receiving and sending unit (3); the master circuit (1) comprises a master circuit communication protocol analysis FPGA unit (12); the backup circuit (2) comprises a backup circuit communication protocol analysis FPGA unit (22); the data receiving and sending unit (3) is respectively connected with the master circuit (1) and the backup circuit (2); the main circuit (1) is connected with the backup circuit (2).
2. A Profibus bus dual channel redundant communication module according to claim 1, wherein the master circuit (1) further comprises a master circuit level and differential conversion unit (14) and a master circuit central control CPU unit (11) connected in series; and the master circuit communication protocol analysis FPGA unit (12) is connected with the master circuit central control CPU unit (11).
3. A Profibus bus dual channel redundancy communication module according to claim 1, wherein the backup circuit (2) further comprises a backup circuit level and differential conversion unit (24) and a backup circuit central control CPU unit (21) connected in series; the backup circuit communication protocol analysis FPGA unit (22) is connected with the backup circuit central control CPU unit (21).
4. A Profibus bus dual channel redundancy communication module according to claim 1, wherein the master circuit (1) further comprises a master circuit power supply unit (13); and the master circuit power supply unit (13) is respectively connected with the master circuit central control CPU unit (11), the master circuit communication protocol analysis FPGA unit (12) and the master circuit level and difference conversion unit (14).
5. A Profibus bus dual channel redundant communication module according to claim 1, wherein the backup circuit (2) further comprises a backup circuit power supply unit (23); the backup circuit power supply unit (23) is respectively connected with the backup circuit central control CPU unit (21), the backup circuit communication protocol analysis FPGA unit (22) and the backup circuit level and differential conversion unit (24).
6. The Profibus bus dual-channel redundancy communication module as claimed in claim 1, wherein the data transceiver unit (3) is provided with a data transceiver circuit; the data transmitting and receiving circuit is connected with the wired driver receiver chip.
7. The Profibus bus dual-channel redundant communication module as claimed in claim 1, wherein a master circuit protocol chip is provided in the master circuit communication protocol parsing FPGA unit (12); and a backup circuit protocol chip is arranged in the backup circuit communication protocol analysis FPGA unit (22).
8. The Profibus bus dual channel redundancy communication module of claim 2, wherein a master isolation switching circuit is provided in the master level and differential switching unit (14); the master isolation conversion circuit is connected with a master circuit isolator chip; and a master circuit control chip is arranged in the master circuit central control CPU unit (11).
9. The Profibus bus dual channel redundant communication module of claim 3, wherein a backup isolation switching circuit is disposed in the backup circuit level and differential switching unit (24); the backup isolation conversion circuit is connected with a backup circuit isolator chip; and a backup circuit control chip is arranged in the backup circuit central control CPU unit (21).
10. The Profibus bus dual-channel redundant communication module as claimed in claim 1, wherein the data receiving and transmitting unit (3) is connected to a Profibus dp bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123351611.5U CN217767435U (en) | 2021-12-28 | 2021-12-28 | Profibus bus double-channel redundant communication module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123351611.5U CN217767435U (en) | 2021-12-28 | 2021-12-28 | Profibus bus double-channel redundant communication module |
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| CN217767435U true CN217767435U (en) | 2022-11-08 |
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| CN202123351611.5U Active CN217767435U (en) | 2021-12-28 | 2021-12-28 | Profibus bus double-channel redundant communication module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115498757A (en) * | 2022-11-17 | 2022-12-20 | 南京芯驰半导体科技有限公司 | Power management chip, power management method, electronic equipment and vehicle |
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2021
- 2021-12-28 CN CN202123351611.5U patent/CN217767435U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115498757A (en) * | 2022-11-17 | 2022-12-20 | 南京芯驰半导体科技有限公司 | Power management chip, power management method, electronic equipment and vehicle |
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