CN217655544U

CN217655544U - Circuit structure, quantum chip and quantum computer

Info

Publication number: CN217655544U
Application number: CN202221641517.5U
Authority: CN
Inventors: 赵勇杰; 马亮亮
Original assignee: Origin Quantum Computing Technology Co Ltd
Current assignee: Origin Quantum Computing Technology Co Ltd
Priority date: 2022-06-28
Filing date: 2022-06-28
Publication date: 2022-10-25
Anticipated expiration: 2032-06-28

Abstract

The application discloses circuit structure, quantum chip and quantum computer belongs to quantum chip and makes the field. The circuit structure is provided with at least two junction units, each junction unit comprises a first electrode and a plurality of second electrodes which are vertically and horizontally overlapped with the first electrode, and barrier layers are arranged at the vertically and horizontally overlapped positions, so that Josephson junctions are formed at the staggered positions. The junction elements in the circuit arrangement are thus arranged in a mirror-symmetrical manner. The junction units arranged in the form are beneficial to the layout of circuits in the quantum chip, and the wiring difficulty is reduced.

Description

Circuit structure, quantum chip and quantum computer

Technical Field

The application belongs to the field of quantum chip preparation, and particularly relates to a circuit structure, a quantum chip and a quantum computer.

Background

The quantum computation is a novel computation mode for regulating and controlling quantum information units to perform computation according to a quantum mechanics law. The traditional theoretical model of the general computer is a general turing machine; correspondingly, the theoretical model of the general quantum computer is a general turing machine which is re-interpreted by the laws of quantum mechanics.

With respect to the problem of computability, quantum computers can solve the problems that conventional computers can solve. However, in terms of computational efficiency, due to the quantum mechanical superposition, some known quantum algorithms are faster than conventional general purpose computers in processing specific problems.

One of the key components in quantum computers is the quantum chip. As a core part of a quantum computer, a quantum chip is a hardware device that performs quantum computation and quantum information processing.

One important type of quantum chip, superconducting quantum chip, utilizes a superconducting circuit formed by josephson junctions to implement a two-level system. The current mainstream adopts aluminum materials, and the control is realized by microwave signals by etching circuit shapes on the aluminum films.

The superconducting quantum chip has the following advantages:

1. the operand is large. The superconducting qubits have long coherence times, fast operating speeds, high fidelity, and can achieve thousands of operations overall.

2. The process is mature. Compared with other solid quantum chip systems, the superconducting quantum bit is less affected by the defects of materials, and can realize mass production by utilizing mature nano processing technology.

3. And the expandability is good. The superconducting qubit has simple structure, convenient regulation and control, and easy expansion.

Despite the above advantages, as the number of bits of chip integration is continuously increased, the difficulty of wiring in quantum chips is increased under the application requirement of limited chip volume.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application discloses a circuit structure, a quantum chip and a quantum computer. The circuit structure provides an optimized arrangement of the Josephson junctions, so that the circuit structure has the potential to be applied to arranging more Josephson junctions under the same chip size. Therefore, by adopting the scheme of the circuit structure, more qubits can be distributed in the quantum chip, and the wiring difficulty of peripheral circuits of the qubits is not obviously increased.

The scheme exemplified in the present application is implemented as follows.

In a first aspect, examples of the present application propose a circuit structure applied to a quantum computing system of multiple quantum bits, which includes at least two junction units, and any two junction units of the at least two junction units are distributed in a mirror-symmetric manner. Each junction unit comprises a first electrode and at least one second electrode, the second electrodes are arranged in parallel and spaced with each other when the number of the at least one second electrode is more than two, the second electrodes are provided with a first end part and a second end part which are far away from each other, and the first end part of each second electrode is respectively overlapped with the first electrode in a longitudinal and transverse mode; the circuit structure further includes a barrier layer between the first and second electrodes at the longitudinal and lateral overlap locations, such that a josephson junction is formed by the first, barrier and second electrodes together at each overlap location.

The various lines in a quantum chip (e.g., read lines, control lines, and transmission lines, etc.) are laid out primarily "around" the qubit. Thus, the distribution of qubits is rather restrictive or restrictive to the various wiring layouts in the qubit, or affecting each other. In other words, the distribution of qubits is an important basis and reference for the arrangement of other circuits or components in a quantum chip. And, with the increasing number of quantum bits in the quantum chip, the corresponding lines will be more and more. This causes a problem that wiring difficulty is drastically increased when a quantum chip is manufactured.

In the above circuit structure, each junction unit may form a josephson junction by the first electrode, the barrier layer, and the second electrode, and thus may serve as a core component for constructing a superconducting qubit. For qubits, especially superconducting qubits, the josephson junction is an important component and also requires care in their layout. Therefore, in the case of pursuit of multi-qubit integration, in the present application, the inventors chose to adopt the optimized junction unit layout structure, so as to reduce the wiring difficulty accordingly, and also introduce more qubits in the qubit at the same time, thereby also improving the integration level of the qubits in the qubit.

In the example of the present application, the inventors arrange the junction units in a mirror distribution manner, so that various peripheral lines and various devices in the quantum chip, which are in matching connection with the qubits, can be configured more. And therefore, the peripheral circuits do not need to be specially routed in consideration of avoiding factors such as crossing, and the layout of the circuits is more flexible.

According to some examples of the application, the number of the first electrodes in each junction unit is one and the number of the second electrodes is two, such that there are two josephson junctions in each junction unit.

According to some examples of the application, the number of the first electrodes is one and the number of the second electrodes is two, such that there are two josephson junctions in each junction unit, and the first electrode has a first segment, a second segment, and a third segment connected in series in each junction unit, the first segment and the third segment being equal in length, the second segment being located between the two second electrodes in each junction unit, wherein one of the two second electrodes is located between the first segment and the second segment, and the other of the two second electrodes is located between the second segment and the third segment.

According to some examples of the present application, the at least two knot units are three knot units, and the three knot units are arranged in a delta-shape.

According to some examples of the present application, the at least two junction units are four junction units; the circuit structure defines a plane rectangular coordinate system, and the four junction units are respectively positioned in a first quadrant, a second quadrant, a third quadrant and a fourth quadrant of the rectangular coordinate system.

According to some examples of the present application, the circuit structure defines a distribution reference point as a distribution basis of at least two junction units, and an inner layer area or an outer layer area outside the inner layer area with the distribution reference point as a center;

at least two junction units are distributed around the distribution reference point, and each junction unit is arranged in a manner that the corresponding first electrode and the first end portion are located in the inner layer area and the corresponding second end portion of the second electrode is located in the outer layer area.

According to some examples of the present application, the circuit structure further comprises a first electrical component and a plurality of second electrical components;

wherein the first electrical element is connected with the first electrode;

the plurality of second electrical elements are respectively connected with the at least one second electrode in a one-to-one correspondence manner, and the connection position is located at the second end part of the second electrode.

According to some examples of the present application, the first electrical component is made of aluminum, niobium, or titanium nitride;

alternatively, the second electrical element is made of aluminum, niobium or titanium nitride.

According to some examples of the present application, the first electrical element and the second electrical element are in a coplanar configuration.

In a second aspect, examples of the present application provide a quantum chip including a substrate, and a read bus, a read resonant cavity, a microwave control line, and a flux bias line disposed on the substrate. The quantum chip further comprises a plurality of bit capacitors and the circuit structure. At least two junction units in the circuit structure correspond to the bit capacitors one to one. The first electrode of the circuit structure is connected with the bit capacitor of the qubit in a matching manner, the second electrode of the circuit structure is connected with the magnetic flux bias line in a matching manner, and the microwave control line is connected with the bit capacitor in a matching manner.

In a third aspect, the present application provides a quantum computer, including the foregoing circuit structure or the foregoing quantum chip.

Has the advantages that:

compared with the prior art, the circuit structure in the example of the application arranges the junction units formed with the Josephson junctions in a mirror symmetry mode, so that more selectable layout design schemes are provided for manufacturing of the quantum chip, and the circuit structure based on the arrangement mode can integrate more quantum bits in the quantum chip, and meanwhile, the difficulty in layout of various circuits in the quantum chip is not obviously improved. That is, the application of the circuit structure of the present example to quantum chip manufacturing can realize the integration of multiple quantum bits (e.g., at least two) at lower cost (e.g., reduced wiring difficulty).

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the prior art of the present application, the drawings used in the embodiments or the prior art description will be briefly described below.

Fig. 1 is a schematic structural diagram of a knot unit according to an embodiment of the present disclosure;

FIG. 2 is a schematic view of the structure of a Josephson junction at section A in the junction unit of FIG. 1;

FIG. 3 is a schematic diagram of a first circuit structure having two junction units shown in FIG. 1 according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a first circuit structure having three junction units shown in FIG. 1 according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a first circuit structure having four junction units shown in FIG. 1 according to an embodiment of the present disclosure;

FIG. 6 discloses two arrangements of the circuit structure of four junction units shown in FIG. 1;

fig. 7 is a schematic structural diagram of a junction unit configured with a first electrical component and a second electrical component simultaneously according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a circuit structure having two junction units shown in fig. 7 according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of a quantum chip configured based on the circuit structure shown in fig. 8 in an embodiment of the present application;

fig. 10 discloses a schematic diagram of the structure of the junction unit shown in fig. 7 in the quantum chip shown in fig. 9 cooperating with various circuits in the quantum chip.

Icon: a 20-junction unit; a 10-junction unit; 11-a first electrode; 12-a second electrode; 121-a first end portion; 122-a second end; 13-a barrier layer; 201-a first electrical component; 202-a second electrical component; 500-quantum chips; 501-bit capacitance; 502-microwave control line; 503-flux bias lines; 504-read cavity.

Detailed Description

In the problem of how to improve the integration of quantum chips, practitioners have made many meaningful attempts to continually increase the number of qubits in a single quantum chip. Due to the particularity of qubits, various lines and devices are typically required to be configured in a qubit chip for each qubit in order to control the qubit and read its state information. Furthermore, matching, such as coupling, between the qubits also requires the provision of corresponding lines. However, the design and fabrication of quantum chips are faced with some problems to be solved. With the further increase in the number of qubits, various circuit and device configurations have been difficult to implement easily or at acceptable cost. Therefore, as the number of qubits in a chiplet increases, the volume of the chiplet also increases accordingly, based on wiring requirements and the like.

Such a contradiction arises on the basis of the above-mentioned reality:

it is required to integrate more qubits in a quantum chip at a sufficiently small volume size. However, the integration of multiple qubits increases the wiring difficulty, and the size of the quantum chip needs to be increased to alleviate such a dilemma. However, it is a general pursuit in the industry that the volume of quantum chips is smaller within an acceptable range.

Therefore, attempts have been made to optimize the wiring of the lines therein, such as by changing the design architecture of the quantum chip. While these attempts have progressed in some circumstances, there is still a need to develop additional alternatives.

In view of this, unlike some current schemes, in the present example, the inventor proposes a scheme that can be used to improve the integration degree of qubits without changing the layout of the main wiring structure in the quantum chip.

In practice, the quantum chip fabrication process adopted by the inventors of the present application is roughly as follows:

firstly, preparing a control circuit of equivalent qubits of a resonant cavity and a transmission line, then preparing a Josephson junction by adopting an electron beam exposure scheme, and then forming electrical connection between the Josephson junction and other structures in the qubit by a series of processes such as electron beam exposure.

Therefore, if the volume of the quantum chip is not changed or increased significantly, integrating more qubits would mean a great deal of redesign and modification of the control lines such as the resonant cavity, the transmission line, and other components. These redesigns and modifications may require a significant amount of effort and may even be difficult to implement, such as at too high an engineering cost or at too low a yield, etc. In this regard, there would be significant technical and cost advantages if more qubits could be inherited in an existing quantum chip volume at a lesser cost.

Under such a real demand, through research and analysis, the inventors propose a circuit structure that can be used to fabricate a quantum computing system having multiple qubits, and thus can also reduce the wiring difficulty of the quantum computing system having multiple qubits during fabrication.

Hereinafter, the description will be made with reference to the accompanying drawings, and refer to fig. 1 to 10 together.

In general, the circuit structure of the present example relates to a scheme of a multi-junction (josephson junction) arrangement, that is, the circuit structure includes a plurality of junction units 10, and the number of the junction units 10 is at least two. The node units 10 are laid out and constructed in a mirror image distribution mode; any two adjacent junction cells 10 in the circuit structure in the example are distributed in a mirror-symmetrical manner.

For ease of understanding and explanation, the junction unit 10 in the example will be described first.

The junction unit 10 includes a first electrode 11 and a second electrode 12, which are coupled to each other. The number of the first electrodes 11 and the at least one second electrode 12 is matched in each junction unit 10. The at least one second electrode 12 may be, for example, one, two, three, four or more; the example is mainly illustrated in a manner that two second electrodes 12 are collocated with one first electrode 11. In addition, when a plurality of second electrodes 12 are provided in one junction unit 10, the respective second electrodes 12 are arranged in a parallel arrangement, and the respective second electrodes 12 are spaced apart from each other, that is, the second electrodes 12 are not in contact with each other. In some of the illustrated structures of the present application, the junction unit 10 has two second electrodes 12, and the second electrodes 12 are arranged in parallel at intervals.

Further, in the junction unit 10, the first electrode 11 and the second electrode 12 are crossed in a vertical and horizontal direction to form a structural region (or a vertical and horizontal overlapping region, not shown) such as a cross shape. The illustrated structure of the present application has the first electrode 11 and the second electrode 12 perpendicular to each other. And the first electrode 11 and the second electrode 12 in the example are respectively configured as a strip-like structure or an elongated strip-like structure. Based on this, the second electrodes 12 are described to have the first end portions 121 and the second end portions 122 in the extending direction/length direction thereof, and in correspondence to this, the respective second electrodes 12 are arranged with the first end portions 121 criss-cross with the first electrodes 11.

In addition to this, the circuit structure includes a barrier layer 13. The barrier layer 13 is disposed at a position where it overlaps vertically and horizontally, and is located between the first electrode 11 and the second electrode 12. Thereby, a Josephson Junction (Josephson Junction) is collectively constituted by the first electrode 11, the barrier layer 13, and the second electrode 12 at each overlapping position.

The electrodes and barrier layers may be selected from a variety of suitable materials depending on the application of the circuit structure. For example, in general, a josephson junction may be composed of two superconductors that are weakly connected to each other. The weak connection may be, for example, a thin insulating layer. The josephson junction formed at this time may be referred to as a superconductor-insulator-superconductor junction. Thus, the first electrode 11 and the second electrode 12 may be superconductors, and the barrier layer 13 is selected to be an insulator. As a specific and optional example, the first electrode 11 and the second electrode 12 may be respectively selected to be aluminum, and the barrier layer 13 may be selected to be aluminum oxide. The first electrode 11 and the second electrode 12 may be made of other materials such as niobium and titanium nitride, respectively. The josephson junction may also be of niobium/aluminium-alumina/niobium construction. In addition, the Josephson junction may have a structure of NbN/AlN/NbN. It should be understood that the materials of the first electrode 11, the second electrode 12, and the barrier layer 13 may be appropriately selected in different cases according to the type of the quantum chip 500, and the present application is not particularly limited thereto.

An exemplary scheme in which one junction unit 10 has one number of first electrodes 11 and two number of second electrodes 12 is disclosed in fig. 1. Meanwhile, two josephson junctions exist in one junction unit 10 shown in fig. 1 in conjunction with the barrier layer 13 shown in fig. 2 disposed at the crisscross position of each of the first electrode 11 and the second electrode 12.

In fig. 1, the first electrode 11 and the second electrode 12 are substantially linear stripe structures, and intersect perpendicularly. In addition, two of the second electrodes 12 also divide the first electrode 11 into three portions, which will be clarified by the following description. The first electrode 11 is defined to have a first segment, a second segment and a third segment connected in sequence, and the three segments can be selected as an integral structure. In particular, in some examples, the lengths of the first and second segments are equal. For this purpose, the second section of the first electrode 11 is arranged between the two second electrodes 12 of the junction unit 10. Accordingly, one second electrode 12 in the junction unit 10 is located between the first segment and the second segment, while the other second electrode 12 in the junction unit 10 is located between the second segment and the third segment. In other words, in some examples, the junction unit 10 of the foregoing structure is an axisymmetric pattern about the center line of the first electrode 11.

In other examples, to facilitate application of the circuit structure to the quantum chip 500, corresponding configuration electrical components (conductive materials, which may be used for transmitting signals) may also be selected in the circuit structure so as to configure the josephson junction in the circuit structure into the quantum chip 500. Therefore, the circuit structure may further include a first electrical component 201 and a plurality of second electrical components 202. The first electrical component 201 and the second electrical component 202 may be disposed in a coplanar manner or in an out-of-plane manner, depending on the distribution of the two components.

The first electrical element 201 is connected to the first electrode 11. The second electrical element 202 is connected to the second electrode 12. The second electrical element 202 is also connected to each second electrode 12 of the junction unit 20. Since the second electrode 12 is connected to the first electrode 11 through the first end portion 121, the second electrical component 202 can be selectively connected to the second end portion 122 of the second electrode 12 in consideration of the layout of the circuit, as shown in fig. 7.

In fig. 7, two second electrodes 12 in one junction unit 20 are respectively and independently connected to one second electrical component 202. However, in other embodiments, two second electrical components 202 may be combined into a single body, so that the second electrical components 202 are a single body structure. It can be known that, when a plurality of second electrodes 12 are disposed in one junction unit 20, and each second electrode 12 is connected to the second electrical component 202, all the second electrical components 202 corresponding to one junction unit 20 can be integrated, and then connected to each second electrode 12.

Based on the junction unit 20 having the first electrical component 201 and the second electrical component 202 shown in fig. 7, when a circuit structure is formed by two junction units 20 of such a structure in cooperation, it can be shown in a structure as shown in fig. 8.

In addition, for the junction unit 10 (as shown in fig. 1) without the first electrical component 201 and the second electrical component 202 in some examples, the following circuit structures are provided.

An exemplary circuit structure based on the junction unit 10 shown in fig. 1 and 2 is composed of two junction units 10, for example, and the structure is shown in fig. 3.

Based on the junction unit 10 shown in fig. 1 and 2, an exemplary circuit structure is formed of three junction units 10, for example, which are arranged in a delta-shape in the overall structure, and see fig. 4.

Based on the junction unit 10 shown in fig. 1 and 2, an exemplary circuit structure is, for example, constituted by four junction units 10, the overall structure of which is arranged

Font, please refer to FIG. 5. In other words,the circuit configuration defines a rectangular plane coordinate system, and therefore, in this case, the aforementioned four junction units 10 are respectively located in the first quadrant, the second quadrant, the third quadrant, and the fourth quadrant of the rectangular plane coordinate system.

In addition, it is worth pointing out that, in the circuit structure, the respective junction units 10 may take a configuration in which the first electrodes 11 are located in a common region. For example, the first electrode 11 is located on the inner ring layer; or the first end 121 of the second electrode 12, is located in the inner ring layer. That is, the respective junction units 10 are arranged dispersedly substantially around one center, and the first electrodes 11 in the respective junction units 10 are closer to the aforementioned center, while the second ends of the second electrodes 12 in the respective junction units 10 are farther from the aforementioned center.

For example, in the above-described examples of the circuit structures shown in fig. 3 to 5, the circuit structure is set to define the distribution reference point that is the basis of the distribution of at least two junction units 10. Then the area within the circuit structure (e.g., when it is drawn as a circuit layout) may be bounded by an inner region centered on the distributed reference point or an outer region outside the inner region.

Further, based on this definition, the respective junction cells 10 in the circuit structure are distributed around the distribution reference point. And the respective junction units 10 are arranged in such a manner that the first end portions 121 of the respective first and

second electrodes

11 and 12 are located at inner regions and the second end portions 122 of the respective second electrodes 12 are located at outer regions, respectively.

In a specific and alternative example, taking a circuit structure with four junction units 10 as an example, fig. 6 shows two arrangements. Wherein, D represents the arrangement mode that the first end portions 121 of the first electrode 11 and the second electrode 12 are located in the inner layer region and the second end portions 122 of the corresponding second electrodes 12 are located in the outer layer region; figure E shows the arrangement in which the first ends 121 of the first and

second electrodes

11, 12 are located in the outer region and the corresponding second ends 122 of the second electrodes 12 are located in the inner region.

On the basis of the circuit structure illustrated in the present application, the inventor also proposes a quantum chip 500 as an application example, and the structure thereof is as shown in fig. 9 and 10. The quantum chip 500 includes a substrate, a read bus (not shown), a read cavity 504, a microwave control line 502, and a flux bias line 503. And wherein the read bus, read cavity 504, microwave control line 502 and flux bias line 503 are each disposed at appropriate locations on the substrate. The read bus, the read resonant cavity 504, the microwave control line 502, and the magnetic flux bias line 503 may be implemented by various embodiments disclosed in the art, respectively, and are not described in detail in this application. For example, the read bus and the read cavity 504 may be implemented by a coplanar waveguide transmission line or a structurally modified and improved product thereof, respectively.

Further, the quantum chip 500 further includes a circuit structure and a plurality of bit capacitors 501. Meanwhile, the junction units 20 (or the junction units 10) in the circuit structure correspond to the bit capacitors 501 one by one, so that at least two junction units 20 (or the junction units 10) in the circuit structure are equal in number to the bit capacitors 501. In addition, as a matched implementation manner, the first electrode 11 in the circuit structure is matched and connected with the bit capacitor 501, the second electrode 12 in the circuit structure is matched and connected with the magnetic flux bias line 503, and the microwave control line 502 is matched and connected with the bit capacitor 501.

As a method of manufacturing the above-described quantum chip 500, it can be briefly described as follows:

first, an electronic layout of the quantum chip 500 is drawn, and the electronic layout is manufactured by projection, so that various structures, such as a read bus, a read resonant cavity 504, a microwave control line 502, a magnetic flux bias line 503, and the like, in the quantum chip 500, except for the junction unit 10, are manufactured. On the basis of which a circuit structure constructed by the junction unit 10 in a mirror-symmetrical manner is then produced by means of evaporation, photolithography and the like. Further, the josephson junctions in the junction unit are matched-connected to the respective structures — either by wire connection or contactless coupling, or the like.

Wherein the evaporation is performed in the junction element 10 by a skew evaporation method. Since the junction unit 10 in the present example includes the first electrode 11 and the second electrode 12, which are arranged in a crisscross manner, it is possible to select the preparation by triple oblique evaporation.

Taking the junction unit 10 shown in fig. 1 as an example, according to the orientation shown in fig. 1, two second electrodes 12 can be formed by oblique evaporation along the horizontal direction (first oblique evaporation), then the first electrodes 11 can be formed by oblique evaporation from bottom to top along the vertical direction (second oblique evaporation), and then the additional coating film can be formed by oblique evaporation from top to bottom along the vertical direction (third oblique evaporation). After the josephson junction is fabricated, various lines may be connected to the electrodes in the josephson junction by photolithography and plating, for example, through the first and second electrical elements described above.

The third oblique evaporation is adopted to consider that the second electrode 12 manufactured by the first oblique evaporation causes blocking during the second oblique evaporation, so that the material of the first electrode 11 cannot be manufactured in the area adjacent to the edge of the second electrode 12, and thus a breakpoint exists in the first electrode 11. Therefore, the electrode material can be supplemented to the break point by the third oblique evaporation supplementary coating, so as to obtain the first electrode 11 which is continuously distributed and has no break point.

In addition, it is to be noted that, in addition to the first electrode 11 and the second electrode 12, the barrier layer 13 is present between them in the josephson junction, and therefore, the description of the formation process of the barrier layer 13 is omitted in order to avoid redundancy in the process of preparing the josephson junction described above.

Therefore, on the basis of obtaining the quantum chip 500, various peripheral control devices (such as refrigerants, microwave sources and the like) and various electronic components are combined, and a quantum computer can be constructed.

The embodiments described above with reference to the drawings are exemplary only for the purpose of illustrating the present application and are not to be construed as limiting the present application. In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the foregoing description explains the embodiments of the present application in detail with reference to the drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The division of the examples is for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be mutually incorporated and referred to each other without contradiction.

It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.

Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are intended to be only preferred embodiments of the present application, but the present application is not limited to the embodiments shown in the drawings, and all equivalent embodiments that can be modified or changed according to the spirit of the present application are intended to be covered by the present application.

Claims

1. A circuit structure applied to a quantum computing system with a plurality of quantum bits is characterized in that the circuit structure comprises at least two junction units, and any two junction units in the at least two junction units are distributed in a mirror symmetry mode;

each junction unit comprises a first electrode and at least one second electrode, when the number of the at least one second electrode is more than two, the second electrodes are arranged in parallel and at intervals, the second electrodes are provided with a first end part and a second end part which are far away from each other, and the first end part of each second electrode is respectively overlapped with the first electrode in a longitudinal and transverse mode;

the circuit structure also includes a barrier layer at the vertical and horizontal overlaps and between the first and second electrodes, collectively constituting a josephson junction from the first electrode, the barrier layer, and the second electrode at each overlap location.

2. The circuit structure of claim 1, wherein the number of first electrodes in each of the junction units is one and the number of second electrodes is two, such that there are two josephson junctions in each junction unit;

and/or the number of the first electrodes is one and the number of the second electrodes is two, so that there are two josephson junctions in each junction unit, and the first electrode has a first section, a second section and a third section connected in sequence in each junction unit, the first section and the third section are equal in length, and the second section is located between the two second electrodes in each junction unit, wherein one of the two second electrodes is located between the first section and the second section, and the other of the two second electrodes is located between the second section and the third section.

3. The circuit structure of claim 1 or 2, wherein the at least two junction units are three junction units, and the three junction units are arranged in a delta shape.

4. The circuit structure of claim 1 or 2, wherein the at least two junction units are four junction units;

the circuit structure is defined with a plane rectangular coordinate system, and the four junction units are respectively positioned in a first quadrant, a second quadrant, a third quadrant and a fourth quadrant of the plane rectangular coordinate system.

5. The circuit structure of claim 1, wherein the circuit structure defines a distribution reference point as a distribution basis of the at least two junction units, and an inner layer area centered on the distribution reference point or an outer layer area outside the inner layer area;

the at least two junction units are distributed around the distribution reference point, and each junction unit is arranged in such a manner that first end portions of the corresponding first and second electrodes are located in the inner layer region and second end portions of the corresponding second electrodes are located in the outer layer region.

6. The circuit structure of claim 1, further comprising a first electrical component and a plurality of second electrical components;

wherein the first electrical element is connected to the first electrode;

7. The circuit structure of claim 6, wherein the first electrical component is made of aluminum, niobium, or titanium nitride;

or, the second electrical element is made of aluminum, niobium or titanium nitride.

8. The circuit structure of claim 6 or 7, wherein the first electrical component and the second electrical component are in a coplanar configuration;

alternatively, the plurality of second electrical components are of an integrated structure.

9. A quantum chip, comprising a substrate, and a read bus, a read resonant cavity, a microwave control line and a magnetic flux bias line disposed on the substrate, wherein the quantum chip further comprises a plurality of bit capacitors and the circuit structure according to claims 1 to 8, wherein the at least two junction units in the circuit structure are in one-to-one correspondence with the plurality of bit capacitors, a first electrode of the circuit structure is connected to the bit capacitors in a matching manner, a second electrode of the circuit structure is connected to the magnetic flux bias line in a matching manner, and the microwave control line is connected to the bit capacitors in a matching manner.

10. A quantum computer comprising the circuit structure of any one of claims 1 to 6 or the quantum chip of claim 9.